KR940016505A - Contact formation method of semiconductor device - Google Patents

Contact formation method of semiconductor device Download PDF

Info

Publication number
KR940016505A
KR940016505A KR1019920027305A KR920027305A KR940016505A KR 940016505 A KR940016505 A KR 940016505A KR 1019920027305 A KR1019920027305 A KR 1019920027305A KR 920027305 A KR920027305 A KR 920027305A KR 940016505 A KR940016505 A KR 940016505A
Authority
KR
South Korea
Prior art keywords
contact
forming
diffusion region
etching
plug
Prior art date
Application number
KR1019920027305A
Other languages
Korean (ko)
Other versions
KR960010060B1 (en
Inventor
이근육
황성로
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR92027305A priority Critical patent/KR960010060B1/en
Publication of KR940016505A publication Critical patent/KR940016505A/en
Application granted granted Critical
Publication of KR960010060B1 publication Critical patent/KR960010060B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

본 발명은 n+콘택은 선택적 화학 증착법을 이용하여 텅스텐 박막으로 형성하고, p+콘택은 화학 증착법에 의해 TiCl4와 B2H6를 포함하고 있는 H2를 이용한 하여 Ti2B2박막을 형성하여 p+콘택 저항을 n+콘택 저항 수준으로 낮출 수 있는 반도체 소자의 콘택 형성 방법으로서, 제 1 및 제2 확산 영역(n+, p+)을 갖고 있는 기판(1)상에 절연막(4)을 증착한 다음, 식각에 의해 제 1 확산 영역(n+)의 콘택을 형성하기 위한 콘택홀을 형성하는 제 1 단계와, 선택적으로 제 1 금속층을 증착하여 제 1 확산 영역(n+)의 콘택 플러그를 형성하는 제 2 단계와, 식각에 의해 제 2 확산 영역(p+)의 콘택을 형성하기 위한 콘택홀을 형성하는 제 3 단계와, 화학증착법을 이용하여 전면적으로 제 2 금속층을 증착하여 제 2 확산 영역(p+)의 콘택 플러그를 형성하는 제 4 단계와, 화학적 기계적 방법(chemical and Mechanical Polishking)으로 표면을 평탄화하는 제 5 단계를 포함하는 것을 특징으로 한다.In the present invention, the n + contact is formed of a tungsten thin film using selective chemical vapor deposition, and the p + contact is formed of Ti 2 B 2 thin film using H 2 containing TiCl 4 and B 2 H 6 by chemical vapor deposition. A method for forming a contact in a semiconductor device capable of lowering a p + contact resistance to a level of n + contact resistance, wherein the insulating film 4 is formed on a substrate 1 having first and second diffusion regions n + and p + . After the deposition, the first step of forming a contact hole for forming a contact of the first diffusion region n + by etching, and optionally depositing a first metal layer to contact the first diffusion region (n + ) A second step of forming a plug, a third step of forming a contact hole for forming a contact of the second diffusion region p + by etching, and a second metal layer deposited on the entire surface by chemical vapor deposition A fourth step of forming a contact plug of the second diffusion region p + And a fifth step of planarizing the surface by chemical and mechanical polishing.

Description

반도체 소자의 콘택 형성 방법Contact formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명에 따른 반도체 콘택 형성 방법의 공정도.1 is a process diagram of a method for forming a semiconductor contact according to the present invention.

Claims (3)

확산층 종류별로 콘택 플러그를 별도로 형성하여 콘택 저항을 낮추기 위한 반도체 소자의 콘택 형성 방법에 있어서, 제1 및 제 2 확산 영역(n+, p+)을 갖고 있는 기판(1)상에 절연막(4)을 증착한 다음, 식각에 의해 제 1 확산 영역(n+)의 콘택을 형성하기 위한 콘택홀을 형성하는 제 1 단계와, 선택적으로 제 1 금속층을 증착하여 제 1 확산 영역(n+)의 콘택 플러그를 형성하는 제 2 단계와, 식각에 의해 제 2 확산 영역(p+)의 콘택을 형성하기 위한 콘택홀을 형성하는 제 3 단계와, 화학 증착법을 이용하여 전면적으로 제 2 금속층을 증착하여 제 2 확산 영역(p+)의 콘택 플러그를 형성하는 제 4 단계와, 화학적 기계적 방법(chemical and Mechanical Polishking)으로 표면을 평탄화하는 제 5 단계를 포함하는 것을 특징으로 확산층 종류별로 콘택 플러그를 별도로 형성하여 콘택 저항을 낮추기 위한 반도체 소자의 콘택 형성 방법에 있어서, 제1 및 제 2 확산 영역(n+, p+)을 갖고 있는 기판(1)상에 절연막(4)을 증착한 다음, 식각에 의해 제1 확산 영역(n+)의 콘택을 형성하기 위한 콘택홀을 형성하는 제 1 단계와, 선택적으로 제 1 금속층을 증착하여 제 1 확산 영역(n+)의 콘택 플러그를 형성하는 제 2 단계와, 식각에 의해 제 2 확산 영역(p+)의 콘택을 형성하기 위한 콘택홀을 형성하는 제 3 단계와, 화학 증착법을 이용하여 전면적으로 제 2 금속층을 증착하여 제 2 확산 영역(p+)의 콘택 플러그를 형성하는 제 4 단계와, 화학적 기계적 방법(chemical and Mechanical Polishking)으로 표면을 평탄화 하는 제 5 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택 형성 방법.In the method for forming a contact of a semiconductor device for forming a contact plug separately for each type of diffusion layer to lower contact resistance, the insulating film 4 is formed on the substrate 1 having the first and second diffusion regions n + and p + . After the deposition, the first step of forming a contact hole for forming a contact of the first diffusion region n + by etching, and optionally depositing a first metal layer to contact the first diffusion region (n + ) A second step of forming a plug, a third step of forming a contact hole for forming a contact of the second diffusion region p + by etching, and a second metal layer deposited on the entire surface by chemical vapor deposition And a fourth step of forming a contact plug of the second diffusion region p + , and a fifth step of planarizing the surface by chemical and mechanical polishing. In the contact method of forming a semiconductor device to reduce the tack resistance, the first and second depositing a diffusion region (n +, p +), the insulating film 4 on the substrate 1, which has by then etching the A first step of forming a contact hole for forming a contact of the first diffusion region n + , a second step of selectively depositing a first metal layer to form a contact plug of the first diffusion region n + , and A third step of forming a contact hole for forming a contact of the second diffusion region p + by etching, and depositing a second metal layer on the entire surface by chemical vapor deposition to contact the second diffusion region p + . And a fourth step of forming a plug and a fifth step of planarizing the surface by a chemical and mechanical polishing method. 제 1 항에 있어서, 상기 제 2 단계는 전면적으로 제 1 금속을 증착하고 후식각에 의해 제 1 확산 영역(n+)의 콘택 플러그를 형성하는 공정에 의해 수행되는 것을 특징으로 하는 반도체 소자의 콘택 형성 방법.The contact of a semiconductor device according to claim 1, wherein the second step is performed by depositing a first metal over the entire surface and forming a contact plug of the first diffusion region n + by post etching. Forming method. 제 1 항에 있어서, 상기 제 1 금속은 텅스텐이고, 상기 제 2 금속은 Ti2B2인 것을 특징으로 하는 반도체 소자의 콘택 형성 방법.The method of claim 1, wherein the first metal is tungsten, and the second metal is Ti 2 B 2 . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR92027305A 1992-12-31 1992-12-31 Contact forming method of semiconductor device KR960010060B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92027305A KR960010060B1 (en) 1992-12-31 1992-12-31 Contact forming method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92027305A KR960010060B1 (en) 1992-12-31 1992-12-31 Contact forming method of semiconductor device

Publications (2)

Publication Number Publication Date
KR940016505A true KR940016505A (en) 1994-07-23
KR960010060B1 KR960010060B1 (en) 1996-07-25

Family

ID=19348454

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92027305A KR960010060B1 (en) 1992-12-31 1992-12-31 Contact forming method of semiconductor device

Country Status (1)

Country Link
KR (1) KR960010060B1 (en)

Also Published As

Publication number Publication date
KR960010060B1 (en) 1996-07-25

Similar Documents

Publication Publication Date Title
MY132400A (en) Ruthenium silicide diffusion barrier layers and methods of forming same
US6815819B2 (en) In situ plasma pre-deposition wafer treatment in chemical vapor deposition technology for semiconductor integrated circuit applications
KR970072431A (en) Manufacturing method of nonvolatile semiconductor memory device
KR940020531A (en) Manufacturing method of metal plug in contact hole
KR930009023A (en) Contact filling method by two-step deposition of selective tungsten thin film
KR860700312A (en) Diffusion barrier layer for integrated circuit device and method of forming the same
KR950021526A (en) Semiconductor device and manufacturing method thereof
KR940010214A (en) Metal contact formation method of semiconductor device
KR940016505A (en) Contact formation method of semiconductor device
KR940001279A (en) Metal wiring formation method of semiconductor
KR970077648A (en) Method for manufacturing capacitor of semiconductor device
KR980006341A (en) Method for manufacturing capacitor of semiconductor device
KR950025868A (en) Bit line formation method of semiconductor device
KR930024106A (en) Contact Forming Method of Semiconductor Device
KR930005179A (en) Manufacturing Method of Semiconductor Device
KR960035803A (en) Manufacturing method of semiconductor device
KR940016774A (en) Method for manufacturing charge storage electrode of semiconductor device
KR970003858A (en) Conductive Film Formation Method Using Selective Vapor Deposition
KR950009930A (en) Metal wiring formation method of semiconductor device
JPH0254659B2 (en)
KR950001899A (en) Contact formation method during PLUG process
KR970072090A (en) Method for forming wiring layer of semiconductor device
KR970052389A (en) Contact hole formation method of semiconductor device
KR940016691A (en) Metal thin film deposition method of semiconductor device
KR930014803A (en) Contact buried method of two-stage selective deposition using TiN thin film

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080619

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee