KR970063497A - Method for forming a metal wiring layer - Google Patents

Method for forming a metal wiring layer Download PDF

Info

Publication number
KR970063497A
KR970063497A KR1019960004696A KR19960004696A KR970063497A KR 970063497 A KR970063497 A KR 970063497A KR 1019960004696 A KR1019960004696 A KR 1019960004696A KR 19960004696 A KR19960004696 A KR 19960004696A KR 970063497 A KR970063497 A KR 970063497A
Authority
KR
South Korea
Prior art keywords
layer
source
forming
tin
contact hole
Prior art date
Application number
KR1019960004696A
Other languages
Korean (ko)
Other versions
KR0176197B1 (en
Inventor
박창수
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960004696A priority Critical patent/KR0176197B1/en
Publication of KR970063497A publication Critical patent/KR970063497A/en
Application granted granted Critical
Publication of KR0176197B1 publication Critical patent/KR0176197B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명에 의한 반도체 소자의 금속 배선층 형성방법은, CVD-W 배선층 하부에 오믹층, 희생층, 밀착층을 두어 후속되는 고온의 열처리 공정에 의해 TiSi2층의 변형, 예컨데 응집(Agglomeration)현상 및 소오스/드레인 영역에 주입된 불순물 이온들의 외부 확산(Out-diffusion)을 억제하여 콘택홀에서의 급격한 저항 증가를 방지할 수 있고, 종래의 텅스텐 폴리사이드 구조에 비해 N+ 소오스/드레인 영역과 P+ 소오스/드레인 영역을 동시에 연결할 수 있다는 잇점이 있다.A metal wiring layer formed in a semiconductor device according to the present invention, CVD-W wiring lower the ohmic layer, the sacrificial layer, and deformation of the TiSi 2 layer is formed by the heat treatment of high temperature is subsequently placing the adhesive layer, for example coagulation (Agglomeration) developing and It is possible to prevent the out-diffusion of the impurity ions implanted into the source / drain regions, thereby preventing an abrupt increase in resistance in the contact hole. As compared with the conventional tungsten polycide structure, the N + source / drain region and the P + source / Drain regions can be connected at the same time.

Description

반도체 소자의 금속 배선층 형성 방법Method for forming a metal wiring layer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도 내지 제7도는 본 발명에 의한 반도체 소자의 금속 배선층 형성 방법을 순차적으로 도시한 단면도이다.2 to 7 are sectional views sequentially showing a method for forming a metal wiring layer of a semiconductor device according to the present invention.

Claims (9)

반도체 기판에 소오스/드레인 영역을 형성하는 단계; 상기 소오스/드레인 영역이 형성된 반도체 기판에 절연막을 증착하고 패터닝하여 상기 소오스/드레인 영역에 콘택홀을 형성하는 단계; 상기 소오스/드레인 영역이 노출된 콘택홀 바닥에 반응지연막을 형성하는 단계; 상기 결과물 전면에 오믹층(Ohmic Layer)을 얇게 증착하는 단계; 상기 결과물에 열처리 공정을 실시하여 상기 반응지연막과 오믹층이 접촉하는 상기 콘택홀 바닥에 화합물층을 형성하고, 상기 콘택홀 바닥을 제외한 상기 절연막 상에 미반응되어 남아있는 상기 오믹층을 제거하는 단계; 및 상기 결과물에 희생층(Sacrificial Layer), 밀착층(Glue Layer) 및 금속 배선층을 차례로 증착하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선층 형성 방법.Forming a source / drain region in a semiconductor substrate; Forming a contact hole in the source / drain region by depositing and patterning an insulating layer on the semiconductor substrate on which the source / drain region is formed; Forming a reaction delay film on the bottom of the contact hole where the source / drain region is exposed; Thinly depositing an ohmic layer on the entire surface of the resultant product; Performing a heat treatment process on the resultant to form a compound layer on the bottom of the contact hole where the reaction retardation layer and the ohmic layer are in contact with each other and removing the remaining unreacted ohmic layer on the insulating layer except for the bottom of the contact hole ; And depositing a sacrificial layer, a glue layer, and a metal interconnection layer on the resultant structure in this order. 제1항에 있어서, 상기 오믹층(Ohmic Layer)은 티타늄(Ti)을 얇게 증착하여 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선층 형성 방법.The method according to claim 1, wherein the ohmic layer is formed by depositing titanium (Ti) thinly. 제1항에 있어서, 상기 희생층의 재료로 SiH4, Si4H6등 중에서 어느 하나를 사용하는 것을 특징으로 하는 반도체 소자의 금속 배선층 형성 방법.The method according to claim 1, wherein any one of SiH 4 , Si 4 H 6 and the like is used as a material of the sacrificial layer. 제1항에 있어서, 상기 희생층은 650℃ 이하에서 저압화학기상증착(LPCVD;Low Pressure Chemical Vapor Deposition), 플라즈마화학기상증착(PE-CVD;Plasma Enhenced Chemical Vapor Deposition)중에서 어느 하나의 방법으로 형성되는 것을 특징으로 하는 반도체 소자의 금속 배선층 형성 방법.The method according to claim 1, wherein the sacrificial layer is formed by any one of low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PE-CVD) Wherein the metal wiring layer is formed on the semiconductor substrate. 제1항에 있어서, 상기 희생층은 1000A°이하의 두께를 가지는 것을 특징으로 하는 반도체 소자의 금속 배선층 형성 방법.The method of claim 1, wherein the sacrificial layer has a thickness of 1000 A or less. 제1항에 있어서, 상기 밀착층은 Ti양이 N양보다 많은 TiN층(Ti Rich TiN)과 Ti : N이 1 : 1인 TiN층의 이중구조를 가지는 것을 특징으로 하는 반도체 소자의 금속 배선층 형성 방법.The method according to claim 1, wherein the adhesion layer has a dual structure of a TiN layer (Ti rich TiN) having a Ti amount larger than the N amount and a TiN layer having a Ti: N ratio of 1: 1 Way. 제1항에 있어서, 상기 밀착층은 Ti양이 N양보다 많은 TiN층(Ti Rich TiN)과 N양이 Ti양보다 많은 TiN층(N Rich TiN)의 이중 구조를 가지는 것을 특징으로 하는 반도체 소자의 금속 배선층 형성 방법.2. The semiconductor device according to claim 1, wherein the adhesion layer has a dual structure of a TiN layer (Ti rich TiN) having a larger amount of Ti than N and a TiN layer (N Rich TiN) having a larger amount of N than Ti Of the metal wiring layer. 제1항에 있어서, 상기 희생층을 증착하기 저에 스퍼터(Sputter) 식각 공정을 실시하는 것을 특징으로 하는 반도체 소자의 금속 배선층 형성 방법.The method of forming a metal wiring layer of a semiconductor device according to claim 1, wherein a sputter etching process is performed on the bottom of the sacrificial layer. 제1항에 있어서, 상기 소오스/드레인 영역의 불순물이 P+형일 경우 상기 콘택홀을 형성하는 단계 후에 P+형 이온 주입 공정을 추가하여 실시하는 것을 특징으로 하는 반도체 소자의 금속 배선층 형성 방법.The method of claim 1, wherein the impurity of the source / drain region is P + type, and the P + type ion implantation process is further performed after forming the contact hole. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960004696A 1996-02-26 1996-02-26 Forming method of metal wiring layer in semiconductor device KR0176197B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960004696A KR0176197B1 (en) 1996-02-26 1996-02-26 Forming method of metal wiring layer in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960004696A KR0176197B1 (en) 1996-02-26 1996-02-26 Forming method of metal wiring layer in semiconductor device

Publications (2)

Publication Number Publication Date
KR970063497A true KR970063497A (en) 1997-09-12
KR0176197B1 KR0176197B1 (en) 1999-04-15

Family

ID=19451814

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960004696A KR0176197B1 (en) 1996-02-26 1996-02-26 Forming method of metal wiring layer in semiconductor device

Country Status (1)

Country Link
KR (1) KR0176197B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100458297B1 (en) * 1997-12-31 2005-02-24 주식회사 하이닉스반도체 Method for forming metal interconnection of semiconductor device to avoid generation of overhang and improve quality of layer and step coverage in contact hole
KR100604089B1 (en) 2004-12-31 2006-07-24 주식회사 아이피에스 Method for depositing thin film on wafer by in-situ

Also Published As

Publication number Publication date
KR0176197B1 (en) 1999-04-15

Similar Documents

Publication Publication Date Title
KR970063577A (en) Metal wiring structure and formation method
KR940020531A (en) Manufacturing method of metal plug in contact hole
KR970063497A (en) Method for forming a metal wiring layer
KR940018699A (en) TiSi_2 / TiN sheath interconnect technology
KR100313256B1 (en) Semiconductor device and manufacture method thereof
KR980005554A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR970072313A (en) Method of wiring semiconductor thin film
KR970018230A (en) Barrier metal formation method of metal wiring
KR970072084A (en) Method for forming a metal layer of a semiconductor
KR950025868A (en) Bit line formation method of semiconductor device
JPS62265718A (en) Manufacture of semiconductor device
KR970077199A (en) Method for forming wiring layer of semiconductor device
KR930005179A (en) Manufacturing Method of Semiconductor Device
KR0130865B1 (en) Manufacture of silicide film
KR970067861A (en) Semiconductor device and manufacturing method thereof
KR980005548A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR890016634A (en) Manufacturing Method of Semiconductor Device
JPS62130540A (en) Semiconductor device
KR930011111A (en) Contact manufacturing method using titanium silicide
KR910015008A (en) Metal wiring method
KR910013508A (en) Method of forming connection area using tungsten silicide
KR940001462A (en) Gate electrode formation method
KR970018231A (en) Metal wiring manufacturing method
KR940016791A (en) Capacitor Structure and Manufacturing Method of Semiconductor Memory Device
KR900010931A (en) Impurity diffusion prevention method of contact area

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20061030

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee