KR0130865B1 - Manufacture of silicide film - Google Patents
Manufacture of silicide filmInfo
- Publication number
- KR0130865B1 KR0130865B1 KR1019940013153A KR19940013153A KR0130865B1 KR 0130865 B1 KR0130865 B1 KR 0130865B1 KR 1019940013153 A KR1019940013153 A KR 1019940013153A KR 19940013153 A KR19940013153 A KR 19940013153A KR 0130865 B1 KR0130865 B1 KR 0130865B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- silicide
- forming
- layer
- polysilicon
- Prior art date
Links
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 27
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229910017855 NH 4 F Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 125000000896 monocarboxylic acid group Chemical group 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 자기 정렬 실리사이드 공정에 의한 반도체 소자의 실리사이드 형성방법에 관한 것으로, 실리콘 기판(21)상부에 웰(23)을 형성한 후 필드산화막(24)으로 소자를 격리하고 게이트산화막(25)을 형성한 후 n+폴리실리콘막(26), p+폴리실리콘막(27)을 증착하고 n+접합층, p+접합층(29)과의 격리를 위해서 스페이서산화막(30)을 형성하는 단계; 전체 구조 상부에 실리사이드화 가능한 금속막(31)을 형성한 다음, 상기 금속막 상부에 폴리실리콘막(33)을 형성하는 단계; 800℃ 내지 950℃의 고온에서 RTA 공정을 진행하여 실리사이드막(32)을 형성하는 단계; 상기 실리사이드막(32)을 선택제거하는 단계; 상기 폴리실리콘막(33)을 선택제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicide formation method of a semiconductor device by a self-aligned silicide process. The well 23 is formed on a silicon substrate 21, and the device is isolated by a field oxide film 24, and the gate oxide film 25 is removed. Forming the n + polysilicon layer 26 and the p + polysilicon layer 27 and forming a spacer oxide layer 30 for isolation from the n + junction layer and the p + junction layer 29; Forming a silicideable metal film 31 on the entire structure, and then forming a polysilicon film 33 on the metal film; Performing a RTA process at a high temperature of 800 ° C. to 950 ° C. to form a silicide film 32; Selectively removing the silicide layer (32); And selectively removing the polysilicon film 33.
Description
제1a도 내지 제1c도는 종래 기술에 의한 티타늄 실리사이드막 형성 공정 단면도.1A to 1C are cross-sectional views of a titanium silicide film forming process according to the prior art.
제2a도 내지 제2d도는 본 발명에 따른 일실시예의 실리사이드 막 형성 공정 단면도.2A to 2D are cross-sectional views of a silicide film forming process of one embodiment according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 21 : 실리콘 기판 2, 22 : P-웰1, 21: silicon substrate 2, 22: P-well
3, 23 : N-웰 4, 24 : 필드산화막3, 23: N-well 4, 24: field oxide film
5, 25 : 게이트 산화막 6, 26 : n+폴리실리콘막5, 25: gate oxide film 6, 26: n + polysilicon film
7, 27 : p+폴리실리콘막 8, 28 : n+접합층7, 27: p + polysilicon film 8, 28: n + bonding layer
9, 29 : p+접합층 10, 30 : 스페이서 산화막9, 29: p + junction layer 10, 30: spacer oxide film
11, 31 : 티타늄막 12, 32 : 실리사이드막11, 31: titanium film 12, 32: silicide film
33 : 폴리실리콘막33: polysilicon film
본 발명은 자기 정렬 실리사이드 공정에 의한 반도체 소자의 실리사이드 형성방법에 관한 것이다.The present invention relates to a method for forming silicide of a semiconductor device by a self-aligned silicide process.
일반적으로 반도체 소자 제조 공정에서 접합 저항 및 게이트 전극의 저항을 줄이기 위해 TiSi2, CoSi2등의 실리사이드를 이용한다. 이때 실리사이드는 자기정렬 실리사이드 공정 즉, 셀리사이드 공정에 의해 접합 영역 및 게이트전극 영역에만 형성되게 한다.In general, silicides such as TiSi 2 and CoSi 2 are used to reduce junction resistance and gate electrode resistance in a semiconductor device manufacturing process. In this case, the silicide is formed only in the junction region and the gate electrode region by a self-aligned silicide process, that is, a celyside process.
제1a도 내지 제1c도는 종래의 티타늄 셀리사이드 공정을 나타내는 단면도로, 이를 통하여 종래 기술을 설명하면 다음과 같다.1a to 1c is a cross-sectional view showing a conventional titanium celide process, it will be described in the prior art as follows.
먼저, 제1a도는 실리콘 기판(1) 상부에 P-웰(3)을 형성한 후 필드산화막(4)으로 소자를 격리하고 게이트 산화막(5)을 형성한 후 n+폴리실리콘막(6), p+폴리실리콘막(7)을 증착하고 n+접합층(8), p+접합층(9)과의 격리를 위해서 스페이서 산화막(10)를 형성한 상태의 단면도이다.First, in FIG. 1A, the P-well 3 is formed on the silicon substrate 1, the device is isolated by the field oxide film 4, the gate oxide film 5 is formed, and then n + polysilicon film 6, It is sectional drawing of the state which deposited the p + polysilicon film 7 and formed the spacer oxide film 10 for isolation | separation from the n + junction layer 8 and the p + junction layer 9.
다음으로, 제1b도에서 전체 구조 상부에 티타늄막(11)을 증착한 다음, 계속해서 제1c도에서 저온 RAT공정을 통해 상기 n+접합층(8), p+접합층(9), n+접폴리실리콘막(6), p+폴리실리콘막(7)영역에 티타늄 실리사이드(12)막이 형성되게 한 후 이들 영역(6,7,8,9)만 티타늄 실리사이드가 잔류하도록 식각 용액(NH4OH : H2O2: H2O =1 : 1 : 5)에서 티타늄(11)을 식각하고, 이후 고온 RTA공정을 실시한다.Next, the titanium film 11 is deposited on the entire structure in FIG. 1b, and then the n + junction layer 8, p + junction layer 9, n through the low temperature RAT process in FIG. 1c. After the titanium silicide 12 film is formed in the + contact polysilicon film (6) and p + polysilicon film (7) region, only the regions (6,7,8,9) are etch solution (NH). 4 OH: H 2 O 2 : H 2 O = 1: 1: 5) and titanium (11) is etched, and then a high temperature RTA process is performed.
그러나, 상기 종래 방법은 n+접합층 및 n+폴리실리콘막에 형성되는 티타늄 실리사이드의 두께는 p+접합층 및 p+폴리실리콘막위에 형성되는 티타늄실리사이드의 두께보다 훨씬 얇게 되어 후속의 고온 열공정(800℃이상)에서 n+접합층 및 n+폴리실리콘막위의 티타늄 실리사이드는 열적으로 불안정하여 n+접합층 및 n+폴리실리콘막의 전기적 특성이 후속의 열공정시 쉽게 열화되는 단점이 있다.However, in the conventional method, the thickness of the titanium silicide formed on the n + junction layer and the n + polysilicon film is much thinner than the thickness of the titanium silicide formed on the p + junction layer and the p + polysilicon film, and subsequent high temperature thermal process. titanium silicide of n + junction layer and the n + polysilicon in makwi (over 800 ℃) has a disadvantage that is thermally unstable and easily degraded n + junction layer and the n + polysilicon film, the electrical properties of the subsequent time to tear.
게다가 저온 RTA공정과 고온 RTA공정의 2단계 공정을 거쳐야 하므로 비경제적이다.In addition, it is uneconomical because it has to go through two stages of low temperature RTA and high temperature RTA.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 서로 다른형(type)의 전도막 상에 실리사이드 형성후 후속 열공정에서 실리사이드막의 열화를 방지하는 반도체 소자의 실리사이드막 형성방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method of forming a silicide film of a semiconductor device which prevents deterioration of the silicide film in a subsequent thermal process after forming the silicide on different types of conductive film. have.
상기 목적을 달성하기 위하여 본 발명은 자기정렬 실리사이드 공정에 의한 반도체 소자의 실리사이드막 형성방법에 있어서, 실리콘 기판 상부에 웰을 형성한 후 필드산화막으로 소자를 격리하고 게이트 산화막을 형성한 후 n+폴리실리콘막, p+폴리실리콘막을 증착하고 n+접합층, p+접합층과의 격리를 위해서 스페이서 산화막을 형성하는 단계; 전체 구조상부에 실리사이드화 가능한 금속막을 형성한 다음, 상기 금속막 상부에 폴리실리콘막을 형성하는 단계; 800℃ 내지 950℃의 고온에서 RTA공정을 진행하여 실리사이드막을 형성하는 단계, 상기 실리사이드막을 선택제거하는 단계; 상기 폴리실리콘막을 선택제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a silicide film of a semiconductor device by a self-aligned silicide process, after forming a well on a silicon substrate, isolating the device with a field oxide film and forming a gate oxide film, and then n + poly Depositing a silicon film, a p + polysilicon film, and forming a spacer oxide film for isolation from the n + junction layer and the p + junction layer; Forming a silicideable metal film on the entire structure, and then forming a polysilicon film on the metal film; RTA process at a high temperature of 800 ℃ to 950 ℃ to form a silicide film, the step of removing the silicide film; And selectively removing the polysilicon film.
이하, 첨부된 도면을 참조하여 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2d도는 본 발명의 일실시예에 따른 티타늄실리사이드 형성 공정단면도로, 먼저, 제2a도는 전술한 제1b도 구조하에서 화학기상증착법 또는 물리기상증착법으로 폴리실리콘막을 증착한 상태를 나타낸다.2A to 2D are cross-sectional views of a titanium silicide forming process according to an embodiment of the present invention. First, FIG. 2A shows a state in which a polysilicon film is deposited by chemical vapor deposition or physical vapor deposition under the above-described structure of FIG. 1B. .
이어서, 제2b도에서 C54구조의 티타늄실리사이드(32)가 형성될 수 있도록 800℃ 내지 950℃의 고온에서 RTA공정을 진행한다. 이렇게 고온에서 RTA 공정을 진행하면 티타늄실리사이드(32)는 n+폴리실리콘막(26), n+접합층(28)에서도, p+폴리실리콘막(27), p+접합층(29)에서와 거의 동일한 두께로 형성시킬 수 있는 장점이 있다. 또한 이렇게 하면 상기(26,27,28,29) 영역의 티타늄은 상기 영역의 실리콘 및 티타늄(31)위에 증착한 폴리실리콘막(33)은 티타늄(31)과 모두 반응치 못하고, 상기(26,27,28,29)영역위에 남아 있게 된다.Subsequently, the RTA process is performed at a high temperature of 800 ° C. to 950 ° C. so that the titanium silicide 32 having the C 54 structure may be formed in FIG. 2B. When the RTA process is performed at such a high temperature, the titanium silicide 32 is formed in the n + polysilicon film 26 and the n + bonding layer 28, and the p + polysilicon film 27 and the p + bonding layer 29. There is an advantage that can be formed to almost the same thickness. In this way, the titanium in the (26, 27, 28, 29) region does not react with the titanium (31), the polysilicon film 33 deposited on the silicon and titanium (31) in the region, 27, 28, 29) will remain on the area.
계속해서, 제2c도에서 NH4F 및 HF를 포함하는 용액내에서 티타늄 실리사이드(32)의 식각율이 산화막(24)의 식각율보다 훨씬 큰 것을 이용하여 티타늄 실리사이드(32)를 선택적으로 제거한다.Subsequently, the titanium silicide 32 is selectively removed using the etching rate of the titanium silicide 32 in the solution containing NH 4 F and HF in FIG. 2C much higher than the etching rate of the oxide film 24. .
끝으로, 제2d도에서 HNO3: CH3COOH : HF가 20 : 20 : 1 내지 200 : 80 : 1인 조성의 폴리식각제로 티타늄 실리사이드(32)위의 폴리실리콘막(33)을 선택적으로 제거한다.Finally, in FIG. 2d, the polysilicon layer 33 on the titanium silicide 32 is selectively removed with a polyetchant having a composition of HNO 3 : CH 3 COOH: HF of 20: 20: 1 to 200: 80: 1 do.
상기와 같이 이루어지는 본 발명은 서로 다른 형의 전도막 상에 형성되는 실리사이드막의 두께가 거의 동일하고, 두껍게 형성되므로 n+지역이 쉽게 열화되는 현상이 방지된다. 또한 본 발명에 따르면 실리사이드막 형성하기 위한 RTA 공정은 한번이면 되므로, 종래의 2단계 RTA공정을 이용하는 셀리사이드 공정보다 경제적이다.In the present invention as described above, since the thicknesses of the silicide films formed on the conductive films of different types are almost the same, and are formed thick, the phenomenon that the n + region is easily deteriorated is prevented. In addition, according to the present invention, since the RTA process for forming the silicide film is required only once, it is more economical than the celicide process using the conventional two-step RTA process.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940013153A KR0130865B1 (en) | 1994-06-10 | 1994-06-10 | Manufacture of silicide film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940013153A KR0130865B1 (en) | 1994-06-10 | 1994-06-10 | Manufacture of silicide film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960002482A KR960002482A (en) | 1996-01-26 |
| KR0130865B1 true KR0130865B1 (en) | 1998-04-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940013153A KR0130865B1 (en) | 1994-06-10 | 1994-06-10 | Manufacture of silicide film |
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| Country | Link |
|---|---|
| KR (1) | KR0130865B1 (en) |
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1994
- 1994-06-10 KR KR1019940013153A patent/KR0130865B1/en not_active IP Right Cessation
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| KR960002482A (en) | 1996-01-26 |
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