KR940004419B1 - Mos type semiconductor device and making method thereof - Google Patents

Abstract

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Description

MOS semiconductor device and manufacturing method thereof

1A to 1B are cross-sectional views sequentially illustrating a manufacturing process of a MOSFET according to an embodiment method of the present invention, respectively.

2 is a top view of a MOSFET according to an embodiment of the present invention.

3A is a sectional view showing the structure of a conventional MOSFET.

3b is a top view of a conventional MOSFET.

* Explanation of symbols for main parts of the drawings

1: Silicon semiconductor substrate 2 _-1 , 2 _-2 : Device isolation insulating film

3: gate oxide film 4: gate electrode

5 _-1 , 5 _-2 : Post Oxidation Film 6 _-1 , 6 _-2 : Si ₃ N ₄ Film

7: impurity diffusion layer 8: polycrystalline oxide film

9: Ti film 10: TiSix film

11 interlayer insulating film 12 connection hole

13: metal wiring

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a MOS semiconductor device for use in a semiconductor integrated circuit requiring high speed operation and high integration, and a method of manufacturing the same, and more particularly, to a MOSFET (MOS field effect transistor).

[Traditional Technology and Problems]

3A is a cross-sectional view showing the structure of a conventional MOSFET, in which a gate electrode 34 is formed through a gate insulating film 33 in an element region surrounded by a device isolation insulating film 32 on a semiconductor substrate 31. Impurity diffusion layers 35 are formed on the surfaces of the substrate 31 on both sides of the electrode 34 as source and drain regions, respectively. An interlayer insulating film 37 is formed through the post-oxidation film 36 on the gate electrode 34, and a connection hole 38 through which a portion of the diffusion layer 35 is exposed is opened to connect the source and drain regions of the connection electrode ( 39) is formed.

In the above configuration, as shown in the top view of the MOSFET of FIG. 3B, the connection hole 38 is opened so as to have a sufficient mask matching margin for the gate electrode 34 and the impurity diffusion layer 35. As shown in FIG. For example, the margin width A of the gate electrode 34 and the connection hole 38 is set to be large enough to match the width of the gate electrode. In addition, the margin width B with the impurity diffusion layer 35 is also set large according to the width A.

However, in such a configuration, the area of the impurity diffusion layer 35 is inevitably increased, thereby minimizing the miniaturization of the device and also increasing the diffusion capacity, which causes a decrease in operating speed.

In addition, the connection electrode 39 is a metal wiring layer made of, for example, an alloy of various metals based on Al (aluminum), and the depth of the impurity diffusion layer 35 has become shallow due to the recent miniaturization. The chemical reaction between the wiring layer and the impurity diffusion layer 35 may cause an increase in connection resistance or breakdown of the junction.

As described above, in the conventional MOSFET, since the connection hole is formed to have a sufficient matching margin for the gate electrode and the impurity diffusion, the area of the impurity diffusion layer is increased, which hinders the miniaturization of the device and the diffusion capacity, thereby increasing the speed of operation. It cannot be achieved. In addition, the depth of the diffusion layer becomes shallow, and there is a drawback that an increase in connection resistance and breakdown of the junction are caused by a chemical reaction with the metal wiring layer connected to the impurity diffusion layer.

[Purpose of invention]

Accordingly, the present invention has been made in view of the above circumstances, and an object thereof is to provide a MOS semiconductor device and a method of manufacturing the same having high reliability and high speed operation.

[Configuration of Invention]

In the MOS semiconductor device according to the present invention for achieving the above object, sidewalls of the first conductivity type are provided on both sides of the gate electrode on the semiconductor substrate, and the sidewalls are impurities of the first conductivity type formed on the substrate surface on both sides of the gate electrode. A first insulating film for element isolation formed on a semiconductor substrate, a second insulating film formed on a substrate surrounded by the first insulating film, and a second insulating film selectively formed on the second insulating film. And a third insulating film covering the gate electrode, a first conductivity type impurity diffusion layer serving as a source and a drain region formed on the substrate surface on both sides of the gate electrode, and a first electrode on both sides of the gate electrode covering the impurity diffusion layer. High-melting-point metal silicide formed to cover the conductive sidewalls, the sidewalls, and upper surfaces of the gate electrodes and the first insulating films, respectively. And a high melting point consists of a wiring electrode connected to the metal silicide layer.

In addition, the manufacturing method of the MOS semiconductor device of the present invention comprises the steps of forming a first insulating film for device isolation on a semiconductor substrate, and forming a second insulating film on a substrate surrounded by the first insulating film, (2) selectively forming a gate electrode on the insulating film, forming a third insulating film covering the gate electrode, covering the top and both sides of the gate electrode covered with the third insulating film, and near the both sides of the gate electrode. Forming a fourth oxidation resistant insulating film so as to extend to the surface of the substrate; forming a fifth insulating film for device isolation using the fourth insulating film as a mask; and the fourth insulating film and the second insulating film under the fourth insulating film. Removing the first conductive type film on the entire surface and introducing impurities of the first conductive type to the substrate surfaces on both sides of the gate electrode to form source and drain regions; The first conductive type conductive film is formed so as to cover the gate electrode side surfaces and the source and drain regions so as to form a gate side wall electrode. A step of converting a part of the deposited high melting point metal into a high melting point metal silicide layer, a step of removing an unreacted metal layer other than the high melting point metal silicide layer, and forming an interlayer insulating film and connecting the solid solution point metal silicide layer. It consists of a process of opening a hole.

[Action]

In the present invention, the sidewalls on both sides of the gate electrode serve as connection electrodes with the source and drain regions as the gate side wall electrodes, thereby reducing the source and drain regions. Furthermore, the high melting point metal silicide layer formed on the gate side wall electrode is formed by reacting the gate side wall electrode and the high melting point metal deposited thereon, so as to cover a part of the upper surface of each of the gate electrode and the first insulating film. Since it forms, the connection margin becomes sufficient.

EXAMPLE

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1A to 1D are cross-sectional views sequentially showing a manufacturing process of a MOSFET by the method of one embodiment of the present invention.

First, to form a gate oxide film 3 after the device isolation insulating film _(2-1) on a silicon substrate 1 to form 4000 ~ 5000Å. Then the polysilicon film serving as the gate electrode 4 by a known technique, after an oxide film (5 _1), Si ₃ N ₄ film are sequentially deposited to _(6-1), is oxidized by this anisotropic etching, and then back to the gate electrode surface A post oxidized film (5 _-2 ) is formed. Then, a Si ₃ N ₄ film (6 _-2 ) is deposited on the entire surface by CVD (chemical vapor deposition) or the like and etched back by RIE (reactive ion etching) or the like. by then the remaining Si ₃ N ₄ film _(6-2) on both sides of the gate electrode [claim 1a Fig.

Then, the Si ₃ N ₄ film _{(6-1, 6-2)} was the second element isolation insulating film _(2-2) in an atmosphere of 900 ~ 1000 ℃ as a mask to form 2000 ~ 3000Å, Si ₃ N ₄ etching the film is removed _{(6-1, 6-2),} and then exposing the substrate (1) surface of the gate electrode on both sides to remove the oxide layer under the Si ₃ N ₄ film _(6-2) [claim 1b Fig.

Next, a source and a drain region are formed on the exposed substrate surface. For example, when forming an N-type region, As is formed, and when forming a P-type region, BF ₂ is dosed at a dose of 1 to 5 x 10 ¹⁵ cm ^-2 at 40 to 60 KeV. Thereafter, a polysilicon film 8 is formed on the entire surface by CVD, etc., doped with the same impurities as the impurity diffusion layer 7, and etched back using an RIE method or the like to cover the impurity diffusion layer 7. ) Is left on the gate electrode surface. After the Ti film 9 is sputter-deposited on the entire surface, Ar gas is introduced in a vacuum and heat treatment is performed at 400 to 500 ° C. As a result, the Ti film 9 consumes silicon in the polysilicon film 8 to be silicided, thereby forming the TiSix (where x = 2.0 to 2.5) film 10 as the upper portion of the gate electrode and the element isolation insulating film _2-2 . It is formed to reach the top of [Fig. 1C].

Subsequently, the unreacted Ti film 9 other than the TiSix film 10 is etched away with a fluorine contract product. Thereafter, a CVD oxide film and a BPSG film are deposited on the entire surface, and the connection hole 12 is formed on the planarized interlayer insulating film 11 so that the upper surface of the TiSix film 10 is exposed to form the metal wiring 13 (manufactured by 1d degree].

According to the method of the above embodiment, it becomes a connection electrode of the direct source and the drain region (the impurity diffusion layer 7) of each of the sidewalls (polysilicon film 8) of the gate electrode 4, and there is no need to provide a matching margin. In addition, the TiSix film 10 having a large area extending over the gate electrode and the upper portion of the device isolation insulating film provides self-matching margin.

FIG. 2 is a top view of the above embodiment, whereby the TiSix film 10 can be refined while having sufficient matching margin of the connection hole 12. Furthermore, since the impurity diffusion layer 7 as the source and drain electrodes is suppressed only by the width of the polysilicon film 8 on the sidewall of the gate electrode 4, and the extra impurity diffusion layer region is eliminated, the diffusion layer capacity is reduced to achieve high speed of operation. do.

In addition, since the polysilicon film 8 is provided on the impurities dispersion layer 7, no chemical reaction occurs between the impurity diffusion layer 7 and the metal wiring 13. Therefore, the problem of an increase in connection resistance or breakage of a junction is solved.

Incidentally, in the above-described method, the Ti film 9 is used as the metal to be silicided by consuming silicon in the polysilicon film 8, but not limited to this, and may be a high melting point metal such as W or Mo.

[Effects of the Invention]

As described above, according to the present invention, since the gate electrode side wall becomes a connection electrode, the source and drain regions can be reduced, and the silicide covering the gate electrode side wall provides a self-aligning margin so that the MOSFET is highly integrated. In addition, it is possible to provide a MOS semiconductor device having a high reliability and a method of manufacturing the same, contributing to the high speed of operation.

Claims (3)

The first conductive type sidewall 8 is provided on both sides of the gate electrode 4 on the semiconductor substrate 1, and the sidewall 8 is formed on the substrate surface on both sides of the gate electrode 4. A MOS semiconductor device, characterized in that it is a connection electrode with each of the diffusion layers (7). A first insulating film for element isolation formed on the semiconductor substrate 1 _{(2-1, 2-2)} and, a second insulating film formed on a substrate enclosed in the first insulating film _{(2-1, 2-2),} (3 ), the second insulating film 3, optionally gate electrode 4 formed in the upper and the gate electrode 4, a third insulating film _{(5-1, 5-2} covering), the gate electrode 4, both sides of the An impurity diffusion layer 7 of the first conductivity type as a source and drain region formed on the substrate surface, sidewalls 8 of the first conductivity type on both sides of the gate electrode 4 covering the impurity diffusion layer 7, and the sidewall 8 ) and on the gate electrode 4 and the first insulating film _{(2-1, 2-2} and the metal silicide layer (melting point 10 formed so as to cover each of a part of the upper surface)) and the high melting point metal silicide layer (10) A MOS semiconductor device comprising a wiring electrode (13) to be connected. Forming a first insulating film _(2-1) for element isolation on the semiconductor substrate (1) and, a second insulating film (3) on a substrate (1) enclosed in the first insulating film _(2-1) Forming, selectively forming a gate electrode 4 on the second insulating film 3, forming a third insulating film 5 _-1 , 5 _-2 covering the gate electrode 4, wherein the oxidation-resistant so as to extend to the substrate surface of the third insulating film _{(5-1, 5-2)} to the opposite side, with box covering the upper surface and both side surfaces of the gate covered electrode 4 and the gate electrode 4, the vicinity of the fourth insulating film Forming (6 _-1 , 6 _-2 ), forming a fifth insulating film ( _2-2 ) for device isolation using the fourth insulating film ( _6-1 , _6-2 ) as a mask, and the fourth to the substrate surface of the insulating film _{(6-1, 6-2)} and the fourth insulating film _{(6-1, 6-2)} a step of removing the second insulating film 3 under the gate electrode 4, both sides of the Source and drain regions by introducing 1-conductive impurities (7), and a step of depositing a first conductive type conductive film (8) on the entire surface, wherein the first conductive type conductive film (8) is formed on both sides of the gate electrode (4) and the source and drain Forming a gate-side wall electrode by remaining to cover the region (7), depositing a high melting point metal layer (9) on the entire surface, vacuum heating and reacting with the conductive film (8) to partially deposit the high-point metal To a high melting point metal silicide layer (10), a step of removing an unreacted metal layer other than the high melting point metal silicide layer (10), and forming the interlayer insulating film (11) after the high melting point metal silicide layer (10) A method for manufacturing a MOS semiconductor device, comprising the step of drilling a connection hole onto the phase.

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