KR19980067517A - Gate pattern of semiconductor device and manufacturing method thereof - Google Patents
Gate pattern of semiconductor device and manufacturing method thereof Download PDFInfo
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- KR19980067517A KR19980067517A KR1019970003579A KR19970003579A KR19980067517A KR 19980067517 A KR19980067517 A KR 19980067517A KR 1019970003579 A KR1019970003579 A KR 1019970003579A KR 19970003579 A KR19970003579 A KR 19970003579A KR 19980067517 A KR19980067517 A KR 19980067517A
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- Prior art keywords
- layer
- gate
- insulating
- metal silicide
- width
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 32
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 23
- 230000003647 oxidation Effects 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 3
- 239000010703 silicon Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910008482 TiSiN Inorganic materials 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 3
- 229910008486 TiSix Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
Abstract
게이트 도전막의 티타늄 실리사이드층의 산화를 방지할 수 있는 반도체 장치의 게이트 패턴 및 그 제조방법에 관하여 개시한다. 이를 위하여 본 발명은, 실리콘 기판에 형성된 게이트 산화막과, 상기 게이트 산화막 상의 소정영역에 형성된 W1의 폭을 갖는 제1 도전층과, 상기 제1 도전층 상에 형성된 상기 W1의 폭보다 작은 W2의 폭을 갖고 금속 실리사이드층과, 상기 금속 실리사이드층 상에 형성된 W2의 폭을 갖는 제1 절연층과, 상기 금속 실리사이드층과 제1 절연층의 양측벽에 W2보다 작은 W3의 폭으로 제1 도전층 상에 형성된 제2 절연층과, 상기 게이트 산화막 상에서 상기 제1 도전층과 제2 절연층의 양측벽에 형성된 게이트 스페이서를 구비하는 것을 특징으로 하는 반도체 장치의 게이트 패턴 및 그 제조방법을 제공한다.A gate pattern of a semiconductor device capable of preventing oxidation of the titanium silicide layer of the gate conductive film and a method of manufacturing the same are disclosed. To this end, the present invention provides a gate oxide film formed on a silicon substrate, a first conductive layer having a width of W1 formed in a predetermined region on the gate oxide film, and a width of W2 smaller than the width of W1 formed on the first conductive layer. And a metal silicide layer, a first insulating layer having a width of W2 formed on the metal silicide layer, and a width of W3 smaller than W2 on both side walls of the metal silicide layer and the first insulating layer. And a gate spacer formed on both sidewalls of the first conductive layer and the second insulating layer on the gate oxide layer, and a gate pattern of the semiconductor device and a method of manufacturing the same.
Description
본 발명은 반도체 장치의 게이트 패턴 및 그 제조방법에 관한 것으로, 상세하게는 게이트 도전막의 티타늄 실리사이드층의 산화를 방지할 수 있는 반도체 장치의 게이트 패턴 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate pattern of a semiconductor device and a manufacturing method thereof, and more particularly, to a gate pattern of a semiconductor device capable of preventing oxidation of a titanium silicide layer of a gate conductive film and a method of manufacturing the same.
반도체 장치의 집적도가 증가함에 따라 저저항 배선의 중요성이 증대되고 있으며, 최근에는 폴리실리콘막을 대체하는 저저항 배선 구조로서 폴리실리콘막 상에 고융점 금속 실리사이드(Refractory Metal Silicide)층, 특히 텅스텐 실리사이드, 티타늄 실리사이드, 코발트 실리사이드, 몰리브덴 실리사이드(MoSi2) 및 탄탈륨 실리사이드 등을 적층시킨 폴리사이드 구조를 널리 사용하고 있다. 반도체장치의 게이트 도전막도 종래에는 폴리실리콘에 인(Phosphorus)을 도핑(doping)하여 저항을 낮춘 것을 널리 사용하고 있었다. 하지만, 최근에는 소자의 고집적화에 따라 한층 더 낮은 저항을 갖는 게이트 도전층이 요구되어 폴리실리콘 위에 텅스텐 실리사이드(WSi) 또는 티타늄 실리사이드(TiSix)등을 적층시킨 이중구조의 폴리사이드가 그 대체 물질로 사용되고 있다. 이중에서 특히, 티타늄 실리사이드는 텅스텐 실리사이드(WSi)보다 낮은 저항을 갖는 배선 물질로서 널리 사용되어 왔으며, 질화처리(Nitridation)로 확산 장벽층을 형성시켜 티타늄 실리사이드와 알루미늄 금속 사이의 접촉을 매우 안정되게 할 수 있는 장점으로 인해 주목을 받고 있다.As the degree of integration of semiconductor devices increases, the importance of low-resistance wiring is increasing. Recently, as a low-resistance wiring structure replacing the polysilicon film, a high melting point metal silicide layer, particularly tungsten silicide, Polysilicon structures in which titanium silicide, cobalt silicide, molybdenum silicide (MoSi2) and tantalum silicide are laminated are widely used. Conventionally, a gate conductive film of a semiconductor device has been widely used in which a resistance is lowered by doping phosphorous (Phosphorus) to polysilicon. However, in recent years, due to the high integration of the device, a gate conductive layer having a lower resistance is required, and a polystructure having a double structure in which tungsten silicide (WSi) or titanium silicide (TiSix) is laminated on polysilicon is used as a substitute material. have. In particular, titanium silicide has been widely used as a wiring material having a lower resistance than tungsten silicide (WSi), and nitriding forms a diffusion barrier layer to make the contact between titanium silicide and aluminum metal very stable. It is attracting attention because of its advantages.
반도체 제조공정에서 티타늄 실리사이드를 갖는 게이트 패턴의 제조공정은 통상, 플라즈마 식각이나 반응성 이온 식각(RIE: Reactive Ion Etching, 이하 'RIE'라 칭함) 등의 건식식각을 이용한다. 그러나 전술한 건식식각으로 게이트 패턴을 식각하면 하부의 게이트 산화막의 가장자리가 손상을 받게 되는 문제점이 있다. 이러한 게이트 산화막의 가장자리의 손상은 게이트산화막의 절연 파괴 전압에 영향을 주어서 소자의 신뢰성을 저해하는 요소로 작용하게 된다. 따라서, 게이트 패턴의 형성 후에 게이트산화막의 손상을 없애기 위한 후속 공정이 필수적으로 수행되어야 한다. 이러한 후속 공정으로서 일반적으로 사용되는 방법은 게이트 패턴을 형성한 후, 추가적으로 산화공정을 실시하여 게이트산화막의 가장자리에 손상된 부분을 회복시켜 주는 방법이 일반적으로 사용되고 있다.In the semiconductor manufacturing process, a gate pattern having a titanium silicide is usually manufactured by dry etching such as plasma etching or reactive ion etching (RIE). However, when the gate pattern is etched by the aforementioned dry etching, the edge of the lower gate oxide layer may be damaged. The damage of the edge of the gate oxide film affects the dielectric breakdown voltage of the gate oxide film, thereby acting as a factor that hinders the reliability of the device. Therefore, after the formation of the gate pattern, a subsequent process for eliminating damage to the gate oxide film must be performed essentially. As a method generally used as such a subsequent step, a method of recovering a damaged part of the edge of the gate oxide film by performing an additional oxidation process after forming a gate pattern is generally used.
도 1 내지 도 4는 종래기술에 의한 반도체 장치의 게이트 패턴 형성방법을 설명하기 위하여 도시한 단면도들이다.1 to 4 are cross-sectional views illustrating a gate pattern forming method of a semiconductor device according to the prior art.
도 1을 참조하면, 소자 분리 공정에 의한 필드 산화막(도시되지 않음)이 형성된 반도체 기판(1)의 전면에 게이트 산화막(3), 폴리실리콘으로 형성된 제1 도전층(5), 티타늄 실리사이드와 같은 내산화성이 약한 물질로 형성된 제2 도전층(7)을 순차적으로 적층한다.Referring to FIG. 1, a gate oxide film 3 is formed on a front surface of a semiconductor substrate 1 on which a field oxide film (not shown) is formed by a device isolation process, a first conductive layer 5 formed of polysilicon, and a titanium silicide. The second conductive layer 7 formed of a material having low oxidation resistance is sequentially stacked.
도 2를 참조하면, 상기 게이트 산화막(3), 제1 도전층(5), 제2 도전층(7)이 순차적으로 적층된 반도체 기판의 전면에 플라즈마 또는 RIE에 의한 건식식각 공정을 진행하여 게이트 패턴을 형성한다. 이때, 상술한 바와 같이 건식식각 진행시에 게이트산화막의 가장자리 부분(9)이 손상을 받게 된다.Referring to FIG. 2, a dry etching process using plasma or RIE may be performed on the entire surface of the semiconductor substrate on which the gate oxide layer 3, the first conductive layer 5, and the second conductive layer 7 are sequentially stacked. Form a pattern. At this time, as described above, the edge portion 9 of the gate oxide film is damaged during the dry etching process.
도 3을 참조하면, 상기 게이트 산화막의 가장자리 부분(9)에 손상을 회복시키기 위한 산화공정을 반도체 기판의 전면에 진행하여 손상된 게이트산화막(3)의 가장자리 부분(9)을 원상 회복시키고 게이트 패턴의 외부를 감싸는 제1 절연막(11)을 형성한다.Referring to FIG. 3, an oxidation process for recovering damage to the edge portion 9 of the gate oxide film is performed on the entire surface of the semiconductor substrate, thereby restoring the edge portion 9 of the damaged gate oxide film 3 to its original shape. A first insulating film 11 surrounding the outside is formed.
도 4를 참조하면, 상기 제1 절연막(11)이 형성된 반도체 기판의 전면에 제2 절연막을 형성한 후, 등방성 식각을 진행하여 게이트 스페이서(13)를 형성한다.Referring to FIG. 4, after forming the second insulating layer on the entire surface of the semiconductor substrate on which the first insulating layer 11 is formed, the gate spacer 13 is formed by isotropic etching.
상술한 종래기술에 의한 반도체 장치의 게이트 패턴 형성방법에 의하면, 제2 도전층인 티타늄 실리사이드가 내산화성에 약한 금속물질이기 때문에 게이트산화막(3)의 가장자리(9)에 있는 손상을 회복시키기 위한 산화공정 중에 티타늄 실리사이드 자체가 빠른 속도로 산화됨으로써 게이트 패턴의 형태 불량 및 게이트도전막의 저항이 크게 증가하는 문제가 있다.According to the gate pattern forming method of the semiconductor device according to the prior art described above, since titanium silicide, which is the second conductive layer, is a metal material that is poor in oxidation resistance, oxidation to restore damage at the edge 9 of the gate oxide film 3 is performed. Titanium silicide itself is oxidized at a high speed during the process, resulting in a problem in that the shape of the gate pattern and the resistance of the gate conductive film are greatly increased.
본 발명이 이루고자 하는 기술적 과제는, 전술한 문제점인 티타늄 실리사이드층의 산화를 방지할 수 있는 반도체 장치의 게이트 패턴을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a gate pattern of a semiconductor device capable of preventing oxidation of the titanium silicide layer.
본 발명이 이루고자 하는 다른 기술적 과제는 전술한 문제점인 티타늄 실리사이드층의 산화를 방지할 수 있는 반도체 장치의 게이트 패턴 제조방법을 제공하는데 있다.Another object of the present invention is to provide a method of manufacturing a gate pattern of a semiconductor device capable of preventing oxidation of the titanium silicide layer, which is the aforementioned problem.
도 1 내지 도 4는 종래기술에 의한 반도체 장치의 게이트 패턴 형성방법을 설명하기 위하여 도시한 단면도들이다.1 to 4 are cross-sectional views illustrating a gate pattern forming method of a semiconductor device according to the prior art.
도 5 내지 도 9는 본 발명에 따른 반도체 장치의 게이트 패턴 형성방법을 설명하기 위하여 도시한 단면도들이다.5 to 9 are cross-sectional views illustrating a method of forming a gate pattern of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 간단한 설명Brief description of symbols for the main parts of the drawings
100: 반도체 기판,102: 게이트 산화막,100: semiconductor substrate, 102: gate oxide film,
104: 제1 도전층,106: 금속 실리사이드층,104: first conductive layer, 106: metal silicide layer,
108: 제1 절연층,110: 제2 절연층,108: first insulating layer, 110: second insulating layer,
112: 게이트 스페이서.112: gate spacer.
상기의 기술적 과제를 달성하기 위하여 본 발명은, 실리콘 기판에 형성된 게이트 산화막과, 상기 게이트 산화막 상의 소정영역에 형성된 W1의 폭을 갖는 제1 도전층과, 상기 제1 도전층 상에 형성된 상기 W1의 폭보다 작은 W2의 폭을 갖고 금속 실리사이드층과, 상기 금속 실리사이드층 상에 형성된 W2의 폭을 갖는 제1 절연층과, 상기 금속 실리사이드층과 제1 절연층의 양측벽에 W2보다 작은 W3의 폭으로 제1 도전층 상에 형성된 제2 절연층과, 상기 게이트 산화막 상에서 상기 제1 도전층과 제2 절연층의 양측벽에 형성된 게이트 스페이서를 구비하는 것을 특징으로 하는 반도체 장치의 게이트 패턴을 제공한다.In order to achieve the above technical problem, the present invention provides a gate oxide film formed on a silicon substrate, a first conductive layer having a width of W1 formed in a predetermined region on the gate oxide film, and A width of W3 smaller than W2 on both side walls of the metal silicide layer and the first silicide layer having a width of W2 formed on the metal silicide layer, and having a width of W2 smaller than the width; And a second insulating layer formed on the first conductive layer and gate spacers formed on both sidewalls of the first conductive layer and the second insulating layer on the gate oxide film. .
본 발명의 바람직한 실시예에 의하면, 상기 W3은 100Å 이하인 것이 적합하고, 상기 W2와 2 개의 W3의 합은 제1 도전층의 폭인 W1인 것이 적합하다.According to a preferred embodiment of the present invention, the W3 is preferably 100 kPa or less, and the sum of the W2 and the two W3 is preferably W1 which is the width of the first conductive layer.
바람직하게는, 상기 제1 절연막은 실리콘 질화막 또는 실리콘 산화막인 것이 적합하고, 상기 금속 실리사이드층은 티타늄 실리사이드(TiSix)인 것이 적합하고, 상기 제2 절연막은 티타늄 실리사이드가 산화되는 것을 방지할 수 있는 SiN, TiN 및 TiSiN막 중에서 선택된 하나인 것이 적합하다.Preferably, the first insulating film is preferably a silicon nitride film or a silicon oxide film, the metal silicide layer is preferably titanium silicide (TiSix), and the second insulating film is SiN which can prevent the titanium silicide from being oxidized. Is one selected from among TiN and TiSiN films.
상기의 다른 기술적 과제를 달성하기 위하여 본 발명은, 반도체 기판에 게이트 산화막을 형성하는 단계와, 상기 게이트 산화막의 상부에 제1 도전층, 금속 실리사이드층 및 제1 절연층을 순차적으로 형성하는 단계와, 상기 제1 도전층, 금속실리사이드층 및 제1 절연층을 순차적으로 형성된 결과물에 건식식각을 진행하여 상기 제1 절연층과 금속 실리사이드층을 식각하는 단계와, 상기 건식식각을 진행한 결과물 상에 제2 절연막을 도포하는 단계와, 상기 제2 절연막을 등방성으로 식각하여 상기 금속 실리사이드층과 제1 절연층의 양측벽에만 제2 절연막을 형성하는 단계와, 상기 제1 절연막과 제2 절연막을 식각마스크로 제1 도전층을 식각하는 단계와, 상기 제2 절연막과 제1 도전층의 양측벽에 게이트 스페이서를 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 게이트 패턴 형성방법을 제공한다.According to an aspect of the present invention, there is provided a method of forming a gate oxide film on a semiconductor substrate, and sequentially forming a first conductive layer, a metal silicide layer, and a first insulating layer on the gate oxide film. And etching the first insulating layer and the metal silicide layer by performing dry etching on a resultant product of sequentially forming the first conductive layer, the metal silicide layer, and the first insulating layer, and on the resultant of the dry etching. Applying a second insulating film, isotropically etching the second insulating film to form a second insulating film only on both sidewalls of the metal silicide layer and the first insulating layer, and etching the first insulating film and the second insulating film Etching the first conductive layer with a mask, and forming gate spacers on both sidewalls of the second insulating layer and the first conductive layer. Which provides a gate pattern formation method of a semiconductor device.
본 발명의 바람직한 실시예에 의하면, 상기 제2 절연막을 형성하는 방법은 플라즈마 화학기상증착(PECVD)법으로 암모니아 가스를 사용하여 100Å 이하의 두께로 형성하는 것이 적합하다.According to a preferred embodiment of the present invention, the method of forming the second insulating film is preferably formed to a thickness of 100 kPa or less using ammonia gas by the plasma chemical vapor deposition (PECVD) method.
본 발명에 따르면, 반도체 장치의 게이트 패턴 형성공정에 있어서 티타늄 실리사이드층의 양측벽에 산화가 발생하여 반도체 장치의 게이트 패턴에서 게이트 도전막의 형태불량이나 전기적인 특성이 저하되는 것을 방지할 수 있다.According to the present invention, in the gate pattern forming step of the semiconductor device, oxidation occurs on both side walls of the titanium silicide layer, thereby preventing the shape defects and electrical characteristics of the gate conductive film from deteriorating in the gate pattern of the semiconductor device.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
먼저, 도 9는 본 발명의 바람직한 실시예에 따른 반도체 장치의 게이트 패턴의 구조 및 특징을 설명하기 위하여 도시한 단면도이다.First, FIG. 9 is a cross-sectional view illustrating the structure and features of a gate pattern of a semiconductor device according to an exemplary embodiment of the present invention.
도 9를 참조하면, 본 발명에 따른 반도체 장치의 게이트 패턴으로, 게이트 산화막(102)이 형성된 반도체 기판(100)의 소정 영역에 W1의 폭을 갖는 제1 도전층(104), 예컨대, 폴리실리콘층이 형성되고, 제1 도전층(104) 상에 W1보다 작은 W2의 폭을 갖는 금속 실리사이드층(106)인 티타늄 실리사이드층과 W2의 폭을 갖는 제1 절연층(108), 예컨대 실리콘 질화막이나 실리콘 산화막이 구성되어 있다. 또한 상기 제1 도전층(104) 상의 금속 실리사이드층(106)과 제1 절연층(108)의 양측벽에는 W2 보다 작은 100Å 이하의 폭을 갖는 제2 절연층(110), 예컨대 TiN, TiSiN 및 TiN 중에서 선택된 하나의 막이 W3의 폭으로 구성되어 있다. 여기서 상기 2개의 W3와 W2의 폭의 합은 상기 W1의 폭이 된다. 마지막으로, 상기 게이트 산화막(102) 상의 제1 도전층(104)과 제2 절연층(110)의 양측벽에 게이트 스페이서(112)가 구성되어 있다.Referring to FIG. 9, as a gate pattern of a semiconductor device according to the present invention, a first conductive layer 104 having a width of W1 in a predetermined region of a semiconductor substrate 100 on which a gate oxide film 102 is formed, for example, polysilicon A layer is formed, and on the first conductive layer 104 a titanium silicide layer 106 which is a metal silicide layer 106 having a width of W2 smaller than W1 and a first insulating layer 108 having a width of W2, such as a silicon nitride film, The silicon oxide film is comprised. In addition, both sidewalls of the metal silicide layer 106 and the first insulating layer 108 on the first conductive layer 104 may have a second insulating layer 110 having a width of 100 Å or less smaller than W2, such as TiN, TiSiN, and the like. One film selected from TiN has a width of W3. Here, the sum of the widths of the two W3 and the W2 becomes the width of the W1. Lastly, gate spacers 112 are formed on both sidewalls of the first conductive layer 104 and the second insulating layer 110 on the gate oxide film 102.
본 발명에 있어서 가장 특징적인 요소는 상기 제2 절연막(110)으로, 금속 실리사이드층(106)인 티타늄 실리사이드의 양측벽을 감싸고 있기 때문에 후속되는 산화공정에서 내산화성에 약한 티타늄 실리사이드의 측벽이 산화되어 게이트 패턴의 형태불량이나, 도전성이 저하되는 문제점을 해결하는 중요한 수단이 된다.In the present invention, the most characteristic element is the second insulating film 110, which surrounds both side walls of the titanium silicide, which is the metal silicide layer 106, so that the sidewall of the titanium silicide, which is weak to oxidation resistance, is oxidized in a subsequent oxidation process. It is an important means for solving the problem of poor shape of the gate pattern and lowering of conductivity.
도 5내지 도 9는 본 발명의 바람직한 실시예에 의한 반도체 장치의 게이트 패턴 형성방법을 설명하기 위하여 도시한 단면도들이다.5 to 9 are cross-sectional views illustrating a method of forming a gate pattern of a semiconductor device in accordance with an embodiment of the present invention.
도 5를 참조하면, 반도체 기판(100)에 게이트 산화막(102)과 제1 도전층(104), 예컨대 폴리실리콘층을 형성한다. 이어서, 상기 제1 도전층(104) 상에 티타늄 실리사이드와 같은 금속 실리사이드층(106)과, 실리콘 질화막 또는 실리콘 산화막을 재질로 하는 제1 절연층(108)을 형성한다.Referring to FIG. 5, a gate oxide film 102 and a first conductive layer 104, for example, a polysilicon layer, are formed on the semiconductor substrate 100. Subsequently, a metal silicide layer 106 such as titanium silicide and a first insulating layer 108 made of a silicon nitride film or a silicon oxide film are formed on the first conductive layer 104.
도 6을 참조하면, 상기 제1 절연층(108)이 형성된 결과물에 제1 절연막을 식각마스크로 패터닝하고 플라즈마 식각이나 RIE와 같은 이방성 식각을 진행하여, 하부의 제1 절연층(108)과 금속 실리사이드층(106)을 패터닝한다.Referring to FIG. 6, the first insulating layer is patterned as an etch mask on the resultant in which the first insulating layer 108 is formed, and anisotropic etching such as plasma etching or RIE is performed to form a lower first insulating layer 108 and a metal. The silicide layer 106 is patterned.
도 7을 참조하면, 상기 제1 절연층(108)과 금속 실리사이드층(106)을 이방성으로 식각한 결과물의 전면에 플라즈마 화학기상층착(PECVD)법으로 암모니아 가스(NH3)를 사용하여 제2 절연막(110), 예컨대 TiN, TiSiN 및 TiN 중에서 선택된 하나의 막을 100Å 이하의 두께로 형성한다.Referring to FIG. 7, the first insulating layer 108 and the metal silicide layer 106 are anisotropically etched using ammonia gas (NH 3 ) by plasma chemical vapor deposition (PECVD) on the entire surface of the resultant. An insulating film 110, for example, one film selected from TiN, TiSiN, and TiN, is formed to a thickness of 100 μm or less.
도 8을 참조하면, 상기 제2 절연막(110)이 형성된 반도체 기판에 등방성 식각을 진행하여 제1 도전층(104)의 상부와, 제1 절연층(108)의 상부에 있는 제2 절연막(110)의 일부를 제거한다. 이어서, 상기 제1 절연막(108)과 제2 절연막(110)을 식각마스크로 하부의 제1 도전층(104)을 식각한다. 이 과정에서 종래 기술에도 지적되었던 게이트 산화막(102)의 측벽이 손상(도면에 도시되지 않음)을 받게 되지만 산화공정을 다시 한 번 진행하여 게이트 산화막(102)의 측벽의 손상을 복원시킨다. 여기서, 상기 제2 절연막(110)이 금속 실리사이드층(106), 예컨대 내산화성이 약한 티타늄 실리사이드층의 측벽을 감싸고 있기 때문에, 게이트 산화막(102)의 측벽의 손상을 복원하기 위한 산화공정 도중에 금속 실리사이드층(106)이 산화되어, 폴리실리콘과 티타늄 실리사이드로 구성된 게이트 도전막의 패턴 변형이나, 도전성이 떨어지는 종래기술의 문제점이 해결되게 된다.Referring to FIG. 8, an isotropic etching is performed on the semiconductor substrate on which the second insulating layer 110 is formed, and the second insulating layer 110 is disposed on the upper portion of the first conductive layer 104 and the upper portion of the first insulating layer 108. Remove part of). Subsequently, the first conductive layer 104 below is etched using the first insulating layer 108 and the second insulating layer 110 as an etch mask. In this process, the sidewall of the gate oxide film 102, which has been pointed out in the prior art, is damaged (not shown), but the oxidation process is once again performed to restore the damage of the sidewall of the gate oxide film 102. Here, since the second insulating layer 110 covers the sidewalls of the metal silicide layer 106, for example, the titanium silicide layer having low oxidation resistance, the metal silicide is in the middle of the oxidation process for restoring damage to the sidewall of the gate oxide layer 102. The layer 106 is oxidized to solve the problem of the pattern deformation of the gate conductive film composed of polysilicon and titanium silicide, or the problem of the prior art, which is poor in conductivity.
도 9를 참조하면, 상기 게이트 산화막의 손상을 복원하기 위한 산화공정이 완료된 결과물에 게이트 스페이서(112) 형성을 위한 물질층을 도포하고, 이를 식각하여 게이트 스페이서(112)를 형성함으로써, 본 발명에 따른 반도체 장치의 게이트 패턴 형성공정을 완료한다.Referring to FIG. 9, a material layer for forming a gate spacer 112 is coated on a result of an oxidation process for restoring damage to the gate oxide layer, and the gate layer 112 is formed by etching the same. The gate pattern forming process of the semiconductor device is completed.
본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함은 명백하다.The present invention is not limited to the above-described embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit to which the present invention belongs.
따라서, 상술한 본 발명에 따르면, 게이트 패턴중에서 티타늄으로 구성된 금속 실리사이드층의 양측벽에서 유발되는 산화를 억제하여 게이트 도전막의 패턴 변형을 방지하고, 도전성이 저하되는 문제점을 해결할 수 있는 반도체 장치의 게이트 패턴 및 그 형성방법을 실현할 수 있다.Therefore, according to the present invention described above, the gate of the semiconductor device capable of preventing the pattern deformation of the gate conductive film by suppressing the oxidation caused from both side walls of the metal silicide layer composed of titanium in the gate pattern, and to solve the problem that the conductivity is lowered The pattern and its formation method can be realized.
Claims (9)
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| KR1019970003579A KR100243280B1 (en) | 1997-02-05 | 1997-02-05 | Gate pattern of semiconductor device &fabrication method thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040051237A (en) * | 2002-12-12 | 2004-06-18 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device having metal-gate electrode |
| KR100751668B1 (en) * | 2001-12-29 | 2007-08-23 | 주식회사 하이닉스반도체 | Method of forming a spacer for a gate electrode |
| US7521316B2 (en) | 2004-09-09 | 2009-04-21 | Samsung Electronics Co., Ltd. | Methods of forming gate structures for semiconductor devices |
| KR20150047218A (en) * | 2013-10-24 | 2015-05-04 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
| CN110610859A (en) * | 2018-06-15 | 2019-12-24 | 台湾积体电路制造股份有限公司 | Method for forming fin field effect transistor and semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0637108A (en) * | 1992-07-14 | 1994-02-10 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0878411A (en) * | 1994-09-08 | 1996-03-22 | Sumitomo Metal Ind Ltd | Semiconductor device and its manufacture |
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1997
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100751668B1 (en) * | 2001-12-29 | 2007-08-23 | 주식회사 하이닉스반도체 | Method of forming a spacer for a gate electrode |
| KR20040051237A (en) * | 2002-12-12 | 2004-06-18 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device having metal-gate electrode |
| US7521316B2 (en) | 2004-09-09 | 2009-04-21 | Samsung Electronics Co., Ltd. | Methods of forming gate structures for semiconductor devices |
| US7772637B2 (en) | 2004-09-09 | 2010-08-10 | Samsung Electronics Co., Ltd. | Semiconductor devices including gate structures and leakage barrier oxides |
| KR20150047218A (en) * | 2013-10-24 | 2015-05-04 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
| CN110610859A (en) * | 2018-06-15 | 2019-12-24 | 台湾积体电路制造股份有限公司 | Method for forming fin field effect transistor and semiconductor device |
| KR20190142273A (en) * | 2018-06-15 | 2019-12-26 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Controlling profiles of replacement gates |
| US10868139B2 (en) | 2018-06-15 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling profiles of replacement gates |
| KR102389064B1 (en) * | 2018-06-15 | 2022-04-22 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Controlling profiles of replacement gates |
| CN110610859B (en) * | 2018-06-15 | 2022-11-29 | 台湾积体电路制造股份有限公司 | Method for forming fin field effect transistor and semiconductor device |
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| KR100243280B1 (en) | 2000-03-02 |
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