JP3724057B2 - MOS transistor and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a MOS transistor capable of increasing tolerance of overlay deviation at the time of forming a contact hole and reducing contact resistance and sheet resistance, and a manufacturing method thereof.
[0002]
[Prior art]
  In ultra-highly integrated semiconductor devices such as VLSI and ULSI in recent years, more and more advanced process technology is required as design rules are reduced.
[0003]
  For example, under the design rule of 0.3 μm and later, when trying to determine the design margin of the connection hole in consideration of the variation in overlay error with the lower layer wiring, the design dimension of the connection hole (= hole diameter + design margin) ) Is becoming too large. If it is attempted to deal with this problem by increasing the line width of the lower layer wiring, reduction of the chip area and high integration are hindered. Conversely, if the hole diameter is reduced, the hole pattern cannot be resolved. The above-described variation in overlay error is caused by insufficient alignment performance of a reduction projection exposure apparatus used in photolithography. Moreover, this variation is an item that is particularly difficult to scale down among various scaling factors included in the semiconductor process, and is said to be a factor that determines the limit of the exposure technology beyond the resolution.
[0004]
  Against this background, a self-aligned contact (SAC) process that can eliminate the design margin for alignment on a photomask has been proposed. Various types of SAC processes are known, but the upper part and side walls of the wiring are covered with a SiN film, or a single layer of SiN film is interposed between the wiring and the interlayer insulating film, and these SiN films are formed. Processes that are used as etch stop films are best studied. This is because an extra exposure step is not required and the interlayer insulating film can be planarized.
[0005]
  On the other hand, reducing the resistance of the wiring is also an important issue. What is reduced along with higher integration of semiconductor devices is not only the hole diameter and wiring width, but also the thickness (junction depth) of the diffusion layer constituting the source / drain regions. However, when the junction becomes shallower, the sheet resistance increases. For example, when the junction depth is about 0.06 μm under the design rule of 0.1 μm, the sheet resistance reaches 1 kΩ / □. This causes a significant decrease in response speed in a device using a diffusion layer as an electrode, such as an ASIC.
[0006]
  There is known a technique for reducing the resistance of the diffusion layer by forming a metal silicide layer on the surface thereof. In general, the metal silicide layer is formed by thinly depositing a metal film capable of forming silicide on the entire surface of the substrate including the exposed portion of the silicon (Si) -based material layer, and then performing a heat treatment, so that the metal film, the Si-based material layer, It is formed by a method in which a self-aligned silicidation reaction (SALICIDE) proceeds in a portion where the contact is made. Transition metals such as Ti and Mo are most often used as the metal capable of forming silicide, and a TiSix film and a MoSix film are formed on the source / drain regions of the MOS transistor and the surface of the gate electrode. If a contact hole is opened facing this source / drain region and the inside thereof is filled with a metal plug, the contact area between the metal plug and Si, which actually determines the contact resistance, is much wider than the actual contact area. Since it is close to the entire drain region, it is possible to effectively reduce the contact resistance.
[0007]
[Problems to be solved by the invention]
  By the way, it is desired that both the above-described SAC and SALICIDE processes are applied simultaneously in the production of semiconductor devices of the future generation. However, there is a possibility that the following problems may occur. This problem will be described with reference to FIGS.
[0008]
  FIG. 23 shows a process for manufacturing a MOS transistor having an LDD structure. After forming a gate electrode 84 (polySi / WSix) and a source / drain region 87 in an element formation region, an interlayer insulating film 90 is interposed via a SiN etching stop film 89. The figure shows a state in which (SiOx / BPSG) is formed almost flat and resist patterning is performed thereon. The process so far will be briefly described. First, a field oxide film 82 (SiO 2) is formed on a Si substrate 81 by a known selective oxidation separation method (LOCOS) method.₂), And the gate oxide film 83 is formed by oxidizing the entire surface of the element formation region defined by the field oxide film 82. Then, a W-polycide film (polySi / WSix) and a SiOx film are sequentially stacked. The laminated film is patterned to form an offset oxide film 85 (SiOx) and a gate electrode 84. Subsequently, an LDD region is formed by low concentration ion implantation, an LDD sidewall 86 is formed by depositing the entire surface of the SiOx film and etching back, and a source / drain region 87 is formed by high concentration ion implantation.
[0009]
  Next, a thin Ti film is formed on the entire surface of the substrate, and silicidation annealing is performed to form a TiSix film 88 on the surface of the source / drain region 87. The TiSix film 88 normally has a shape that slightly rises from the element formation region onto the LDD sidewall 86 and the field oxide film 82. The length of the creeping portion increases by increasing the thickness of the Ti film first formed on the entire surface and the annealing time, and these conditions are advantageous in order to reduce the resistance. On the other hand, however, an increase in the length of the scooping portion increases process instability. Further, when the offset oxide film 85 is not provided so that the upper surface of the gate electrode 84 can be silicided, a long rising portion causes a short circuit between the gate electrode 84 and the source / drain region 87. Therefore, usually, the process is optimized so that the length of the creeping portion can be reduced as much as possible while reducing the resistance.
[0010]
  Further, after covering the entire surface of the substrate with a conformal SiN etching stop film 89, the surface of the substrate is substantially planarized by the interlayer insulating film 90. The interlayer insulating film 90 is a laminated film of, for example, a SiOx film and a boron / phosphorus / silicate / glass (BPSG) film. On this interlayer insulating film 90, a resist pattern 91 (PR) serving as a contact hole etching mask is formed. The opening 92 of the resist pattern 91 should be formed facing the center of the source / drain region 87 in an ideal state without misalignment. In the illustrated example, the opening 92 and the LDD sidewall 86 are located. It overlaps with the field oxide film 82.
[0011]
  In this state, the exposed portion of the interlayer insulating film 90 is first selectively removed by dry etching under conditions that can ensure a high selectivity with respect to the SiN etching stop film 89, and the SiN etching stop film 89 is exposed. Etching is stopped once. Next, the exposed portion of the SiN etching stop film 89 is selectively removed under conditions that can ensure a high selectivity with respect to the TiSix film 88, thereby forming a contact hole 93 as shown in FIG. However, the conditions that can ensure a high selectivity with respect to the TiSix film 88 cannot generally guarantee a high selectivity with respect to the SiOx-based material film. For this reason, when the LDD sidewall 86 and the field oxide film 82 are exposed on a part of the bottom surface of the contact hole 93, the SiOx film is eroded from the exposed portion, and a hole 94 as shown is opened. End up. When such a hole 94 exists, when performing so-called contact ion implantation for compensating for impurities in the source / drain region 87 removed during the contact hole etching and reducing the contact resistance, a base through the hole 94 is provided. Impurities are also introduced into the semiconductor device, resulting in degradation of device characteristics such as breakdown voltage degradation and increased junction leakage. If the rising length of the TiSix film 88 is increased, this problem seems to be solved at first glance, but this length cannot be increased for the reasons described above.
[0012]
  Thus, the process of applying SAC while reducing the sheet resistance and contact resistance of the source / drain regions is difficult to realize at present. It is an object of the present invention to provide a MOS transistor and a method for manufacturing the same that can satisfy both of these requirements.
[0013]
[Means for Solving the Problems]
  The MOS transistor of the present invention is proposed in order to achieve the above-mentioned object, and the field insulating film and the etching selection are formed in the region on the field insulating film where contact hole misalignment is expected to occur. With a conductive filmetchingBy forming the stopper film, even if the opening position of the contact hole is shifted, it is possible to prevent the field insulating film from being opened. Also thisetchingWhen the stopper film is also used on the gate electrode side, it is necessary to form a sidewall on the side wall surface of the gate electrode in order to prevent a short circuit between the gate electrode and the stopper film. Furthermore, in order to insulate the upper surface of the gate electrode, if an offset insulating film is formedetchingThe formation range of the stopper film can be expanded, which is more preferable.
[0014]
  the aboveetchingThe stopper film may cover the entire surface of the source / drain region or may be separated in the middle. In case of full-coverage type,etchingAll or part of the surface of the stopper film can be silicided. In the case of a partially covered type, it is effective to silicide the surface of the source / drain region corresponding to this portion in order to reduce the resistance of the separated portion.
[0015]
  Next, a method for manufacturing the above-described MOS transistor is described. First, a gate electrode andetchingWhen the stopper film is formed of another conductive film, this is basically applied to a conventionally known MOS transistor manufacturing process.etchingForming a stopper film andetchingA stopper film may be added, and a SALICIDE process is appropriately added thereto.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
  According to the present invention,etchingWhen the stopper film is made of a conductive film, at least part of the bottom surface of the contact holeetchingEven if it is placed on the stopper film, this film functions as a source / drain extraction electrode as it is, so that the contact resistance can be reduced. In addition, if the surface of the source / drain region is silicided in a self-aligned manner, the sheet resistance can be reduced. In this way, a combination of SAC and SALICIDE is possible at a practical level.
[0017]
  By the way, in a normal silicon device, a field insulating film and a side wall insulating film are formed of a silicon oxide-based material (SiOx). On the other hand, as a conductive film capable of securing an etching selectivity, W, Mo, Metal films such as Ti, Al, and Cu, metal compound films such as TiN, TiON, TiO, and WN, transition metal silicide films such as TiSix, CoSix, NiSix, WSix, MoSix, PtSix, ZrSix, and HfSix, or the upper layer side thereof Alternatively, a multilayer film in which a polycrystalline, amorphous, or single crystal Si film is laminated on the lower layer side can be given.
[0018]
【Example】
  Hereinafter, specific examples of the present invention will be described.
[0019]
  Example 1
  This embodiment is a partial type for protecting each of a field oxide film and an LDD sidewall in a MOS transistor manufacturing process.etchingA stopper film is formed using a WSix film, and both of these partial types are used in the source / drain regions.etchingIn this example, the portion exposed in the middle of the stopper film is silicided in a self-aligning manner to reduce the resistance. The process of the present embodiment will be described with reference to FIGS. However, these drawings show either one of a pMOS transistor and an nMOS transistor that constitute a CMOS transistor, and a description will be given in a form in which two types of processes are described together with respect to a portion where the processes differ between the two transistors.
[0020]
  FIG. 1 shows a state where a gate electrode 4 and a source / drain region 7 having an LDD structure are formed in an element formation region. The process so far will be briefly described. First, the field oxide film 2 (SiO 2) is formed on the Si substrate 1 by a known selective oxidation separation method (LOCOS) method.₂And the entire surface of the element formation region defined by the field oxide film 2 is thermally oxidized by a pyrogenic oxidation method to form a gate oxide film 3 having a thickness of about 10 nm. Next, a W-polycide film (polySi / WSix) having a thickness of about 140 nm and a SiOx film having a thickness of about 100 nm are sequentially laminated on the entire surface of the substrate, and the laminated film is patterned to form an offset oxide film 5 (SiOx) and a gate. An electrode 4 was formed. Subsequently, an LDD region was formed by low-concentration ion implantation, an entire surface of an SiOx film having a thickness of about 200 nm was deposited, and an LDD sidewall 6 was formed by etching back the SiOx film. Further, this substrate is carried into an oxidation furnace, and O₂After forming a channeling-preventing SiOx film (not shown) to a thickness of about 10 nm under conditions of a flow rate of 4 SLM and 800 ° C. for 10 minutes, source / drain regions 7 were sequentially formed by high-concentration ion implantation. . This high-concentration ion implantation is performed, for example, with respect to the pMOS formation region by ion species BF.₂ ⁺, Ion acceleration energy 40 keV, dose amount 3 × 10¹⁵/ Cm²In the nMOS formation region, the ion species As⁺, Ion acceleration energy 50 keV, dose amount 3 × 10¹⁵/ Cm²It went on condition of.
[0021]
  The introduced impurity is N₂Activation was performed by annealing at 1000 ° C. for 10 seconds in an atmosphere.
[0022]
  Next, LPCVD by a dichlorosilane reduction method was performed to form a WSix film 8 with a thickness of about 30 nm on the entire surface of the substrate as shown in FIG. This WSix film 8 is subjected to patterning later to form a partial type.etchingIt is a film that becomes a stopper film.
  WF₆Flow rate 2.8SCCM
  SiCl₂H₂Flow rate 300SCCM
  Ar flow rate 50SCCM
  Pressure 20Pa
  Substrate temperature 520 ° C
It was.
[0023]
  Subsequently, resist patterns 9F and 9G (PR) were formed on the WSix film 8. Here, the resist pattern 9F (subscript F indicates that it is formed on the field side; the same applies hereinafter) covers the region extending from the element formation region to the field oxide film 2, and the resist pattern 9G (subscript G is the gate side). The same applies hereinafter) covers the region from the element formation region through the LDD sidewall 6 to the end of the offset oxide film 5. This covering region is determined based on a predicted range of occurrence of overlay deviation of contact holes formed facing the source / drain regions in a later step.
[0024]
  Next, the WSix film 8 was dry-etched using a magnetic field microwave plasma etching apparatus. Etching conditions at this time are, for example,
  SF₆Flow rate 25SCCM
  Cl₂Flow rate 20SCCM
  Pressure 1Pa
  Microwave power 950W (2.45GHz)
  RF bias power 50W (800kHz)
  Substrate temperature 25 ° C (room temperature)
It was. Thereafter, ashing was performed to remove the resist patterns 9G and 9F. As a result, as shown in FIG.etchingStopper films 8F and 8G were formed.
[0025]
  Next, the substrate was washed with a buffered dilute hydrofluoric acid solution to remove a natural oxide film (not shown) on the surface of the source / drain region 7. Thereafter, magnetron sputtering was immediately performed, and a Ti film 10 having a thickness of about 30 nm was formed on the entire surface of the substrate as shown in FIG. The Ti film 10 is a raw material for forming a silicide film, and the film formation conditions are, for example,
  Target Ti
  Ar flow rate 100SCCM
  Pressure 0.47Pa
  RF power 1kW (13.56MHz)
  The substrate temperature was 150 ° C.
[0026]
  Next, two-stage RTA (rapid thermal annealing) was performed on the surface of the source / drain region 7 for silicidation in a self-aligned manner. That is, first, the substrate in the state shown in FIG. 4 is carried into the RTA apparatus.₂A first RTA was performed under the conditions of a flow rate of 5 SLM, 650 ° C., and 30 seconds to form a TiSix film having a C49 structure. Thereby, the silicide formation reaction proceeded in a self-aligned manner in the region where the exposed surface of the Si-based material layer is in contact with the Ti film 10, that is, the surface of the source / drain region 7. Here, the substrate is once treated with ammonia overwater (NH₄OH / H₂O₂In the mixed aqueous solution), the unreacted Ti film is selectively dissolved and removed.₂The second RTA was performed under the conditions of a flow rate of 5 SLM, 800 ° C., and 30 seconds. As a result, a TiSix film 11 was selectively formed on the surface of the source / drain region 7 as shown in FIG.
[0027]
  Next, as shown in FIG. 6, the entire surface of the substrate was almost conformally covered with a SiN etching stop film 12 having a thickness of about 50 nm. The film formation conditions at this time are, for example,
  SiCl₂H₂Flow rate 50SCCM
  NH₃Flow rate 200SCCM
  N₂Flow rate 200SCCM
  Pressure 70Pa
  Substrate temperature 700 ° C
It was.
[0028]
  Thereafter, an interlayer insulating film 13 (SiOx / BPSG) was laminated on the SiN etching stop film 12. This interlayer insulating film 13 is formed by sequentially forming a SiOx film having a thickness of about 100 nm and a BPSG (boron / phosphorus / silicate / glass) film having a thickness of about 500 nm having excellent reflow characteristics in this order. The film formation conditions of these films are, for example,
(Deposition conditions for SiOx film)
  CVD equipment LPCVD equipment
  SiH₄Flow rate 30SCCM
  O₂Flow rate 540SCCM
  Pressure 10.2Pa
  Substrate temperature 400 ° C
(BPSG film deposition conditions)
  CVD equipment Normal pressure conditions
  SiH₄Flow rate 40SCCM
  PH₃Flow rate 10SCCM
  B₂H₄Flow rate 13SCCM
  Pressure 101080Pa
  Substrate temperature 520 ° C
It was as follows.
[0029]
  Next, a resist pattern 14 (PR) serving as a contact hole etching mask was formed on the interlayer insulating film 13. The contact hole is ideally opened toward the center of the source / drain region 7, but in the illustrated example, the contact hole is shifted to the right toward the entire resist pattern 14 that determines the opening position. That is, the position of the opening 15 of the resist pattern 14 overlaps the LDD sidewall 6 and the field oxide film 2. FIG. 6 shows the process so far.
[0030]
  In this state, next, dry etching for opening a contact hole was performed. As an example of the etching at this time, a magnetic field microwave plasma etching apparatus is used, and the following conditions are used.
  CHF₃Flow rate 30SCCM
  CH₂F₂Flow rate 10SCCM
  Pressure 0.27Pa
  Microwave power 1200W (2.45GHz)
  RF bias power 250W (800kHz)
  Substrate temperature 20 ° C
  Overetch rate 50%
The contact hole 16 as shown in FIG. 7 was formed. Thereafter, ashing was performed to remove the resist pattern 14.
[0031]
  Conventionally, when performing contact hole etching in a SAC process using a SiN etching stop film, generally, first, the interlayer insulating film 13 is first etched under a condition that can ensure a high selection ratio with respect to the SiN etching stop film 12, and then Then, a two-step etching is performed in which the SiN etching stop film 12 is etched under a condition that can ensure a high selection ratio with respect to a member formed of a normal SiOx film, such as an offset oxide film, an LDD sidewall, and a field oxide film.
[0032]
  However, in this embodiment, the LDD sidewall 6 and the field oxide film 2 are partial types each made of WSix.etchingSince it is covered with the stopper films 8F and 8G, the etching can be performed even if the conditions that allow the SiOx-based film and the SiN film to be etched together as described above (however, the SiN film has a slower etching rate) are employed. Is this subtypeetchingStops on the stopper films 8F and 8G. Moreover, this partial typeetchingThe stopper films 8F and 8G are formed so as to cover the predicted range of occurrence of the overlay error of the contact hole 16. Therefore, even when the overlay error of the contact hole 16 is the largest, a part of the bottom surface of the stopper film is formed. Is always a partial typeetchingIt exists on the stopper films 8F and 8G. Therefore, there is no possibility that a hole is formed in the sidewall 6 or the field oxide film 2 at the time of contact hole etching.
[0033]
  Next, contact ions were implanted into the base via the contact hole 16. This ion implantation is performed for the pMOS formation region with the ion species BF.₂ ⁺, Ion acceleration energy 30 keV, dose amount 3 × 10¹⁵/ Cm²As for the nMOS formation region, the ionic species As⁺, Ion acceleration energy 30 keV, dose amount 5 × 10¹⁵/ Cm²It went on condition of. After this, N₂Impurity activation annealing was performed in an atmosphere at 850 ° C. for 30 seconds.
[0034]
  Thereafter, according to a conventional method, an upper layer wiring as shown in FIG. 8 was formed. This upper layer wiring is composed of a plug 17 (Ti / W) buried in the contact hole 16 and a wiring pattern 18 (Ti / Al) connected thereto.
[0035]
  First, the plug 17 was formed by etching back the Ti / TiN adhesion film formed by sputtering and the W film formed by blanket W-CVD. The conditions for each of these processes are for example
  (Film formation conditions for plug 17 part Ti film)
  Equipment Magnetron sputtering equipment
  Target Ti
  Ar flow rate 100SCCM
  Pressure 0.47Pa
  RF power 8kW (13.56MHz)
  Substrate temperature 150 ° C
  Film thickness 10nm
  (TiN film formation conditions)
  Equipment Magnetron sputtering equipment
  Target Ti
  Ar flow rate 40SCCM
  N₂Flow rate 20SCCM
  Pressure 0.47Pa
  RF power 5kW (13.56MHz)
  Substrate temperature 150 ° C
  Film thickness 70nm
  (W film formation conditions)
  Equipment LPCVD equipment
  WF₆Flow rate 75SCCM
  Ar flow rate 2200SCCM
  N₂Flow rate 300SCCM
  H₂Flow rate 500SCCM
  Pressure 10640Pa
  Substrate temperature 450 ° C
  Film thickness 400nm
  (Etch back condition of W film and Ti / TiN film)
  Equipment Parallel plate RIE equipment
  SF₆Flow rate
  50 SCCM
  Pressure 1.33Pa
  RF power 150W (13.56MHz)
  Substrate temperature 25 ° C (room temperature)
It was.
[0036]
  One wiring pattern 18 is formed by patterning a laminated film of a Ti barrier metal and an Al-1% Si film. The conditions of each process are, for example,
  (Ti barrier metal deposition conditions)
  Equipment Magnetron sputtering equipment
  Target Ti
  Ar flow rate 100SCCM
  Pressure 0.47Pa
  RF power 4kW (13.56MHz)
  Substrate temperature 150 ° C
  Film thickness 30nm
  (Al-1% Si film formation conditions)
  Equipment Magnetron sputtering equipment
  Target Al-1% Si
  Ar flow rate 50SCCM
  Pressure 0.47Pa
  RF power 22.5kW (13.56MHz)
  Substrate temperature 150 ° C
  Film thickness 500nm
  (Dry etching conditions for Al-1% film and Ti film)
  Equipment Magnetic field microwave plasma etching equipment
  BCl₃  60 SCCM
  Cl₂  90 SCCM
  Pressure 0.016Pa
  Microwave power 1000W
  RF bias power 50W (800kHz)
  Substrate temperature 25 ° C (room temperature)
It was.
[0037]
  The characteristic feature of the MOS transistor formed as described above is the partial type, as is apparent from FIG.etchingThe stopper films 8F and 8G are used as extraction electrodes for the source / drain regions 7. For this reason, even if a part of the bottom surface of the contact hole 16 is applied above the LDD sidewall 6 and the field oxide film 2, an increase in contact resistance is suppressed to a minimum, and a structure that is resistant to overlay errors is obtained. Has been achieved.
[0038]
  Reference example
  Next, a reference example as a premise of Example 2 described later will be described. In this reference example, the source / drain entire surface covering type for protecting the field oxide film and the LDD sidewall collectively.etchingThe stopper film was formed using a laminated film of a WSix film and a TiSix film. The process of this reference example will be described with reference to FIGS.
[0039]
  In FIG. 9, a WSix film 19 having a film thickness of about 30 nm and a polysilicon film 20 (polySi) having a film thickness of about 30 nm are laminated in this order so as to cover the entire surface of the substrate shown in FIG. A state in which the pattern 21 (PR) is formed is shown. As is apparent from the drawing, the stacking order of the WSix film 19 and the polysilicon film 20 is reverse to that of the normal W-polycide film. The film formation conditions of the lower-layer WSix film 19 are as described above in the first embodiment, for example. The polysilicon film 20 on the upper layer side is formed as a raw material for silicidation in a later process, and the film formation conditions are, for example,
  Equipment LPCVD equipment
  SiH₄Flow rate 100SCCM
  He flow rate 400SCCM
  N₂Flow rate 200SCCM
  Pressure 70Pa
  Substrate temperature 610 ° C
It was.
[0040]
  The resist pattern 21 is formed such that one edge is over the field oxide film 2 and the other edge is over the offset oxide film 5. This formation range, of course, covers the prediction range for occurrence of overlay errors in contact holes formed in a later process.
[0041]
  Next, using the resist pattern 21 as a mask, the polysilicon film 20 and the WSix film 19 were dry-etched to form a polysilicon film pattern 20a and a WSix film pattern 19a as shown in FIG. This dry etching was performed under the same conditions as the etching conditions of the WSix film 8 in Example 1 described above.
[0042]
  Next, a natural oxide film (not shown) is removed with a buffered dilute hydrofluoric acid solution, and the entire surface of the substrate is covered with a Ti film 22 having a thickness of about 30 nm as shown in FIG. Annealing was performed to change the polysilicon film pattern 20a into a TiSix film 23 as shown in FIG. The conditions for forming the Ti film 22 and the silicidation annealing conditions are all as described in the first embodiment. The WSix film pattern 19a and the TiSix film 23 formed as described above cooperate to form a source / drain entire surface covering type.etchingStopper film 24 (hereinafter referred to as full surface type)etchingThis is referred to as a stopper film 24. ).
[0043]
  Next, as shown in FIG. 13, an SiN etching stop film 25 that covers the entire surface of the substrate almost conformally and an interlayer insulating film 26 (SiOx / BPSG) that substantially flattens the entire surface of the substrate are sequentially formed. Then, a contact hole 27 was formed through resist patterning and dry etching. This dry etching is the above-mentioned whole surface typeetchingSince it stops on the stopper film 24, no hole is formed in the LDD sidewall 6 or the field oxide film 2 even if the contact hole 27 is displaced from the normal position as shown.
[0044]
  After that, as shown in FIG. 14, the contact hole 27 was filled with plugs 28 (Ti / W) according to a conventional method, and a wiring pattern 29 (Ti / Al) was formed to complete the MOS transistor. The characteristic feature of the MOS transistor formed in this way is the entire surface type, as is apparent from the figure.etchingThe stopper film 24 is in full contact with the source / drain region 7 and is used as a source / drain extraction electrode. In addition, since the portion exposed to the bottom surface of the contact hole 16 becomes a stopper film having a two-layer structure on the entire surface, there is an advantage that damage to the source / drain region 7 is small.
[0045]
  Example 2
  In this embodiment, as a modification of the reference example described above,etchingThe formation range of the TiSix film constituting the upper layer side of the stopper film 24 is limited only to the upper part of the source / drain region 7, and the part that essentially functions as the stopper film is formed of a single material film (WSix film). As a result, process stability was improved. The process of the present embodiment will be described with reference to FIGS. Each process condition is the same as that described in Example 1 and the reference example unless otherwise specified.
[0046]
  FIG. 15 shows a state where the formation position of the resist pattern 30 (PR) on the laminated film of the WSix film 19 and the polysilicon film 20 (polySi) is limited to the flat portion on the source / drain region 7. . Only the upper polysilicon film 20 was dry-etched through the resist pattern 30 to form a polysilicon film pattern 20b composed of only a flat portion as shown in FIG. Thereafter, the resist pattern 30 was removed by ashing.
[0047]
  Next, the natural oxide film is removed with a buffered dilute hydrofluoric acid solution, and the entire surface of the substrate is covered with a Ti film 31 having a thickness of about 30 nm as shown in FIG. The silicon film pattern 20b was changed to a TiSix film 32 as shown in FIG. Subsequently, the WSix film 19 was patterned through resist patterning and dry etching to form a WSix film pattern 19a as shown in FIG. The WSix film pattern 19a is extended from the gate side to the field side so as to cover a predicted range of occurrence of a contact hole overlay error formed in a later process.
[0048]
  Next, as shown in FIG. 20, an SiN etching stop film 33 that covers the entire surface of the substrate substantially conformally and an interlayer insulating film 34 (SiOx / BPSG) that substantially flattens the entire surface of the substrate are sequentially formed. Then, a contact hole 35 was formed through resist patterning and dry etching. This dry etching stops on the exposed surfaces of the TiSix film 32 and the WSix film pattern 19a. However, the TiSix film 32 mainly contributes to the reduction of the sheet resistance and contact resistance, and the LDD sidewall 6 and the field oxide film 2 Only the WSix film pattern 19a is responsible for protection. Since the etching resistance of the TiSix film 32 may fluctuate depending on the progress of the silicidation reaction, using the WSix film pattern 19a, which is unlikely to cause such fluctuation, as a substantial etching stop film makes the etching process stable. It leads to improvement in performance.
[0049]
  Thereafter, as shown in FIG. 21, the contact hole 35 was filled with plugs 36 (Ti / W) according to a conventional method, and a wiring pattern 37 (Ti / Al) was formed to complete the MOS transistor. The characteristic feature of the MOS transistor formed in this way is that the low resistance conductive film is in full contact with the source / drain region 7 and a part thereof is on the gate side, as is apparent from the figure. The extended portion can be used as a source / drain extraction electrode even when the contact hole is displaced in the overlapping direction. Therefore, both sheet resistance reduction and contact resistance reduction are realized.
[0050]
  As described above, two specific examples of the present invention have been described. However, the present invention is not limited to these examples. Process conditions such as deposition, ion implantation, dry etching, and annealing, film thickness, The device structure can be changed or selected as appropriate. For example, the device structure is not limited to the single gate type MOS transistor as described in the first and second embodiments, and a double gate type MOS transistor can be formed.
[0051]
  FIG. 22 shows a partial type as an example.etchingIt is a top view showing a double gate type MOS transistor at a stage where a stopper film is formed. Two gate electrodes 73 (shaded portions in the figure) are formed in the square element formation region defined by the edge 71 of the field oxide film 70, and the region not masked by this gate electrode 73 is the source. / Drain region 75. On the gate side, a gate-side stopper film 76G extending from the gate electrode 73 to the source / drain region 75 across the edge 74 is formed, and on the field side, the source / drain is formed across the edge 71 from the field oxide film. A field side stopper film 76F extending to the drain region 75 is formed. The gate-side stopper film 76G and the field-side stopper film 76F are formed to have a width that can cover a predicted range of occurrence of overlay deviation of contact holes formed in a later process, and the constituent materials are WSix film and W-polycide. Film, W-polycide / TiSix film, and the like.
[0052]
  In each of the above-described embodiments, the process using the SiN etching stop films 12 and 33 has been described. However, this film may be omitted. However, when the SiN etching stop film is omitted and the interlayer insulating films 13 and 34 are flattened, the stopper film is exposed to a long overetching. Therefore, when omitted, considering the etching resistance of the formation stopper, it is better to make the interlayer insulating film conformal, and if the interlayer insulating film is to be planarized, it is better to provide a SiN etching stop film.
[0053]
【The invention's effect】
  As is clear from the above description, if the present invention is applied, it is possible to secure a large margin for contact hole overlay deviation while reducing the sheet resistance and contact resistance of the source / drain regions of the MOS transistor. it can. For this reason, even if the design rule of the semiconductor device is further reduced in the future, it becomes possible to manufacture a MOS transistor that operates at high speed with a high yield.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a state where a gate electrode, an LDD sidewall, and source / drain regions are formed in a MOS transistor manufacturing process (Example 1).
FIG. 2 is a schematic cross-sectional view showing a state in which a WSix film is formed on the entire surface of the substrate shown in FIG. 1 and resist patterning is performed.
FIG. 3 shows dry etching of the WSix film of FIG. 2 to form a partial type on the field side and the gate side.etchingIt is a typical sectional view showing the state where a stopper film was formed.
4 is a schematic cross-sectional view showing a state where a Ti film for silicidation is formed on the entire surface of the substrate of FIG.
5 is a schematic cross-sectional view showing a state in which a TiSix film is formed in a self-aligned manner on a part of the surface of the source / drain region of FIG. 4 by performing silicidation annealing.
6 is a schematic cross-sectional view showing a state in which an SiN etching stop film and an interlayer insulating film are sequentially formed on the entire surface of the substrate shown in FIG. 5, and resist patterning for contact hole formation is further performed.
7 is a schematic cross-sectional view showing a state where contact holes are opened by sequentially etching the interlayer insulating film and the SiN etching stop film of FIG. 6;
8 is a schematic cross-sectional view showing a state in which an upper layer wiring is formed covering the contact hole of FIG.
9 shows a state in which a WSix film and a polysilicon film are laminated in this order on the entire surface of the substrate of FIG. 1 and further subjected to resist patterning in a MOS transistor manufacturing process (reference example) as a premise of the present invention. It is a typical sectional view shown.
10 is a schematic cross-sectional view showing a state in which the polysilicon film and WSix film of FIG. 9 are dry-etched to form a pattern extending from the gate side to the field side.
11 is a schematic cross-sectional view showing a state in which a Ti film for silicidation is formed on the entire surface of the base shown in FIG.
FIG. 12 shows silicidation annealing to change the polysilicon film of FIG. 11 into a TiSix film in a self-aligned manner, so that the source / drain entire surface covering type is obtained.etchingIt is a typical sectional view showing the state where a stopper film was formed.
13 is a schematic cross-sectional view showing a state in which contact holes are opened in an SiN etching stopper film and an interlayer insulating film which are sequentially formed so as to cover the entire surface of the base body in FIG. 12;
14 is a schematic cross-sectional view showing a state in which an upper layer wiring is formed covering the contact hole of FIG.
15 is a schematic cross-sectional view showing a state in which a WSix film and a polysilicon film are laminated in this order on the entire surface of the substrate shown in FIG. 1 in the MOS transistor manufacturing process (Example 2), and resist patterning is further performed. It is.
16 is a schematic cross-sectional view showing a state in which only the polysilicon film is etched using the resist pattern of FIG. 15 as a mask, and the pattern of the polysilicon film is left on the flat portion on the source / drain region.
17 is a schematic cross-sectional view showing a state where a Ti film for silicidation is formed on the entire surface of the substrate of FIG.
FIG. 18 is a schematic cross-sectional view showing a state where the polysilicon film pattern of FIG. 17 is changed to a TiSix film by performing self-aligned silicidation annealing.
FIG. 19 shows dry etching of the WSix film of FIG. 18 to cover the entire surface of the source / drain.etchingIt is a typical sectional view showing the state where a stopper film was formed.
20 is a schematic cross-sectional view showing a state in which contact holes are opened in an SiN etching stop film and an interlayer insulating film which are sequentially formed so as to cover the entire surface of the substrate in FIG. 19;
21 is a schematic cross-sectional view showing a state in which an upper layer wiring is formed by covering the contact hole of FIG.
FIG. 22 Partial typeetchingIt is a top view which shows the example of a layout of the double gate type MOS transistor in the step which formed the stopper film | membrane.
FIG. 23 is a schematic cross-sectional view showing a state in which a substrate subjected to self-aligned silicidation is planarized with an interlayer insulating film and further subjected to resist patterning in a conventional MOS transistor manufacturing process.
24 is a schematic cross-sectional view showing a state where holes are opened in an LDD sidewall and a field oxide film when a contact hole is opened in the interlayer insulating film of FIG. 23. FIG.
[Explanation of symbols]
1 Si substrate, 2 field oxide film, 3 gate oxide film, 4 gate electrode, 5 offset oxide film, 6 LDD sidewall, 7 source / drain region, 8G (gate side) partial typeetchingStopper film, 8F (field side) partial typeetchingStopper film, 11, 32 TiSix film, 12, 33 SiN etching stop film, 13, 34 Interlayer insulating film (SiOx / BPSG), 16, 35 contact hole, 19a WSix film pattern

Claims (4)

It becomes an etch selectivity from securable conductive film for the field insulating film formed on a silicon substrate, and is formed as covering the generating estimated range of misalignment of the contact hole to be formed in a later step etching Having a stopper film,
The etching stopper film includes a field-side extending portion extending from the element formation region to the field insulating film, and the sidewall insulation of the gate electrode whose side wall surface is covered with the sidewall insulating film from the element formation region. to the gate-side extending portion which extends toward the film, while being spaced from each other on the source / drain region, it made the extraction electrode of the source / drain regions,
The source / drain region, by silicide after the the field-side extending portion and the gate-side extending portion of the etching stopper film is deposited titanium on the surface thereof in spaced regions, the etching stopper film A MOS transistor having a silicide film formed in a self-aligned manner. It is made of a conductive film capable of ensuring an etching selectivity with respect to a field insulating film made of a SiOx film formed on a silicon substrate, and covers a predicted range of occurrence of overlay deviation of contact holes formed in a later process. It has an etching stopper film made of the formed WSix film,
The etching stopper film is formed continuously from the sidewall insulating film located on the side wall surface of the gate electrode to the field insulating film, and is used as an extraction electrode of the source / drain region.
After titanium is deposited on the polysilicon film formed on the surface of the region other than the field-side extension portion and the gate-side extension portion just above the etching stopper film and just above the source / drain regions A MOS transistor having a silicide film selectively formed by silicidation. It is possible to secure an etching selectivity with respect to the field insulating film on the entire surface of the silicon substrate on which the field insulating film, the gate insulating film, the gate electrode whose side wall surface is covered with the side wall insulating film, and the source / drain regions are formed in advance. A first step of forming a conductive film, and an etching stopper film that can cover a predicted range of occurrence of misalignment of contact holes formed in a later step by patterning the conductive film from the element formation region. A second step of forming on the sidewall insulating film and from the element formation region to the field insulating film, a third step of covering the entire surface of the substrate with an interlayer insulating film, and using the source / drain region as an overlay target And a fourth step of opening a contact hole in the interlayer insulating film. Oite,
Wherein in the second step, the field and the etching stopper film is extended over the element formation region of the insulating film, the etching stopper film and the source / drain region extending over the element formation region of the side wall insulating film Formed as spaced apart from each other above,
Between the second step and the third step , titanium is deposited on the surface of the source / drain region where the two etching stopper films are separated, and then silicided, thereby making the etching stopper film And a method of manufacturing a MOS transistor in which a silicide film is formed in a self-aligning manner. It is possible to secure an etching selectivity with respect to the field insulating film on the entire surface of the silicon substrate on which the field insulating film, the gate insulating film, the gate electrode whose side wall surface is covered with the side wall insulating film, and the source / drain regions are formed in advance. An etching stopper film capable of covering a predicted range of occurrence of misalignment of contact holes formed in a later step by patterning the conductive film, and forming a sidewall of the sidewall insulating film. A second step of continuously forming from the top to the field insulating film; a third step of covering the entire surface of the substrate with an interlayer insulating film; and contacting the interlayer insulating film using the source / drain regions as overlapping targets. In a manufacturing method of a MOS transistor having a fourth step of opening a hole,
Between the second step and the third step, silicidation is performed after titanium is deposited on the polysilicon film formed on the surface of the flat portion on the source / drain region immediately above the etching stopper film. A method of manufacturing a MOS transistor in which a silicide film is selectively formed only in a region corresponding to a region immediately above the source / drain region.

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