KR960028461A - HDIVE's motion vector predictor - Google Patents

HDIVE's motion vector predictor Download PDF

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Publication number
KR960028461A
KR960028461A KR1019940036313A KR19940036313A KR960028461A KR 960028461 A KR960028461 A KR 960028461A KR 1019940036313 A KR1019940036313 A KR 1019940036313A KR 19940036313 A KR19940036313 A KR 19940036313A KR 960028461 A KR960028461 A KR 960028461A
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South Korea
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motion vector
output
motion
code
predictor
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KR1019940036313A
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Korean (ko)
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KR0156134B1 (en
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김진경
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구자홍
엘지전자 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/513—Processing of motion vectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Television Systems (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

본 발명은 움직임 벡터 예측기에서 사용되는 개별 구성블럭을 간단하게 구현할 수 있도록 한 HDTV의 움직임 벡터 예측기에 관한 것이다.The present invention relates to a motion vector predictor of an HDTV, which enables simple implementation of individual component blocks used in the motion vector predictor.

종래의 HDTV의 움직임 벡터 예측기는 각 블럭들의 구현을 위하여 곱셈기 및 멀티플렉서 및 비교기등이 다수 필요하였으며, 이에 따라 하드웨어가 복잡해지는 단점이 있었던 점을 감안하여 본 발명은 디퍼런셜 움직임 벡터 디코더는 움직임 코드 테이블을 이용하여 입력되는 움직임 벡터에 해당하는 코드로부터 디퍼런셜 움직임 벡터를 발생하도록 하고, 움직임 벡터 예측부는 움직임 벡터 인덱스에 따라 이전 매크로블럭의 움직임 벡터가 저장되며 예측 움직임 벡터를 출력하도록 하며, 리미터로 상기 디퍼런셜 움직임 벡터 디코더의 출력과 움직임 벡터 예측부의 출력의 가산값이 움직임 벡터의 범위를 벗어날 경우 움직임 벡터의 MSB 6비트는 항상 5번째 LSB비트와 같도록하여 움직임 벡터의 범위값으로 리미트함으로써 종래와 같이 복잡한 가산기나 멀티플렉서를 사용하지 않고 보다 간단한 구성으로 움직임 벡터 예측기를 구성할 수 있도록 한 것이다.The motion vector predictor of the conventional HDTV requires a multiplier, a multiplexer, a comparator, etc. to implement each block, and accordingly, the differential motion vector decoder uses a motion code table. Generate a differential motion vector from a code corresponding to the input motion vector using the motion vector, and the motion vector predictor stores the motion vector of the previous macroblock according to the motion vector index and outputs the predicted motion vector, and the differential motion as a limiter. If the addition of the output of the vector decoder and the output of the motion vector predictor is out of the range of the motion vector, the MSB 6 bits of the motion vector are always the same as the fifth LSB bit so that the limiter is limited to the range of the motion vector. Me multi The motion vector predictor can be configured with a simpler configuration without using a flexure.

Description

에이치디티브이의 움직임 벡터 예측기HDIVE's motion vector predictor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명에 따른 디퍼런셜 움직임 벡터 디코더의 블록구성도, 제6도는 제5도 각부의 타이밍도, 제7도는 본 발명에 다른 리미터의 블럭구성도.5 is a block diagram of a differential motion vector decoder according to the present invention, FIG. 6 is a timing diagram of each part of FIG. 5, and FIG. 7 is a block diagram of a limiter according to the present invention.

Claims (4)

움직임 코드 테이블을 이용하여 입력되는 움직임 벡터에 해당하는 코드로부터 디퍼런셜 움직임 벡터를 발생하는 디퍼런셜 움직임 벡터 디코더와, 움직임 벡터의 인덱스에 따라 이전 매크로 블럭의 움직임 벡터가 저장되며 예측 움직임 벡터를 출력하는 움직임 벡터 예측부와, 상기 디퍼런셜 움직임 벡터 디코더의 출력과 움직임 벡터 예측부의 출력을 가산하는 가산기와, 움직임 벡터의 범위를 나타내는 f코드의 값에 따라 상기 가산기의 출력이 움직임 벡터의 범위를 벗어날 경우 움직임 벡터의 MSB 6비트는 항상 5번째 LSB비트와 같도록하여 움직임 벡터의 범위값으로 리미트하는 리미터로 구성됨을 특징으로 하는 HDTV의 움직임 벡터 예측기.The differential motion vector decoder generates the differential motion vector from the code corresponding to the motion vector input using the motion code table, and the motion vector of the previous macro block is stored according to the index of the motion vector, and the motion vector outputs the predicted motion vector. A predictor, an adder that adds an output of the differential motion vector decoder and an output of the motion vector predictor, and an output of the adder when the output of the adder is out of the motion vector according to a value of an f code indicating a range of the motion vector. MSB 6-bit is a motion vector predictor of the HDTV, characterized in that it consists of a limiter to limit to the range value of the motion vector always equal to the fifth LSB bit. 제1항에 있어서, 상기 디퍼런셜 움직임 벡터 디코더는 움직임 벡터에 해당하는 코드의 입력을 움직임 코드로 변환하는 움직임 코드 테이블과, 상기 움직임 코드 테이블에서 출력되는 사인, 제로신호, 움직임 코드를 각각 딜레이하는 제1-제3딜레이와, f코드값이 쉬프트양으로 입력되는 배럴 쉬프터와, 상기 배럴 쉬프터의 출력값이 양수일 경우 1을 가산하는 가산기와, 상기 배럴 쉬프터의 출력이 음수일 경우 배럴 쉬프터의 출력을 반전하는 제1반전기와, 상기 제1딜레이의 출력값인 사인값에 따라 상기 제1반전기 및 가산기의 출력을 선택하여 출력하는 멀티플렉서와, 상기 제1딜레이의 출력을 반전하여 사인값으로 출력하는 제2반전기와, 상기 멀티플렉서의 출력과 상기 제2딜레이의 반전 출력을 논리곱하여 디퍼런셜움직임 벡터값을 출력하는 앤드 게이트로 구성됨을 특징으로 하는 HDTV의 움직임 벡터 예측기.The method of claim 1, wherein the differential motion vector decoder comprises: a motion code table for converting an input of a code corresponding to the motion vector into a motion code, and a delay for sine, zero signal, and motion code respectively output from the motion code table. 1-third delay, a barrel shifter in which the f-code value is input as a shift amount, an adder for adding 1 when the output value of the barrel shifter is positive, and an output of the barrel shifter when the output of the barrel shifter is negative A multiplexer for selecting and outputting the outputs of the first inverter and the adder according to a sine value, which is an output value of the first delay, and a second inverting output of the first delay as a sine value An AND gay, for outputting a differential motion vector value by ANDing the output of the multiplexer and the inverted output of the second delay; Motion vector predictor of claim 1, characterized in that it is composed of a plurality of images. 제1항에 있어서, 상기 리미터는 상기 가산기의 출력의 사인을 선택하는 멀티플렉서와, f코드에 따른 복수의 선택신호를 발생하는 사인 선택기와, 상기 사인 선택기의 복수의 선택신호에 따라 가산기의 출력을 출력할 것인지 사인을 셋팅할 것인지를 선택하는 복수개의 멀티플렉서로 구성됨을 특징으로 하는 HDTV의 움직임 벡터 예측기.The output of the adder of claim 1, wherein the limiter comprises: a multiplexer for selecting a sine of the output of the adder, a sine selector for generating a plurality of selection signals according to an f code, and a plurality of selection signals for the sine selector. A motion vector predictor for an HDTV, comprising a plurality of multiplexers for selecting whether to output or set a sine. 제1항에 있어서, 상기 움직임 벡터 예측부는 움직임 벡터 인덱스에 따라 이전 매크로 블록의 움직임 벡터가 저장되는 복수개의 레지스터와, 움직임 벡터 포맷이 필드이고 픽춰 구조가 프레임 픽춰일 때 수직 움직임 벡터를 상기 각 레지스러에 저항 및 출력할 때 2를 곱하고 나누어지기 위한 제1, 제2쉬프터로 구성됨을 특징으로 하는 HDTV의 움직임 벡터 예측기.The register of claim 1, wherein the motion vector predictor comprises a plurality of registers storing a motion vector of a previous macro block according to a motion vector index, and a vertical motion vector when the motion vector format is a field and the picture structure is a frame picture. A motion vector predictor for an HDTV, comprising a first shifter and a second shifter for multiplying and dividing two when resistance and output to a thruster. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940036313A 1994-12-23 1994-12-23 Motion vector decoder of hdtv KR0156134B1 (en)

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KR960028461A true KR960028461A (en) 1996-07-22
KR0156134B1 KR0156134B1 (en) 1998-11-16

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