KR0156134B1 - Motion vector decoder of hdtv - Google Patents

Abstract

The present invention relates to a motion vector decoder of an HDTV, which enables simple implementation of individual component blocks used in the motion vector decoder.

In the conventional HDTV motion vector decoder, a multiplier, a multiplexer, and a comparator are required for the implementation of each block, and accordingly, the differential motion vector decoder is a modified motion code in consideration of the disadvantage of complicated hardware. A differential motion vector is generated from a code corresponding to an input motion vector using a table. The motion vector predictor stores a motion vector of a previous macro block according to a motion vector index and outputs a predicted motion vector. If the sum of the output of the differential motion vector decoder and the output of the motion vector predictor is out of the range of the motion vector, the MSB 6 bits of the motion vector are always the same as the fifth LSB bit, thereby limiting to the range of the motion vector. As complex addition This makes it possible to construct a motion vector decoder with a simpler configuration without using a device or a multiplexer.

Description

HDTV's motion vector decoder

1 is a block diagram of a motion vector decoder of a general HDTV.

2 is a block diagram of the differential motion vector decoder of FIG.

3 is a flow chart for implementing the limiter of FIG.

4 is a block diagram of a limiter according to FIG.

5 is a block diagram of a differential motion vector decoder according to the present invention.

6 is a timing diagram of each part of FIG. 5;

7 is a block diagram of a limiter according to the present invention.

8 (a) and 8 (b) are block diagrams of a motion vector storage unit according to the present invention.

9 is a table showing the relationship between the f code and the motion vector range according to the present invention.

10 is a diagram illustrating a modified motion code table according to the present invention.

* Explanation of symbols for main parts of the drawings

1: differential motion vector decoder 2: adder

3: limiter 4: motion vector storage

11: deformed motion code table 12: barrel shifter

13: adder 14-16: inverter

17: AND gate 21: sine selector

31: motion vector prediction register 31a-31g: register

32, 33: shifter

The present invention relates to an HDTV decoder, and more particularly, to a motion vector decoder of an HDTV that decodes a motion vector from a code corresponding to a motion vector.

In general, an HDTV decoder transmits image information by compressing data using a coding scheme of MPEG2. The HDTV decoder codes and transmits a coefficient motion vector in units of 16 × 16 macroblocks.

The motion vector sends a difference from the motion vector of the previous macro block so that the decoder reconstructs the motion vector in addition to the motion vector of the previous macro block and the differential motion vector currently decoded. As shown in FIG.

It consists of a differential motion vector decoder (1), an adder (2), a limiter (3), and a motion vector storage unit (4). The f code is a signal representing a range of the motion vector and the length of the code of the motion vector. When the code corresponding to the motion vector is input, the differential motion vector decoder 1 decodes the differential motion vector mvd and reads it from the motion vector storage unit 4 storing the motion vector of the previous macro block. Mv 'is added by adding the predicted motion vector pmv and the adder 2, and the limiter 3 limits the value according to the value of f code to finally output the motion vector mv.

As shown in FIG. 2, the differential motion vector decoder 1 has a comparator COMP1 and COMP2 to know whether the f code is 1 and the motion code (hereinafter referred to as mc) is 0. FIG. And an output of the NOR gate NOR1 is input to the selection terminal 5 of the multiplexer MUX1 through the delay D1.

In addition, the mc value is multiplied by -1 in the multiplier M1 when the value is negative, and is input to the input terminal 0 of the multiplexer MUX2. When the value is positive, the mc value is directly input to the input terminal 1 of the multiplexer MUX2. do.

The mc value is inputted to the selection terminal S of the multiplexer MUX2 through a comparator COMP3 to determine the sign of mc, and thus the input terminal 0 according to the value of the selection terminal S. The value of (1) is output as the output value of the multiplexer (MUX2), and the output of the multiplexer (MUX2) is added by -1 in the adder (A1) and multiplied by the f code value in the multiplier (M1) and then delayed (D3). Is added by the adder A2 and the Motion Residual value.

When the output of the adder A2 is added with 1 through the adder A3, and if the value is negative, -1 is multiplied by the multiplier M3 and then input to the input terminal 0 of the multiplexer MUX3. When the output of the adder A3 is positive, the input terminals 0 and 1 are directly input to the input terminal 1 of the multiplexer MUX3 according to a sine value input to the selection terminal S. The value of is output.

In addition, the mc value is input to the input terminal (0) of the multiplexer (MUX1) through the delay (D2) and the output value of the multiplexer (MUX3) is input to the input terminal (1) of the multiplexer (MUX1) to the delay The differential motion vector mvd is output according to the value of the selection terminal S input through D1.

The operation of the multiplier M1 and the comparator COMP3 to the adder A3 is performed by calculating mvd = (| mc | -1) * f + mr + 1, and the conventional differential motion vector decoder 1 As described above, many multipliers and multiplexers were required.

In addition, the limiter 3 determines whether the output mv 'of the adder 2 is smaller than the low of the range value of the motion vector and the maximum value of the range of the motion vector as shown in the flowchart of FIG. If the value is smaller than the minimum value, the range value of the motion vector is added to mv 'and output as a motion vector value. If the value is larger than the maximum value, the range value of the motion vector is subtracted from mv' and output as a motion vector value. 4 is implemented in hardware.

This means that the comparator COMP4 and COMP5 for comparing the output value mv 'of the adder 2 with the minimum and maximum values of the range of the motion vector and the range of the motion vector if mv' is smaller than the minimum value of the motion vector. An adder A4 for adding a value, an adder A5 for subtracting a range value of a motion vector from mv 'if mv' is greater than the maximum value of the motion vector, and the outputs of the comparators COMP4 and COMP5. Comprising a multiplexer (MUX4) for selecting the output of the adders (A4), (A5), the comparators (COMP4), (COMP5) and adders (A4), (A5) are 10-bit comparator and adder, the multiplexer (MUX4) is a 10-bit 3: 1 multiplexer.

That is, the conventional motion vector decoder requires a multiplier, a multiplexer, a comparator, etc. to implement each block as described above, and thus has a disadvantage in that hardware is complicated.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a motion vector decoder of HDTV that can implement each block with a simpler configuration by changing the algorithm for the hardware configuration of each conventional block. .

According to an aspect of the present invention, there is provided a differential motion vector decoder for generating a differential motion vector from a code corresponding to an input motion vector using a modified motion code table, and a previous macro block according to a motion vector index. A motion vector storage unit for storing and outputting a motion vector, an adder for adding the output of the differential motion vector decoder and the output of the motion vector storage unit, and an output value of the adder if the output of the adder is out of a range of a predetermined motion vector. In the motion vector decoder of the HDTV consisting of a limiter to limit the range of the motion vector accordingly.

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described in detail.

5 is a detailed block diagram of the differential motion vector decoder according to the present invention, where conventional calculation of mvd = ((| mc | -1) * f) + mr +1 is the original value of the output of the motion code table. The circuit was simplified by constructing a table (see FIG. 10) with a modified motion code (mc ') = | mc | -1 rather than a motion code.

First, a modified motion code table 11 for converting an input of a code corresponding to a motion vector into mc 'and a sign, zero signal, and mc' outputted from the modified motion code table 11 are respectively. Mc is inputted from the delays D11, D12, and D13 to be delayed, and the code corresponding to the motion vector, and mc 'and f's code values, which are outputs of the delay D13, are input. A barrel shifter 12 for calculating a value of '* f + mr', an adder 13 for adding 1 when the output value of the barrel shifter 12 is positive, and a barrel output when the output of the barrel shifter 12 is negative Inverter 14 for inverting the output of the shifter 12 and a multiplexer MUX11 for selecting and outputting the outputs of the inverter 14 and the adder 13 according to a sine value which is an output value of the delay D11. And an inverter 15 for inverting the output of the delay D11 and outputting a sine value, and the multiplexer MUX11. And AND gates 17 which multiply the output of the output by the inverter 16 of the delay D12 and output the differential motion vector mvd.

The operation of the differential motion vector decoder configured as described above is as follows. First, the code corresponding to the motion vector is converted from the transformed motion code table 11 to mc '. The transformed motion code table 11 is composed of combinatorial logic. The transformed motion code table ( 11) has table values from -16 to +16.

The modified motion code table 11 outputs a zero signal that is output as 1 when the sine and mc 'values of mc' and mc 'are 0.

If mc 'is not 0 or f is greater than 1, then mr follows mc' to the code to match the delay (D11-D13). The barrel shifter 12 processes mc '* f + mr from mc' and mr. Since f is a power of 2, * f processing is performed by shifting. F is determined by f code. When the f-code is 6 or less, the input of the barrel shifter 12 is shifted, and since the range of the motion vector ranges from -512 to 511, the motion vector can be represented by 10 bits.

If the f code is 6, mc 'becomes 5 bits and mr becomes 5 bits. Therefore, MSB 5 bits should be mc' converted to mc, and LSB 5 bits should be composed of 5 bits that enter mr. The shift amount is zero.

Thus, as the f-code changes, the remaining number of bits and the shift amount of the barrel shifter 12 are as shown in the following table.

For example, if f is 4, mc is 10, binary 01010, and mr is 6, binary 110, mc 'becomes | 10 | -1 = 9.

When mc 'and mr are combined and 7 bits 1001110 is inputted from the MSB of the barrel shifter 12, it is shifted by 2 in the barrel shifter 12 to give a 9-bit output of 001001110, which is the value of mc' * f + mr. The result is 78.

The 9-bit value output from the barrel shifter 12 is handled differently depending on whether mc 'is positive or negative. If it is positive, 1 is added through the adder 13, and if negative, 1 is added and -signed to output. do.

Taking a negative number after adding 1 to a positive number is the same as inverting all bits. When mc 'is negative, the output of the barrel shifter 12 is inverted through the inverter 14 and output.

The multiplexer MUX11 is selected by the sine value delayed by the delay D11. When the sine value is 1, mc 'is positive and 0 is negative.

The output of the multiplexer MUX11 is output by being ended with the signal inverting the output of the delay D12 at the AND gate 17. The output 9-bit signal is LSB 9 bits of mvd and is a MSB 1 bit which is a sine bit. Inverts the delayed sinusoidal signal through the inverter 15 and outputs the inverted signal.

6 is an operation timing of the differential motion vector decoder, and codes are input and output to mc'1, mc'2, ... and mr1, mr2, ... corresponding to mc 'and mr. mvd is output by one clock delay at mc '.

mc'3 is the code when mc 'is 0. mr corresponding to mc'3 is not input. At this time, the output of mvd is delayed 1 clock to mc'3 and outputs 0 value.

The limiter 3 subtracts or adds a range value when the mv 'output from the adder 2 is out of a range, that is, greater than or less than a low, and converts the value into mv, which is a value within the range. The table of 9 degrees shows the range of the motion vector according to the f code, where min is low and max is high.

When the f code is 1, only 4 bits are decoded and the upper 6 bits are fixed to 0 or 1. If the range is exceeded, a carry occurs at the 4th bit, and the 5th bit becomes B000001 xxxx different from the higher bit. At this time, if the value is higher than high, 32 should be subtracted from this value, which is equivalent to adding -32 (B1111100000), so mv becomes B111111xxxx.

Therefore, the LSB 4 bits do not change in any case and the MSB 6 bits are always the same as the 5th LSB to limit the range.

Thus, even when f code is larger than 1, MSB can be set as shown in the table of FIG.

7 shows a detailed block diagram of the limiter according to the present invention. The multiplexer MUX12 selects the sine of the output mv 'of the adder 2 to be set in the MSB of the motion vector by f code, and f Whether to output mv 'or set the sine according to the output of the sine selector 21 generating the selection signals S10-S14 according to the code and the selection signals S10-S14 of the sine selector 21; It consists of multiplexers (MUX13-MUX17) that select and output the motion vectors.

The limiter configured as described above selects the mv 'sine to be set in the MSB by the f code in the multiplexer (MUX12), and selects the MSB to be set according to the f code in the sine selector 21 in the multiplexer (MUX13-MUX17). By selecting and outputting whether to pass mv 'or setting the sine, a motion vector is generated.

The following table shows the selection signal generated by the sine selector 21 according to the f code.

8 (a) and 8 (b) show a block diagram of a motion vector storage unit according to the present invention. The motion vector storage unit is composed of a motion vector prediction register 31, which is an index of a motion vector r, 8 registers 31a-31h divided according to s, t, and 2 when storing and outputting a vertical motion vector in registers 31a-31h when the motion vector format is a field and the picture structure is a frame picture. It consists of shifters 32, 33 for multiplying and dividing.

R, s, and t are indices of the motion vectors, r represents the input sequence of the motion vectors, s represents forward and backward, and t represents horizontal and vertical.

The motion vector prediction register 31 can read and write independently like a dual port RAM, and the selection of each of the registers 31a-31h is determined by r, s, and t. 32) is to multiply by 2 when storing the vertical motion vector in registers 31a-31h when the mv format is a field and the picture structure is a frame picture, and the shifter 33 is divided by 2 when reading from the registers 31a-31h. It is to give.

As described above, the present invention changes the algorithm for implementing each block to simplify the hardware configuration of the blocks constituting the motion vector decoder of the HDTV. Thus, the motion vector is simplified without using a complicated adder or multiplexer as in the prior art. There is an effect that the decoder can be configured.

Claims (4)

A differential motion vector decoder for generating a differential motion vector from a code corresponding to an input motion vector using the modified motion code table, and a motion vector storage for storing and outputting a motion vector of a previous macro block according to the index of the motion vector. And an adder for adding the output of the differential motion vector decoder and the output of the motion vector storage unit, and a limiter for limiting the range of the motion vector according to the f code value when the output of the adder is out of the range of a preset motion vector. The motion vector decoder of the HDTV, characterized in that consisting of. The motion code table of claim 1, wherein the modified motion code table takes an absolute value to an input motion code value and subtracts '1' as a motion code, and a zero (0) value and a sign among the input motion code values. The motion vector decoder of the HDTV, characterized in that to display. The register of claim 1, wherein the motion vector storage unit comprises a plurality of registers storing a motion vector of a previous macro block according to a motion vector index, and a vertical motion vector when the motion vector format is a field and the picture structure is a frame picture. And a first shifter and a second shifter for multiplying and dividing when storing and outputting the motion vector decoder. The motion vector decoder of claim 1, wherein the limiter changes up to a set higher bit of the motion vector to the same value according to an f code value.