JP5086675B2 - Filter calculator and motion compensation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a filter computing unit using Booth's algorithm and a motion compensation device that can reduce hardware resources and power consumption. <P>SOLUTION: The filter computing unit, which multiplies-and-accumulates filter coefficients and input pixel values by Booth's algorithm, has an input part for inputting the pixel values, two or more operation parts 10<SB>j</SB>each for repeatedly decoding an output from the input part by Booth's algorithm to produce one or more code data and multiplying each of the one or more code data by the corresponding filter coefficient, input selectors 13<SB>j</SB>each for inputting an output from the input part selectively into any of the operation parts 10<SB>j</SB>, and a control part 31 for determining repeated operation cycles and repeated operation timings of each operation part 10<SB>j</SB>according to the output of the input part and controlling the input selectors 13<SB>j</SB>according to the determinations. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a filter processing apparatus suitable for executing a filter operation in a motion compensation process used for compression coding / decoding of a moving image, and a motion compensation processing apparatus including the filter processing apparatus.

  H. has been decided to be adopted for the next generation DVD (Digital Versatile Disk) and DTV (digital television). There are new codecs such as H.264 / AVC and VC-1. In these decoding apparatuses, the filter operation of the motion compensation prediction filter in the motion compensation unit may be configured by a multiplier to which Booth's algorithm is applied.

  The operation time of the multiplier is the sum of the time required to add the partial products and the time required to absorb the carry signal. In order to increase the operation speed, the processing time can be shortened. It becomes a problem. As a countermeasure, it is necessary to reduce the number of partial products in order to reduce the number of adder circuits. For this purpose, partial products can be reduced by grouping together a plurality of bits having consecutive multipliers and generating a partial product corresponding to this group. Therefore, the secondary booth is used to reduce the partial product number. The secondary booth is a partial product reduction technique to which an algorithm is applied in which a multiplier is divided every 2 bits, and a total of 3 bits of the most significant bits of each group and the lower group are combined.

  However, when the codec filter operation as described above is performed by a multiplier to which the Booth algorithm is applied, a large number of multipliers are required and the circuit scale increases. Similarly, H. When the filter operation used to generate a predicted image in the H.264 intra-screen prediction is applied by a multiplier to which the Booth algorithm is applied, the circuit scale increases.

  By the way, Patent Document 1 discloses a discrete cosine transformer in which the number of multipliers is reduced as much as possible and the circuit scale is reduced. FIG. 13 is a diagram illustrating a discrete cosine transformer described in Patent Document 1. In FIG. The discrete cosine transformer includes adders 612, 640, and 642, a difference unit 610, a register 614, multiplexers 616 and 652, multiplexer multipliers 618, 620, 622, and 634, butterfly adders 626, 628, 630, 632, and 644. , 646, 648, 650, multipliers 624, 636, 638, and a quantizer 654. Difference data by the difference unit 610 is obtained as an AC component of the image data, and DCT is performed on the difference data. Since the number of necessary coefficients is reduced by using the DCT for the difference, the number of multipliers can be reduced. Further, when multiplying different data by the same coefficient, multiplexer multipliers 618, 620, 622, and 634 are used to perform multiplication in a time division manner. For this reason, the number of multipliers can be further reduced. In addition, since the coefficient to be multiplied is previously multiplied with the quantization table of the quantizer 654, the number of multiplications can be reduced. As described above, the discrete cosine transformer described in Patent Document 1 uses the characteristics of the discrete cosine transform and performs the same operation at high speed using multiplication and butterfly operations.

Patent Document 2 discloses a signal processing apparatus that performs image signal processing such as spatial filtering in a time series. This signal processing apparatus reduces the circuit scale of a multiplier by repeatedly using the same partial product multiplier. FIG. 14 is a diagram illustrating a processor, a register circuit, and a coefficient register in the information processing apparatus described in Patent Document 2. The information processing apparatus includes an input / output buffer circuit 740, a coefficient register 711 that holds _five coefficients W _{1 to} W ₅ , and a processor 710. The input / output buffer circuit 740 includes a RAM 746 that holds pixel data for five rows and five registers 741 to 745 that respectively hold pixel data D _{1 to} D ₅ on the bus 820. The processor 710 includes two multipliers 710a and 710b, an adder 710c, a register 710d, a gate circuit 710e, multiplexers 710f and 710g on the data input side, and multiplexers 710h and 710i on the coefficient input side.

In this information processing apparatus, multipliers 710a and 710b calculate partial products P ₁ = W ₁ × D ₁ and P ₂ = W ₂ × D ₂ , respectively. The partial products P ₁ and P ₂ and the value of the register 710d are input to the adder 710c through the gate circuit 710e, the sum is obtained, and the result is held in the register 710d. A gate signal is applied to the gate circuit 710e from a control circuit (not shown), and the value in the register 710d is added to the partial product. Next, multipliers 710a and 710b calculate partial products P ₃ = W ₃ × D ₃ and P ₄ = W ₄ × D ₄ , respectively, and add them to the sum of the previous partial products. Further, the partial product P ₅ = W ₅ × D ₅ is calculated by the multiplier 710a, and zero is input to the multiplier 710b. Therefore, is added to the sum of partial products only up to the last P _5, it is held in the register 710d. The contents of the register 710d are stored in a memory cell unit (not shown) through the gate 717 and the bus 810. In this way, a fifth-order vector convolution integral can be obtained for the data D ₂ , D ₁ , D ₄ , and D ₅ adjacent to the data of interest D ₃ . Thus, in the information processing apparatus described in Patent Document 2, two multipliers 710a and 710b can be used for the degree 5 of vector convolution.
JP-A-6-44291 JP-A-62-105287

  However, the discrete cosine transformer described in Patent Document 1 has a problem that the circuit scale is large because a large-scale multiplier is used to perform multiplication at high speed. In addition, since image processing is not particularly used for general-purpose processing, when computing accuracy is required, the computing unit and the circuit scale are increased by that amount, which increases power consumption. Connected.

  In addition, the information processing apparatus described in Patent Document 2 has a problem that the computation time is three times longer than that in the case where five multipliers are provided in the processor.

  A filter arithmetic unit according to the present invention is a filter arithmetic unit that performs a product-sum operation on a multiplier and a multiplicand using a Booth algorithm, and an input unit to which the multiplier is input, and an output from the input unit according to the Booth algorithm 2 or more to obtain one or a plurality of code data, select two or more arithmetic units for performing a repetitive operation to obtain a product of the corresponding multiplicand and each of the one or a plurality of code data, and select an output from the input unit Then, an input selection selector that inputs to any of the arithmetic units, and the number of repetitive operations and the repetitive operation timing in each of the arithmetic units are determined based on the output from the input unit, and the input selection selector is selected based on the determination result. And a control unit for controlling.

  A motion compensation processing apparatus according to the present invention is a motion compensation processing apparatus that generates a predicted image, and includes a first filter arithmetic unit that performs a filter operation on vertical input data and a horizontal input data. A second filter arithmetic unit that performs a filter operation, and a weighting arithmetic unit that performs weighting on the operation results of the first and second filter arithmetic units or input data input to the first and second filter operations, The first and second filter arithmetic units are filter arithmetic units that perform a product-sum operation on input data and filter coefficients using a Booth algorithm, and a filter operation that performs a product-sum operation on a multiplier and a multiplicand using a Booth algorithm. An input unit to which the multiplier is input, and an output from the input unit according to the Booth algorithm to decode one or more codes Two or more arithmetic units that perform data calculation and perform a repetitive calculation to obtain a product of the corresponding multiplicand and each of the one or more code data, and an output from the input unit to select any one of the arithmetic units An input selection selector for input, and a control unit that determines the number of repetition operations and the repetition operation timing in each of the operation units based on an output from the input unit, and controls the input selection selector based on the determination result. is there.

  In the present invention, the number of repetitive operations and the repetitive operation timing in each operation unit are determined based on the output from the input unit, the input selection selector is controlled based on the determination result, and the output from the input unit is selected to calculate the operation unit By inputting to either of these, multiple arithmetic units can be shared with respect to the output from one input unit, reducing the number of repeated operations and reducing the processing time while reducing hardware Can be achieved.

  According to the present invention, it is possible to provide a filter arithmetic unit and a motion compensation device using a booth algorithm that can reduce the amount of hardware and power consumption.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the present embodiment, in the filter arithmetic unit using the Booth algorithm, the arithmetic unit is effectively used to reduce the number of repetitive calculations and improve the processing speed.

  First, an image decoding apparatus to which the filter arithmetic unit according to this embodiment can be applied will be described. Here, as an example, a case will be described in which the present invention is applied to a filter computing unit that executes filter computation in motion compensation processing in H.264 and VC-1. In addition, this invention is H.264. A motion compensation circuit capable of performing a filter operation in both H.264 and VC-1 standards will be described. Of course, the present invention can also be applied to a motion compensation circuit that performs a filter operation of only H.264, a motion compensation circuit that performs a filter operation of only VC-1, or other filter operation units such as MPEG (Moving Picture Experts Group) 2, 4 and the like. It is.

  First, an H.264, VC-1 image decoding apparatus will be described. 1 and 2 are block diagrams illustrating a decoding device that decodes a compressed image encoded in accordance with H.264 and VC-1. H. H.264 is also referred to as MPEG4 AVC (Advanced Video Coding), and is a compression encoding method that can make the data compression rate more than twice that of MPEG-2 and 1.5 times that of MPEG-4. VC-1 (Windows Media Video (WMV) 9) (registered trademark) is a video compression technology developed by Microsoft Corporation. The data compression rate is about the same as H.264. These advanced codecs (high compression codecs) are applied to next-generation DVD standards such as HD DVD (High Definition DVD) or Blu-ray Disc.

  As shown in FIG. 1, an H.264 image decoding apparatus 200 includes a variable length decoding unit 202, an inverse quantization unit 203, an inverse Hadamard transform unit 204, an adder 205, a deblocking filter 206, a motion The compensation unit 212, the weighted prediction unit 211, the in-screen prediction unit 210, and the monitor 209 that displays the decoded image 208 are included.

  The variable-length decoding unit 202 performs variable-length decoding on the compressed data that is input with the compressed data 201 and is variable-length encoded based on the conversion table. The decoded data subjected to variable length decoding is inversely quantized by the inverse quantization unit 203, subjected to inverse Hadamard transform by the inverse Hadamard transform unit 204, and sent to the adder 205. The output of the adder 205 is deblocked by the deblocking filter 206 to obtain a decoded image 208, which is displayed via the monitor 209.

  Here, the output of the adder 205 is also input to the in-screen prediction unit 210, and a predicted image 213 is generated. In addition, the motion compensation unit 212 performs motion compensation processing on the decoded image, and the weighted prediction unit 211 weights the decoded image to generate a predicted image 213. The adder 205 adds a prediction error to the predicted image 213 from the intra-screen prediction unit 210 and outputs the result when performing I frame processing. On the other hand, in the P and B frame processing, switching is performed by the switching unit 207, and a prediction error is added to the predicted image 213 sent from the weighted prediction unit 211 and output.

As shown in FIG. 2, the VC-1 image decoding apparatus 220 is also configured in substantially the same manner as the image decoding apparatus 200, and includes a variable length decoding unit 222, an inverse quantization unit 223, an inverse DCT conversion unit 224, and an adder. 225, a loop filter 226, a weighted prediction unit 229, a motion compensation unit 230, and a monitor 228 for displaying a decoded image 227. The VC-1 image decoding apparatus 220 is different in that it does not perform intra prediction, performs motion compensation processing after performing weighted prediction, and uses a loop filter 226 instead of the deblocking filter 206.
(3-2) Motion compensation unit

  FIG. 3 is a block diagram showing a motion compensation (MC) unit that executes a motion compensation process including a filter operation conforming to the standards of H.264 and VC-1. This motion compensation unit 300 is an H.264 standard. H.264 and VC-1 motion compensators can be used. That is, it can be shared by both standards. The motion compensation unit 300 includes filter arithmetic units 302 and 303, selectors 301, 304, 307, 310 and 313, multipliers 304 and 312, adders 306, 308 and 311, and a line memory 309.

H. In H.264, after the filter operation is performed by the filter operation units 302 and 303, a weighted interpolation signal with an offset is obtained using the above-described weighting coefficient, and a predicted image 213 is obtained. Here, the pixel value of the reference picture R0 input from the input IN is subjected to a filter operation by a vertical filter in the filter arithmetic unit 302, and is subjected to a filter operation by a horizontal filter in the filter arithmetic unit 303. The generated filter-calculated data is stored in the line memory 309. Next, when the pixel value of the reference picture R1 is input from the input IN, similarly, the filter arithmetic units 302 and 303 perform the filter operation, and the multiplier 305 multiplies the filter-calculated data by the weight coefficient. Then, the adder 306 adds the offset value. On the other hand, the data stored in the line memory is multiplied by the weighted coefficient by the multiplier 312 via the selector 313 and added by the adder 308, and the weighted interpolation signal W ₀ X ₀ + W ₁ X with offset is added. ₁ + D is generated. The generated data is output from the output OUT via the line memory 309.

In the case of VC-1, data from the input IN is input to the filter arithmetic units 302 and 303 via the selector 313 and the selector 310, further from the selector 304 via the multiplier 305 and the adder 306, and via the selector 301. The The result of the filter computing unit 303 is stored in the line memory 309 as it is via the selector 304 and the selector 307 and is output from the output OUT. In the multiplier 312, the adder 311, the multiplier 305, and the adder 306, the following weighting is executed.
H = (iScale × F + iShift + 32) >> 6
Here, F is an input value, and iScale and iShift are weighting factors.

  The motion compensator 300 configured in this way is selected by the selectors 301, 304, 307, 310, and 313 so that the inputs and outputs to the filter calculators 302 and 303 are appropriately selected. Even if it is H.264, even if it is VC-1 which performs weighting before a filter calculation, it is applicable to any calculation.

  Next, a filter arithmetic unit that can be used for such a motion compensation unit will be described in detail. In the present embodiment, H.264 is used. This filter arithmetic unit can be used as a filter arithmetic unit in MPEG4, 2 or the like.

FIG. 4 is a diagram showing details of the filter calculators 302 and 303, and is a block diagram showing the filter calculator according to the present embodiment. Since the filter calculators 302 and 303 have the same configuration, they will be described as the filter calculator 1 here. Further, in the present embodiment, in order to explain a case where a filter operation having five filter coefficients and obtaining one operation result from five pixel values is performed, five operation units 10 ₁ to 10 ₅ are provided. . However, for example, H.M. If it is H.264, the luminance signal Gy is a 6-tap filter and the color difference signal Gc is a 2-tap filter, and if it is VC-1, the luminance signal Gy is a 4-tap filter and the color-difference signal Gc is a 2-tap filter. Thus, a filter calculator corresponding to each filter coefficient is used. Note that it is also possible to prepare only a number of filter operation units or a number less than the filter coefficient, and perform the operation by repeatedly using the filter operation units.

The filter computing unit 1 according to the present embodiment includes a booth decoder and a partial product generation unit, and greatly reduces the scale of the filter computing unit by sharing the computing units 10 ₁ to 10 ₅ that perform repeated computations. The calculation processing speed is improved by using the calculation units 10 ₁ to 10 ₅ with high efficiency. Further, the subtracters 12 _{1 to} 12 ₅ take the difference between the current image data and the previous image data and perform a filter operation to reduce the amount of calculation, thereby shortening the calculation time. Further, by adding the calculation results of the calculation units 10 ₁ to 10 ₅ with one adder 21, even if adjacent calculation units are used, addition processing is performed without restoring the calculation results. be able to.

  Here, the filter arithmetic unit according to the present embodiment is a filter arithmetic unit that performs multiplication using Booth's algorithm. In order to facilitate understanding of the filter arithmetic unit according to the present embodiment, first, a multiplier using a second order Booth algorithm will be described.

Multiplier Y is a signed 8-bit integer Y = −y [7] · 2 ⁷ + y [6] · 2 ⁶ + y [5] · 2 ⁵ + y [4] · 2 ⁴ + y [3] · 2 ³ + y [2]・ 2 ² + y [1] ・ 2 ¹ + y [0] ・ 2 ⁰
Then, the product P = X × Y with the multiplicand X, which is an arbitrary integer, is as follows.

What calculates (−2 · y [2i + 1] + y [2i] + y [2i-1]) is a booth decoder, X × (−2 · y [2i + 1} + y [2i] + y [2i-1]) × 2 ²ⁱ is called partial product. In this specification, the decode value (−2 · y [2i + 1] + y [2i] + y [2i−1]) obtained by the Booth decoder is referred to as code data. In addition, a circuit for generating X × (−2 · y [2i + 1} + y [2i] + y [2i−1]) × 2 ²ⁱ (partial product) is a partial product generation unit, and X × (−2 · y [2i + 1} + Y [2i] + y [2i-1]) × 2 ²ⁱ , a circuit that generates a partial product corresponding to each i is represented by a partial product generation unit, code data (−2 · y [2i + 1] + y [2i] + y [ 2i-1]) is a booth decoder, a circuit that performs an operation consisting of code data × multiplicand to obtain a partial product is a multiplication unit, and a portion of the partial product that is to execute an operation of × 2 ²ⁱ is a bit shift unit. And

Here, as shown in Table 1 below, there are only eight combinations of values of the code data (−2 · y [2i + 1] + y [2i] + y [2i−1]), and 0, ± 1, ± 2 Takes only a value. Therefore, the multiplier can calculate a value (partial product) obtained by multiplying 0, ± X, ± 2X by 2 ²ⁱ and write it as a correspondence (truth table) of combinations of values to be added. Further, since there are only 8 values of the code data, the booth decoder can be obtained by a simple combinational logic circuit.

Of 0, ± X, and ± 2X, 2X can be generated by a 1-bit shift. On the other hand, since the multiplicand X is expressed in the complement of 2 when generating the negative number, it is only necessary to invert each bit of X and add 1 to the least significant bit. In order to realize this, for example, a circuit (Booth decoder) that generates code data (−2 · y [2i + 1] + y [2i] + y [2i−1]) Three signals including two signals for selecting an absolute value (0, X, 2X) and one signal for selecting inversion are generated. Further, the multiplication unit receives these three signals, and when the absolute value is 0, it is 0, and when it is X, the multiplicand X In the case of 2X, the multiplicand X shifted by 1 bit is selected, and if the inversion is necessary, the value can be inverted to generate a partial product. Furthermore, the bit shift unit that executes x2 ²ⁱ may simply shift the bit line by 2i.

  FIG. 5 is a block diagram showing a multiplier that performs multiplication in accordance with such a second order Booth algorithm. The multiplier 400 includes a register F0 that outputs a multiplicand X and a register F7 that outputs a multiplier Y. Furthermore, a partial product generation unit 401 that receives a multiplier Y and a multiplicand X and generates a partial product, and an adder 450 that adds the partial products generated by the partial product generation unit 401 are provided. The partial product generation unit 401 includes four partial product generation units 410, 420, 430, and 440.

  As described above, each partial product generator receives a predetermined bit of the multiplier Y, generates a code data (0, ± 1, ± 2) according to Booth's algorithm, and the obtained code data It is assumed that a multiplication unit that outputs a multiplication result with the multiplicand X and a bit shift unit that performs a bit shift of a calculation result of the multiplication unit.

Each partial product generator corresponds to “i” of X × (−2 · y [2i + 1} + y [2i] + y [2i−1]) × 2 ²ⁱ . For example, the multiplier Y is 8 bits. (Y _{0 to} y ₇ ), i = 0 to 3, and X × (−2 · y ₁ + y ₀ +0) × 2 ⁰ and X × (−2 · y ₃ + y ₂ + y _{1, respectively.} ) × 2 ² , X × (−2 · y ₅ + y ₄ + y ₃ ) × 2 ⁴ , and X × (−2 · y ₇ + y ₆ + y ₅ ) × 2 ⁶ are obtained. In FIG. 5, the partial product generators for obtaining these partial products are 410, 420, 430, and 440, respectively. In the present embodiment, the multiplier Y decoded by the Booth decoder is described by taking 8 bits as an example, but it is needless to say that the multiplier Y may be less than or more than this. In that case, what is necessary is just to adjust the number of partial product production | generation parts suitably.

Next, the operation of the multiplier 400 will be described using an actual calculation as an example. The 8-bit multiplier Y can be expressed as shown in FIG. The multiplier is divided every 2 bits, and the code data is obtained from the data of a total of 3 bits (however, y ₋₁ = 0) of the most significant bit of each group and the lower group. A partial product can be generated by multiplying these by the multiplicand X and calculating the corresponding bit shift (× 2 ⁱ ). For this reason, as shown in FIG. 6B, the register F7 is formed of a shift register that outputs 8 bits, and outputs a multiplier Y {y _{0 to} y ₇ }. At this time, the partial product generator 410 has the lower two bits {y ₀ , y ₁ } of the multiplier Y, and the partial product generators 420, 430, and 440 have {y ₁ , y ₂ , y ₃ }, { Enter y ₃ , y ₄ , y ₅ }, {y ₅ , y ₆ , y ₇ }. The partial product generation unit 410 generates a code data from these inputted predetermined bits, a booth decoder 411, a multiplication unit 412 that multiplies the obtained code data and the multiplicand X, and shifts the multiplication result by a predetermined bit. A bit shift unit 413. The other partial product generation units 420, 430, and 440 are similarly configured. Here, the multiplication of the multiplicand X = 358 (166H) and the multiplier Y = 123 (7BH) will be described. Table 2 below shows each output value in the calculation process.

Ｘ×Ｙ＝３５８×１２３＝４４０３４（ＡＣ０２Ｈ）
Ｙ＝１２３（７ＢＨ）
＝(−２・０＋１＋１)・２^６
＋（−２・１＋１＋１）・２^４
＋（−２・１＋０＋１）・２^２
＋（−２・１＋１＋０）・２^０
＝２・２^６＋０・２^４＋（−１）・２^２＋（−１）・２^０
よって、下記となる。
Ｘ×Ｙ＝{（２×３５８）×２^６} ・・・部分積生成部４１０にて演算
＋{（０×３５８）×２^４} ・・・部分積生成部４２０にて演算
＋{（−１×３５８）×２^２} ・・・部分積生成部４３０にて演算
＋{（−１×３５８）×２^０} ・・・部分積生成部４４０にて演算

X × Y = 358 × 123 = 44034 (AC02H)
Y = 123 (7BH)
= (-2 ・ 0 + 1 + 1) ・ 2 ⁶
+ (− 2 · 1 + 1 + 1) · 2 ⁴
+ (-2 · 1 + 0 + 1) · 2 ²
+ (-2 · 1 + 1 + 0) · 2 ⁰
= 2 · 2 ⁶ + 0 · 2 ⁴ + (− 1) · 2 ² + (− 1) · 2 ⁰
Therefore, it becomes the following.
X × Y = {(2 × 358) × 2 ⁶ }... Operation by partial product generation unit 410 + {(0 × 358) × 2 ⁴ }... Operation by partial product generation unit 420 + {( −1 × 358) × 2 ² }... Operation by partial product generation unit 430 + {(− 1 × 358) × 2 ⁰ }... Operation by partial product generation unit 440

First, “358” is input to each partial product generation unit 410, 420, 430, 440 from the multiplicand input unit F0. From the multiplier input unit F7, each partial product generation unit 410, 420, 430, 440 receives {y ₀ , y ₁ } = {1, 1}, {y ₁ , y ₂ , y ₃ } = {1, 0, 1}, {y ₃ , y ₄ , y ₅ } = {1, 1, 1}, {y ₅ , y ₆ , y ₇ } = {1, 1, 0} are input. The booth decoders 411, 421, 431, and 441 respectively receive (−2 · y [2i + 1} + y [2i] + y [2i−1]) = (− 2 · y ₁ + y ₀ +0), ( Code data corresponding to the calculation of (−2 · y ₃ + y ₂ + y ₁ ), (−2 · y ₅ + y ₄ + y ₃ ), (−2 · y ₇ + y ₆ + y ₅ ) is output. From the above equation, in this example, each booth decoder 411, 421, 431, 441 outputs “−1”, “−1”, “0”, “2”, respectively.

  Each of the multipliers 412, 422, 432, 442 calculates the code data × the multiplicand X and inputs them to the bit shift units 413, 423, 433, 443, respectively. The bit shift unit 413 outputs it to the adder 450 as it is. In this example, the bit shift unit 413 is provided for clarity of explanation, but it is not necessary to provide it. Bit shift sections 423, 433, and 443 shift the received results by 2 bits, 4 bits, and 6 bits, respectively, and input the result to adder 450.

  The adder 450 of this example includes full adders (full adders) 451 and 452, half adders (half adders) 453, and a register 454 for receiving the result. The values input from the bit shift units 413, 423, 433, and 443 are added by the adder 450 and output as the multiplication result P.

In this way, when the second-order Booth algorithm is used, the multiplier is set to 0, ± 1, ± 2 code data × 2 ²ⁱ and the calculation is performed with the multiplicand, so that the number of partial products is substantially halved. Therefore, the number of partial products to be added by the adder can be substantially halved, so that the multiplier can be reduced in size.

  When such a partial product generation unit is used, the filter arithmetic unit shown in FIG. 5 becomes an arithmetic circuit as shown in FIG. FIG. 7 is a diagram illustrating a filter arithmetic unit having a conventional configuration. That is, as described above, for example, if it is 8 bits, four partial product generators are required, and if it is 10 bits, for example, five partial product generators are required. FIG. 7 shows only three partial product generators for simplicity.

  Briefly describing FIG. 7, the filter arithmetic unit 501 includes registers (flip-flops: FFs) 502, 510, 511, 513, and 516, partial product generation units 503 to 505, an adder 509, adders 512 and 514, and a limiter circuit. 515. The partial product generators 503 to 505 have booth decoders 506 to 508, respectively. Pixel data is input as a multiplier Y and held in the FF 502. A value is input from the FF 502 to the partial product generation units 503 to 505 corresponding to each bit to generate a partial product. The adder 509 adds them and inputs the upper and lower bits to the FFs 512 and 511, respectively. The adder 512 adds the values from the FF 510 and the FF 511 and outputs the result to the FF 513. The adder 514 adds the value from the FF 513 and the filter coefficient B. The limiter circuit 515 sets the value of the adder 514 to 0 to 255, for example. Limit to the range and output to FF516.

This filter operator
[Output pixel] = Lim ([Input pixel] × A + B)
Execute the operation. Here, A indicates a filter coefficient. B is a predetermined constant added as needed in each filter operation. In a conventional filter arithmetic unit, data read from an external memory or the like is read in bursts. At this time, in general, when high-speed computation is performed, the pipeline processing is performed by a large-scale multiplier. For this reason, for example, if the input pixel data is 10 bits, five partial product generation units are required, which results in a large circuit scale and thus high power consumption.

Therefore, in the present embodiment, the partial product generation units 503 to 505 shown in FIG. 7 are used as one partial product generation unit, and the circuit scale is reduced and power consumption is reduced by repeatedly using one partial product generation unit. To do. In this embodiment, as will be described later, in order to perform a 5-tap filter operation, there are five operation units that perform repeated operations. Therefore, in the example shown in FIG. In addition, as described above, the calculation time can be shortened by effectively using the calculation units 10 ₁ to 10 ₅ . Furthermore, the calculation value can be reduced by using difference data of adjacent pixel values, and the calculation processing time can be further shortened.

Returning to FIG. 4, the filter computing unit 1 is a filter computing unit that performs a product-sum operation using a Booth algorithm on a pixel value that is a multiplier and a filter coefficient that is a multiplicand, and an input unit to which the pixel value is input. , Two or more arithmetic units that perform one or more arithmetic operations to obtain one or a plurality of code data by decoding the output from the input unit according to the Booth algorithm and obtain a product of the corresponding filter coefficient and each of the one or a plurality of code data 10 _j , an input selection selector 13 _j that selects an output from the input unit and inputs it to one of the arithmetic units, and determines the number of repetitive operations and the repetitive arithmetic timing in each arithmetic unit 10 _j based on the output from the input unit And a control unit 31 that controls the input selection selector 13 _j based on the determination result. Further, an adder 21 that adds all the outputs from the respective arithmetic units 10 _j, a register 22 that holds the value of the adder 21, a limiter circuit 23 that limits the value of the register 22, and an output from the limiter circuit 23 It has a register 24 for holding, and a selector 25 for selecting and outputting the output of the register 22 or 0.

The input unit includes registers F00 to F04 that store current pixel values, registers F01 to F05 that store previous pixel values corresponding thereto, and subtractors 12 _j (12 _{1 to} 12 ₅ ) that take the difference data therebetween. ) and has a selector ₁₁ 1 to 11 ₅ for selectively outputting the pixel value or zero F01～F05, register F06~F09 for storing the subtraction result, and F0A. For calculation unit ₁₀ 1 to 10 ₅ has the same structure, explaining arithmetic unit 10 _1, the arithmetic unit 10 _1, the 3 bits corresponding to the repeated number of operations to be described later of the value stored in register F06 selector 14 1 selects and outputs the _value, the selector 14 ₁ decodes according to the algorithm of the selected output value booth booth decoder 151 to generate the code _data, is with the code data coefficients (filter coefficients a) multiplying unit 16 1 for multiplying the _bets, bit shift section 17 1 for bit shifting in response to the repeated number of _operations, with the number of repetitions determining unit 18 ₁ to determine the number of multiplications by the multiplier unit 16 _1. The booth decoder 15 ₁ , the multiplier 16 ₁ , and the bit shift unit 17 ₁ constitute a partial product generator. Incidentally, determining the number of repetitions 18 ₁ selector 14 _1, and controls, based on the repetition number of calculations and its timing bit shift section 17 ₁ may perform these controls by the control unit 31.

Here, in this filter arithmetic unit 1, assuming that A to E are filter coefficients, the following description will be made assuming that the calculation is performed.
[Output Pixel] = Lim (A * F1 + B * F2 + C * F3 + D * F4 + E * F5)

  Since the data from the external memory is normally transferred in bursts in the filter computing unit 1, the data is not always input continuously. In addition, since the image data has a relatively correlation between adjacent pixels, the difference between the pixels is relatively small. By utilizing the above features, the circuit scale can be greatly reduced using a small partial product generator. At the same time, when the difference from the previous data is small, the data is output almost continuously, and even if the difference is large and the multiplication time is extended, there is a little time between burst data, so there is a considerable performance degradation. Processing can be made without Furthermore, power consumption can be reduced by reducing the circuit scale.

Furthermore, when performing a filter operation consisting of five filter coefficients as in the present embodiment, the calculation efficiency may be reduced if an operation for each filter coefficient is processed in parallel at a high speed. It may not be obtained. Or there are cases where the control becomes complicated. Therefore, in the present embodiment, the input selection selectors 13 _{1 to} 13 ₅ are provided in the preceding stage of the calculation units 10 ₁ to 10 ₅ , and the calculation efficiency is obtained using the calculation unit that has not performed the calculation process (the calculation has been completed). Improve the processing speed.

Hereinafter, the filter computing unit 1 according to the present embodiment will be described in more detail. The subtracters 12 _{1 to} 12 ₅ subtract the current image value held in the registers F00 to F04 from the previous image value held in the registers F01 to F05 to obtain difference data. The reason for this will be described. FIG. 8 is a diagram showing the amplitude distribution of the difference signal between adjacent pixels in the horizontal direction for an image (image information compression, Television Society bias, P71). The horizontal axis represents amplitude and the vertical axis represents frequency. The difference signal is concentrated in a narrow range near zero. Therefore, by obtaining the difference signal by the subtracters 12 _{1 to} 12 ₅ , a value close to 0 can be obtained. By setting the input as the difference data to a value close to 0, it is possible to minimize the number of repeated calculations described later, and to shorten the calculation processing time. This value is held in F06 to F09 and F0A. In this embodiment, the pixel value is 8 bits, and the value after subtraction is 9 bits including the sign bit.

Next, based on the subtraction results of the registers F06 to F09 and F0A, the control unit 31 obtains the number of repeated operations in the operation unit and its timing, and based on this, the number of repeated operations and the repeated operation in each of the operation units 10 ₁ to 10 ₅ Determine timing. That is, for example, the output from the register F07 not only computing unit 10 ₂ performs any operation unit ₁₀ 1, 10 ₃ as necessary.

Hereinafter, specific numerical values will be described as an example. From F00 to F05, the values 10, 11, 6, 39, 34, and 35 are input as shown in Table 3 below. In this case, the difference between the pixel values is 1, −5, 33, −5, 1 and the code data used in each multiplication unit (× 2 ⁰ , × 2 ² , × 2 ⁴ , × 2 ⁶ ) is As shown in the following table, the number of repeated computations of the computation units 10 ₁ to 10 ₅ is ₁ , 2, 4, 2, and 1 respectively. Here, when the output results of the registers F06 to F09 and F0A are respectively performed by the corresponding computing units 10 ₁ to 10 ₅ , they are assumed to be their own computations.

Control unit 31 repeats the number of operations in each of these computing section ₁₀ 1 to 10 ₅ controls the selectors _{131-134 5} so as to be as uniform as possible. In other words, a calculation unit with a large number of repeated calculations uses a calculation unit with a small number of repeated calculations to perform the calculation. In the present embodiment, the arithmetic unit 10 ₁ has its own operation and the arithmetic unit 10 ₂ of the operation once, arithmetic unit 10 ₂ is its operation once and once operation of the arithmetic unit 10 _3, an arithmetic unit 10 ₄ Each calculation unit 10 ₁ to 10 ₅ performs the calculation twice by performing one calculation of itself and the calculation of the calculation unit 10 ₃ once. If the arithmetic unit 10 ₁ to 10 ₅ is not shared by the arithmetic unit is repeatedly the number of calculations is required calculation time of the largest four times, as in the present embodiment, provided selectors _{131-134 5} By sharing the adjacent computing units 10 ₁ to 10 ₅ , it is possible to reduce the number of repeated computations in half and to speed up the computation process.

In the present embodiment, the multiplicands multiplied by the arithmetic units 10 ₁ to 10 ₅ are described as filter coefficients A to E. However, when the multiplicand is a pixel value and the multiplier is a filter coefficient, that is, When the multiplier is a predetermined value, the number of calculations is known in advance. In such a case, without providing the control unit 31, the outputs of the registers F06 to F09 and F0A may be distributed in advance so that the number of computations of the computation units 10 ₁ to 10 ₅ becomes uniform.

Next, a method for determining the number of repeated calculations and the repeated calculation timing in the controller 31 will be described. As shown in Table 3, when the number of repeated operations of each of the arithmetic units 10 ₁ to 10 ₅ is added, it is 10 in total, and it is understood that each of the arithmetic units 10 ₁ to 10 ₅ may perform the operation twice. . Therefore, the control unit 31 repeats the number of calculations of the arithmetic unit ₁₀ 1 to 10 ₅ is such that twice, and switching control of the selector _{131-134 5.} Thus, for example, it performs the arithmetic unit 10 ₁ and the operation repeated first time itself, the second iteration operation of the arithmetic unit 10 _2. Arithmetic unit 10 _2, the first iteration and arithmetic, arithmetic unit 10 ₃ repeatedly performs computation third arithmetic unit 10 ₃ of itself, repeated computation first and second times of itself. Arithmetic unit 10 ₄ performs a first repeat operation itself, the 4th repetitive operation of the arithmetic unit 10 _3. Calculation unit ₁₀₅ repeats performing the operation a second time of the first iteration operation and the arithmetic unit 10 ₄ of its own.

  On the other hand, in the case of the conventional method, as shown in Table 4, the number of repetitive calculations of the calculation unit alone is a maximum of four times. Furthermore, the total number of repeated calculations is 17. Therefore, in the case of this example, even if the adjacent calculation units are shared, the total number of repeated calculations remains four. On the other hand, when the difference between adjacent pixels is taken, the number of iterations of the computation unit alone is the maximum of 4 times, which is the same as the conventional one, but by further sharing the neighboring computation unit, the number of iterations as described above. Can be greatly reduced to twice. In the case of this example, if the difference is not taken, the number of repeated computations does not decrease, but not only the computation units adjacent in the horizontal direction as in this example, but also computation units adjacent in the vertical direction as described later. By sharing, the ability to reduce the number of operations can be improved.

  FIG. 9 is a diagram illustrating an effect when the difference between adjacent pixels is obtained and the adjacent calculation units are shared by comparing the present embodiment with the reference example. The reference example shows a case where only the difference between adjacent pixels is taken and adjacent calculation units are not shared. As shown in FIG. 9, originally, a maximum of four iterations are required, but in this embodiment, all the computations can be completed with two iterations. That is, the calculation speed can be doubled.

Here, as a specific control method of the selector 13 _j , there is a method described below. The control unit 31 obtains the total number of iterations of all computation units 10 _j and calculates the average number of iterations in each computation unit 10 _j . The average number of iterations is an integer rounded up to the decimal point, and the selector 13 _j is controlled to perform the iterations for the integer number of times. In this case, for example, the number of iterations is counted according to a sequence of 9 bits, but a table in which the number of iterations according to a sequence of 9 bits is associated in advance is prepared, as shown in FIG. There is a method of referring to the table 41 and counting the number of repeated operations of each operation unit 10 _k and controlling the selector 13 _j according to the total number of repeated operations.

As another method for obtaining the total number of repetitive operations, there is a method of detecting the sign change point by determining the sign from the higher 9 bits stored in the registers F06 to F09 and F0A. (Y ₋₁ , y ₀ , y ₁ ) = data group S 0, (y ₁ , y ₂ , y ₃ ) = data group S 1, (y ₃ , y ₄ , y ₅ ) = data group S 2, (y ₅ , If y ₆ , y ₇ ) = data group S3, (y ₇ , y ₈ , y ₈ ) = data group S4, for example, if it is −5, then when checking from the higher bit y ₈ , bit y _Since all the values up to ₃ are 1 and the bit y ₂ is 0, the change point is included in the data group S1. In this case, only the calculation of the data groups S0 and S1 has to be performed, and the number of repeated calculations is two. That is, it is only necessary to perform calculation on the data group after the change point appears. If it is 33, the change point is included in the data group S3. In this case, four groups of calculations from the data group S0 to the data group S3 may be performed, and the number of repeated calculations is four. By adding the number of repeated operations thus obtained, the total number of repeated operations can be obtained, and the average number of repeated operations can be obtained by dividing by the total number of computing units 10 ₁ to 10 ₅ .

  Furthermore, as another method for obtaining the total number of repeated operations, it may be detected for each data group whether the data group is (000) or (111). When the data group is (000) or (111), the secondary booth decoding result is 0, so that there is no need for calculation. In this case, the processing may be performed from the upper bit side, the lower bit side, or all the bits simultaneously. For example, in the case of 33, the data group S0, S2, S3 is a calculation target, and the number of repeated calculations is three. Thus, since “33” can be simply represented by 6 bits, the number of repeated operations can be reduced as compared with the case where the number of operations is four.

  FIG. 10B is a diagram illustrating an example of a circuit that detects whether the data group is (000) or (111). The 9-bit data is divided into data groups S0 to S4, which are input to the determination units 51 to 55, respectively, to determine whether they are (000) or (111). For example, if (000) or (111), 0 is output, otherwise 1 is output. The table 56 outputs the number of repetitive calculations according to the outputs of the determination units 51 to 55. At this time, information indicating which data group is to be calculated, that is, information indicating the repetitive calculation timing (hereinafter referred to as data group information) is output together.

FIG. 10C is a diagram illustrating an example of a specific circuit that determines the number of repetitive computations by detecting where the change point is located. Image data is input to the FF 61 from the upper bits. The higher order bit held in the FF 61 is compared with the next lower order input bit by the comparator 62, and for example, “0” is output if they match, and “1” is output if they do not match. The counter 63 is a down counter and counts the count value from 9 to 0. The number determination unit 64 outputs the number of repeated calculations to the selection unit 14 and the bit shift unit 17 based on the counter value when “1” is input. As described above, the control unit 31 obtains the number of repeated calculations and data group information indicating which data group requires the calculation. It should be noted that the number of repetition calculations and data group information are determined by the repetition number determination units 18 ₁ to 18 ₅ , and the control unit 31 determines the calculation to be executed by each of the calculation units 10 ₁ to 10 ₅ based on these data. Good.

The selection units 13 _{1 to} 13 ₅ select inputs from the registers F06 to F09 and F0A according to the number of repeated operations and the data group information. That is, in this example, the selection unit 13 _1, when the repetition number of calculations first, the value of the register _{F06 (y 1, y 0,} 0) = select (0,1,0), the second time In this case, the value (y ₃ , y ₂ , y ₁ ) = ( ₁ , 0, ₁ ) of the register F07 is selected. Similarly, the selection unit 13 _2, first the value of the register F07 is during operation _{(y 1,} y 0, 0) = select (1,1,0), the second is the value of the register F08 (y ₅ , y ₄ , y ₃ ) = (1, 0, 0). Selector 13 ₃ repeats the number of calculations first time, the register value of F08 _{(y 1,} y 0, 0) = select (0,1,0), the second value also registers F08 when ( y ₃ , y ₂ , y ₁ ) = (0, 0, 0) is selected. Selector 13 _4, when the repetition number of calculations first, register the value of _{F09 (y 1, y 0,} 0) = select (1,1,0), the second value of the register F08 when the ( y ₇ , y ₆ , y ₅ ) = (0, 0, 1) is selected. Selector 13 ₅ repeats the number of calculations first time, the register value of _{F0A (y 1, y 0,} 0) = select (0,1,0), the second value of the register F09 when the ( y ₃ , y ₂ , y ₁ ) = ( ₁ , 0, ₁ ) is selected.

In the present embodiment, it is described as being able to share only calculation unit adjacent to, the arithmetic unit 10 ₁ and 10 ₅ and may share. Or, for example, the arithmetic unit 10 ₁ and arithmetic unit 10 ₄ may be able to share with any of the arithmetic unit.

The booth decoder 15 _k obtains the code data shown in Table 3 from each 3-bit data group as described above. As described above, the multiplication unit 16 _k multiplies the code data by the filter coefficient A and outputs the result to the bit shift unit 17 _k .

Data group information is inputted to the bit shift section ₁₇ 1-17 _5, based on the data group information (repeated calculation timing), 0 bit shift (× ² 0, 1 bit shift (× ² 2), 2-bit shift ( × ² 4), 3-bit shift (× ^{2 6)} appropriately performed. further, in this embodiment, in the subsequent stage of the bit shift unit ₁₇ 1 to 17 _5, calculation results of all calculation unit ₁₀ 1 to 10 ₅ the order in which one adder 21 for adding all provided, for example, the output data from the F02 is computed by the next operation unit 10 _1, without returning to the original operation unit 10 _2, as adders 21 can be added and added.

  In this example, the adder 21 completes all the calculations in two times as described above. Therefore, the adder 21 adds the calculated values for two times to the previous calculated value stored in the register 22 and outputs the result. To do. The adder 21 adds the partial products obtained from the data groups S0 to S4, and adds the current addition result to the previous addition result, thereby obtaining the filter operation result of the current pixel data. it can. That is, both the previous addition result and the current addition result are composed of partial product sums obtained by multiplying the difference data by the filter coefficient A, and by adding these, the filter operation result of pixel data that is not difference data is obtained. Can do.

  The adder 21 adds the coefficient a and the like if necessary, and outputs the calculation result to the limiter circuit 23. The limiter circuit 23 outputs the result to the register 24 by limiting the operation result to fall within a range of 0 to 255, for example. The selector 25 selects 0 in the first iterative calculation and selectively outputs the value of the other register 22.

In the present embodiment, a filter arithmetic unit that includes a calculation unit 10 _j (Booth decoder 15 _j and multiplication unit 16 _j ) that performs code data × filter coefficient, and that reduces the calculation scale by repeatedly using the calculation unit 10 _j . , The number of repetitive calculations using each calculation unit 10 _j is leveled by sharing the adjacent calculation unit 10 _j . Thus, for example, when the number of repeated calculations of a certain calculation unit is four and the number of repeated calculations of an adjacent calculation unit is two, the calculation unit adjacent to one calculation unit of one calculation unit is adjacent. By performing the above, the number of computations of both can be made 3, and the maximum number of repeated computations can be reduced.

  Furthermore, since the image data is relatively correlated with the adjacent pixels, the difference between the pixels is utilized, and the difference between the current data and the next data is obtained for the input image data. The filter coefficient is multiplied and added to perform a filter operation. At this time, the input data taking the difference becomes a value in the vicinity of 0, so that the number of repeated calculations can be greatly reduced. Since data from the external memory is normally transferred in bursts, data is not always input continuously. In other words, since there is a waiting time for data input, even if repetitive calculation is included, it can be performed during the waiting time.

  As described above, the operation unit can be used repeatedly and shared, so that the circuit scale can be greatly reduced, and the number of repeated operations executed by each operation unit can be averaged to significantly reduce the processing time. it can. Further, by using the value between adjacent pixels for the calculation, the number of repeated calculations can be further reduced to reduce the power consumption.

Next, a modification of the present embodiment will be described. 11 and 12 are diagrams showing a modification example according to the present embodiment. In the above-described embodiment, it has been described that the number of repetitive calculations is reduced by sharing the calculation unit 10 _j adjacent in the horizontal direction. However, in this modification, the calculation units adjacent in the vertical direction are also shared. In this way, the number of repeated calculations is further reduced. Of course, as in the above-described embodiment, only the arithmetic unit in the vertical direction may be shared.

A filter arithmetic unit 100 shown in FIG. 11 is a collection of five filter arithmetic units 1 shown in FIG. 4, and these filter arithmetic units are designated as 1 ₁ , 1 ₂ , 1 ₃ , 1 ₄ , 1 ₅ , When there is no need to distinguish, it is referred to as a filter computing unit 1. This filter calculator 100 can simultaneously calculate five pixels in the vertical direction by connecting five filter calculators 1 in parallel. And the calculation part of the filter calculator 1 adjacent to a perpendicular direction is shared. In this modification, the five pixel values horizontally continuous in the filter operation unit 1 is input, the filter operation unit 1 _1, 1 2, _{1 3, 1 4,} 1 ₅ continuous in the vertical direction 5 In the case of a vertical filter, five pixel values that are continuous in the vertical direction are input to the filter calculator 1 ₁ , and the filter calculators 1 ₁ , 1 ₂ , 1 ₃ , Five pixel values that are continuous in the horizontal direction are input to 1 ₄ and 1 ₅ .

Filter operation unit _{1 1} includes an arithmetic unit _{10 j (10 1 ~10 5)} , the filter operation unit _{1 2} includes an arithmetic unit _{10 k (10 6 ~10 10)} , the filter operation unit _{1 3} calculation unit a 10 _l a _{(1011 15),} the filter operation unit _{1 4} has an arithmetic unit ₁₀ m ₍₁₀ 16 _{to 10 20),} the filter operation unit _{1 5} calculation unit ₁₀ n ₍₁₀ 21 _{to 10 25} ). FIG. 12 is a block diagram illustrating details of the arithmetic units 10 ₁ to 10 ₂₅ . For calculation unit ₁₀ 1 _{to 10 25} is basically has the same configuration, it will be described operation section ₁₀₇ of the filter operation unit _{1 2.}

As illustrated in FIG. 12, the calculation unit 10 ₇ is adjacent to the calculation units 10 ₆ and 10 _{8 in the} horizontal direction and shares the calculation units with each other. For this reason, the values of the registers F06 and F08 of the arithmetic units 10 ₆ and 10 ₈ are input to the selector 113, respectively. Also, in these 25 arithmetic units 10 ₁ to 10 ₂₅ , it is assumed that a control unit (not shown) controls which register 113 selects data from which the selector 113 selects data.

The arithmetic unit ₁₀₇ is in the vertical direction, adjacent to the arithmetic unit ₁₀ 2, _{10 12,} share the arithmetic unit with these operations unit. Therefore, the values of the registers F02 and F12 of the arithmetic units 10 ₂ and 10 ₁₂ are input to the selector 113, respectively. Under the control of a control unit (not shown), the selector 113 performs repetitive calculation of each calculation unit so that the number of repeated calculations of the adjacent calculation units 10 ₆ , 10 ₈ , 10 ₂ , 10 ₁₂ and the calculation unit 10 ₇ is leveled. The number of times is assigned, and in response to this, the selector 1113 is made to select an input corresponding to the calculation.

Furthermore, in this modification example, since the calculation in the vertical direction is also performed, it is necessary to return the data after the repeated calculation to the original filter calculator 1. For this reason, in the horizontal direction, the output side is also connected to the adjacent arithmetic units 10 ₂ , 10 ₁₂ , and when the selector 113 selects the values of the registers F 02, F ₁₂ of the arithmetic units 10 ₂ , 10 ₁₂ , respectively The result is output to the original arithmetic units 1 ₁ , 1 ₃ . For this reason, it has the output selection selector 114 into which the outputs of the arithmetic units 10 ₂ , 10 ₁₂ of the adjacent horizontal pixels are input. This output selection selector 114 is also under the control of a control unit (not shown), the calculation result of itself or the calculation result of the horizontal adjacent calculation unit, specifically, if the calculation unit 10 ₇ , the bit shift unit 10 ₇ output, the output of the shift register 10 _2, or selects the output of the bit shifter _{10 12,} and outputs to the adder 21. Further, the output of the arithmetic unit ₁₀₇ is input to the connected output selection selector to the output of the operational section ₁₀ 2, _{10 12.}

Of course, the control unit may be physically provided separately in the vertical direction and the horizontal direction. Also, if you want to use the operation section ₁₀₇ in both the horizontal and vertical directions, for example, priority is given to the use of horizontal operation unit, the repetitive operation may have a priority. Furthermore, to connect the filter operation unit 1 ₁ and the filter operation unit 1 ₅ in the horizontal direction, it may share the arithmetic unit in both. Furthermore, in addition to the calculation units adjacent in the horizontal and vertical directions, the calculation units 10 ₁ , 10 ₃ , 10 ₁₁ , and 10 ₁₃ may share the calculation units as long as they are in the oblique direction, that is, the calculation unit 10 _7. Good.

  Also in this modification, as described above, by sharing the calculation unit, the maximum number of repeated calculations can be reduced, and the calculation processing speed is increased. In particular, by sharing not only the horizontal calculation unit but also the vertical calculation unit, one calculation unit can make a calculation unit that can be shared, for example, a calculation unit in the vicinity of the adjacent eight, and more efficiently average the number of calculations. Can be

  Further, in this modified example, as in the above-described embodiment, a simple operation with a small selector and an adder (Full ADDER) is added, so that an operation to a calculation unit with a high operation rate is performed at a low operation rate. The calculation unit shares (consolidates) and reduces the multiple cycle time. However, when the data correlation in the vertical direction is high, the load is prevented from concentrating on the calculation unit of the filter operator in the vertical direction. Therefore, the input data is shifted, for example, by one cycle. Thus, by shifting the timing, it becomes possible to perform high-speed computation without further reducing the processing speed.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the above-described embodiment, the hardware configuration has been described. However, the present invention is not limited to this, and arbitrary processing may be realized by causing a CPU (Central Processing Unit) to execute a computer program. Is possible. In this case, the computer program can be provided by being recorded on a recording medium, or can be provided by being transmitted via the Internet or another transmission medium.

It is a block diagram which shows the decoding apparatus which decodes the compressed image encoded based on H.264. It is a block diagram which shows the decoding apparatus which decodes the compressed image encoded based on VC-1. It is a block diagram which shows the motion compensation (MC) part which performs the motion compensation process containing the filter calculation based on the specification of H.264 and VC-1. It is a block diagram which shows the filter arithmetic unit concerning embodiment of this invention. FIG. 3 is a block diagram illustrating a multiplier that performs multiplication according to a second order Booth algorithm. (A) is a figure explaining the bit used for code | cord | chord data generation by Booth's algorithm, (b) is a figure which shows the detail of the partial product production | generation unit of the multiplier shown in FIG. It is a figure which shows the conventional filter calculator. It is a figure which shows the amplitude distribution of the difference signal between the adjacent pixels of the horizontal direction about an image. It is a figure which shows the specific example which counts the total number of repetitive calculations in the control part of the filter arithmetic unit concerning embodiment of this invention. (A) is a figure which shows the calculation timing of the filter arithmetic unit concerning this Embodiment, (b) is a figure which shows the calculation timing of the conventional filter arithmetic unit shown in FIG. It is a figure which shows the filter computing unit concerning the modification in embodiment of this invention. It is a figure which shows the detail of the calculating part of the filter arithmetic unit concerning the modification in embodiment of this invention. It is a figure which shows the discrete cosine transformer of patent document 1. FIG. 11 is a diagram illustrating a processor, a register circuit, and a coefficient register in the information processing apparatus described in Patent Document 2.

Explanation of symbols

1,11,1 _{2, 1 3,} 1 _4, 1 5, 100,302,303,501 filter operation unit _{10 1 ~10 25, 10 j,} 10 k, 10 l, 10 m, 10 n arithmetic unit 11, 11 ₁ to 11 _5, 25,301,304,307,310,313 selector _{12 j,} 12 1 to 12 ₅ subtractor 13 _{1-13 5,} 113 input selection selector 14, 14 ₁ to 14 ₅ selector 15 _j , 15 ₁ to 15 ₅ , 506 to 508 Booth decoder 16 _j , 16 _{1 to} 16 ₅ , 503 to 505 Partial product generation unit 17, 17 _{1 to} 17 ₅ , 413, 423, 433, 443 Bit shift unit 18 ₁ to 18 ₅ repeat count determination unit 21 adder 22, 24 registers 23 the limiter circuit 31 the control unit 41,56 table 51 to 55 judging unit 62 comparator 63 counts 64 Number determination unit 200, 220 Image decoding device 201, 221 Compressed data 202, 222 Variable length decoding unit 203, 223 Inverse quantization unit 204 Inverse Hadamard transform unit 205, 225 Adder 206 Deblocking filter 207 Switching unit 208, 227 Decoding Image 209, 228 Monitor 210 In-screen prediction unit 211, 229 Weighted prediction unit 212, 230, 300 Motion compensation unit 213, 233 Predicted image 224 Inverse DCT transform unit 226 Loop filter 304, 305, 312, 400, 412, 422, 432 , 442 Multiplier 306, 308, 311, 450, 612 Adder 309 Line memory 401 Partial product generation unit

Claims (12)

A filter arithmetic unit that performs a product-sum operation on a multiplier and a multiplicand using a Booth algorithm,
An input unit for inputting the multiplier;
The sought by decoding one or more encoded data output from the input unit in accordance with Booth's algorithm, two or more operations to perform the iterative operations for obtaining the product of the respective corresponding said multiplicand and the one or more encoded data And
An input selection selector that selects an output from the input unit and inputs it to one of the two or more arithmetic units;
A filter arithmetic unit comprising: a control unit that determines the number of repeated calculations and a repeated calculation timing in each of the two or more calculation units based on an output from the input unit, and controls the input selection selector based on the determination result . The filter arithmetic unit according to claim 1, wherein the input unit includes a subtractor that obtains a difference between current input data and previous input data, and outputs the subtraction result. Has one of the first adder for adding the respective output results of the two or more arithmetic unit,
The input unit includes a subtractor that obtains a difference between current input data and previous input data, and outputs the subtraction result.
The first adder, the cumulative result obtained from the input of the input data of the previous result of the subtraction of claims 1 filter operation, wherein the cumulative addition of the multiplication result obtained by the arithmetic unit vessel. The input unit is provided corresponding to each arithmetic unit,
The input selection selector, said each arithmetic unit provided in correspondence, the input unit corresponding to the self, and by selecting one of the output from the input unit pixel value is input horizontally adjacent The filter arithmetic unit according to claim 1, wherein the filter arithmetic unit inputs to the arithmetic unit corresponding to the self. The input unit is provided corresponding to each arithmetic unit,
The input selection selector provided corresponding to each of the arithmetic unit, output from the input unit corresponding to the self, and one of the output from the input unit pixel value is input vertically adjacent The filter arithmetic unit according to claim 1, wherein the filter arithmetic unit is selected and input to the arithmetic unit corresponding to itself. The input unit is provided corresponding to each arithmetic unit,
The input selection selector provided corresponding to each of the arithmetic unit, one of the outputs from the input unit outputs of the input unit corresponding to the self, the well is pixel values adjacent in the horizontal and vertical directions is input select filter operation unit according to claim 1 or 2, wherein the input to the arithmetic unit corresponding to the self. A second adder provided corresponding to each horizontal direction for adding output results obtained by each of the two or more arithmetic units based on one horizontal pixel value;
An output selection selector that selects an output result obtained by the arithmetic unit based on one horizontal pixel value to be added by the second adder provided corresponding to the horizontal direction;
The input unit includes a subtractor that obtains a difference between current input data and previous input data, and outputs the subtraction result.
The second adder, based on the value selected from the output selection selector, adds the result obtained by subtracting the pixel value in the horizontal direction to the accumulated result obtained from the previous input data input in one horizontal direction. The filter arithmetic unit according to claim 5 or 6, wherein the multiplication results obtained by the arithmetic unit are cumulatively added. The computing unit is
A selection unit that divides the output data output from the input unit every two bits from the lower order and selects a total of 3 bits, one of each set and the most significant bit of the lower set,
A Booth decoder to generate the code data decoding in accordance with the Booth algorithm 3-bit data output from the selector,
A multiplier for obtaining a product of the code data and the multiplicand;
The filter arithmetic unit according to claim 1, further comprising: a bit shift unit that shifts an output result from the multiplier by a predetermined bit. The control unit searches for a position where there is a change in the bit value in order from the upper bit of the subtraction result output from the input unit, which is the difference between the current input data and the previous input data. The filter arithmetic unit according to any one of claims 1 to 8, wherein the number of repetitive operations and the repetitive operation timing are determined based on the search result. The control unit changes the bit value for all bits from the lower bit to the upper bit of the subtraction result output from the input unit, which is the difference between the current input data and the previous input data. searches the is located, the repetition number of operations and filter operation unit of any one of claims 1 to 8, characterized in that determining the repeat calculation timing based on the search results. The control unit divides a subtraction result output from the input unit, which is a difference between the current input data and the previous input data, every two bits from the lower order, as a group per total of three-bit bit, for each group, determines whether all the bit values are either identical, and determines the repetition number of operations and the repetitive operation timing based on the determination result The filter arithmetic unit according to any one of claims 1 to 8. A motion compensation processing device for generating a predicted image,
A first filter calculator for performing a filter operation on the input data in the vertical direction;
A second filter arithmetic unit that performs a filter operation according to horizontal input data;
A weighting operation unit that performs weighting on the operation results of the first and second filter operation units or input data input to the first and second filter operations,
The first and second filter arithmetic units are filter arithmetic units that perform a product-sum operation on input data and filter coefficients using a Booth algorithm,
A a multiplier and multiplicand filter calculator for calculating a product sum with the Booth algorithm,
An input unit for inputting the multiplier;
The sought by decoding one or more encoded data output from the input unit in accordance with Booth's algorithm, two or more operations to perform the iterative operations for obtaining the product of the respective corresponding said multiplicand and the one or more encoded data And
An input selection selector for selecting an output from the input unit and inputting the output to any of the arithmetic units;
A motion compensation processing apparatus comprising: a control unit that determines the number of repetition calculations and a repetition calculation timing in each of the two or more calculation units based on an output from the input unit, and controls the input selection selector based on the determination result.

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