JP5668391B2 - Arithmetic circuit - Google Patents

Description

  The present invention relates to an arithmetic circuit.

  In recent years, product-sum operations are frequently used in vector calculation processing in coordinate transformation performed at the time of drawing an image, digital filter processing of audio data, and the like. The product-sum operation is an operation for obtaining the sum of products, that is, an operation for sequentially adding the results of multiplication. For example, in the calculation of an FIR (finite impulse response) filter, which is an operation of digital filter processing, product-sum operation is used as processing for multiplying image and audio data by a coefficient and cumulatively adding them. In such digital filter processing, it is possible to improve the overall processing speed by improving the processing speed of the product-sum operation.

  In the digital filter processing as described above, some of the values of the image and audio data are updated, and the coefficients are not updated. Therefore, the arithmetic circuit does not need to repeat the product-sum operation for all input data. However, the conventional arithmetic circuit requires time for the product-sum operation processing by performing the product-sum operation based on all input data. Thus, for example, an arithmetic circuit as disclosed in Patent Document 1 has been proposed.

Japanese Patent No. 2530916

  However, in the arithmetic circuit of Patent Document 1, although a product-sum operation value can be obtained when fixed data is updated among input data, a product-sum operation value when arbitrary data is updated is obtained. I can't.

  Further, the processor performs not only product-sum operations but also various operations based on combinations of addition / subtraction, multiplication, logical product, logical sum operation, and the like. Similarly, in such other combinational operation circuits, when any value in the input data is updated, it takes time for the calculation by recalculating all the input data.

  Therefore, an object of the present invention is to provide an arithmetic circuit capable of calculating an arithmetic result corresponding to input data in which an arbitrary value is updated at high speed with a small number of processing cycles.

A first aspect includes a first register holding a first value having N elements;
A second register holding a second value having N elements;
An output register for holding a product-sum operation value obtained by performing a product-sum operation on the first value and the second value;
A first subtractor for subtracting the element of the first value in the first register corresponding to the element from one of the elements of the input first value;
A multiplier that multiplies the output of the first subtractor with the element of the second value in the second register corresponding to the element of the input first value;
An adder that adds the output of the multiplier and the product-sum operation value of the output register and outputs the result to the output register.

  According to the first aspect, calculation results corresponding to input data in which an arbitrary value is updated can be calculated at high speed with a small number of processing cycles.

It is an example of a system having a dedicated product-sum operation circuit. It is a figure showing an example of the product-sum calculator in Formula 1. FIG. 3 is a diagram illustrating an example of a circuit that connects the product-sum calculator of FIG. 2 to a bus. is a diagram showing operation waveforms in the multiply-add unit when a ₀ ~a ₇ is updated. is a diagram showing the operation waveforms in the product-sum operation circuit when only a ₂ is updated. It is a figure showing an example of the sum-of-products calculator in the example of this Embodiment in Formula 2. It is a figure showing the circuit which connects the product-sum operation unit of FIG. 6 to a bus | bath. a ₀ ~a ₇ is a diagram showing operation waveforms in the multiply-add unit 6 when being updated. Only a ₂ is a diagram showing operation waveforms in the multiply-add unit 6 when it is updated. It is a figure showing an example of the sum-of-products calculator in the example of this Embodiment in Formula 3. It is a figure showing an example of the sum-of-products calculator in the example of this Embodiment in Formula 4. It is a figure showing an example of the product-sum calculator in the example of a 4th embodiment. It is a 1st arithmetic circuit in a 5th example of an embodiment. It is the 2nd arithmetic circuit in a 5th example of an embodiment. It is a figure showing the circuit which connects the circuit of FIG.13 and FIG.14 to a bus | bath. It is a figure showing an example of the circuit in this Embodiment in Formula 7.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

  FIG. 1 is an example of a system 10 having a dedicated product-sum operation circuit. A system 10 in FIG. 1 includes a CPU 11 and a DMAC 12, a memory 13, a dedicated product-sum operation circuit 14 (hereinafter referred to as a product-sum operation unit), and other hardware 15. The CPU 11 sends the instruction read from the memory 13 to the product-sum operation circuit 14 via the bus 16, and the product-sum operation circuit sends the operation result to the CPU 11 via the bus 16. The DMAC 12 controls data transfer not via the CPU 11 such as between the other hardware 15 and the memory 13.

  Specifically, the CPU 11 exchanges data with the product-sum calculator 14 through read and write processing with respect to the address assigned to the product-sum calculator 14. For example, when data is written from the CPU 11 to the product-sum operation unit 14, the CPU 11 issues the address, write data, timing signal, and write mode signal of the product-sum operation unit 14 to the bus 16. The product-sum operation unit 14 detects these signals, determines that the issued address is the address of the product-sum operation unit 14, and takes in data from the bus 16. On the other hand, when outputting data from the product-sum calculator 14, the CPU 11 issues an address and timing signal of the product-sum calculator 14 to the bus 16, and sends the data supplied from the product-sum calculator 14 to the bus 16. Capture from.

  The product-sum operation circuit 14 generally calculates a product-sum operation value based on the following equation 1. In Equation 1, the product-sum operation value “S” is a product-sum operation value of the values “a” and “b”.

Value "a", n elements _{"a 0, a 1, ...,} a n-1 ", the value "b" n elements _{"b 0, b 1, ...,} b n-1 ", respectively Have. In Equation 1, a product-sum operation value “S” is calculated by sequentially adding a multiplication value “a _i × b _i ” of a set of i (0 ≦ i ≦ n−1) -th elements of each value. Is done.

FIG. 2 is a diagram illustrating an example of a product-sum calculator when “n = 8” in Equation 1. In the product-sum operation unit shown in the figure, the elements a _{0 to} a ₇ of the value “a” are input to the registers R 00 to R 07, and the elements b _{0 to} b ₇ of the value “b” are input to the registers R 10 to R 17. The In the product-sum operation unit shown in the figure, all or a part of the values “a” and “b” are input as the input signal input and written into the corresponding register. Subsequently, an operation is performed using element data of all values “a” and “b” held in the register, and a product-sum operation value “S” is output to the output register OUT.

  In the product-sum calculator of FIG. 2, first, each element data (input update data) to be calculated is input as an input signal input, and a register corresponding to the input update data responds to the write signals write_0_0 to write_1_7, Input update data is written. When all the input update data is written, the input signal start is input to the counter CNT and the delay unit DELA. In response to the input signal start, the counter CNT outputs a signal incremented from 0 every time the clock rises to the comparator COM and the selectors SELA and SELB.

  The selectors SELA and SELB output the data held in the register corresponding to the select signal select1 to the multiplier MUL in response to the select signal select1 (0 to 7) from the counter CNT. Specifically, for example, when the select signal select1 is “0”, the selector SELA outputs the data in the register R00, and the selector SELB outputs the data in the register R10 to the multiplier MUL. The multiplier MUL multiplies each data of the corresponding element set of the values “a” and “b” inputted simultaneously and sequentially outputs them to the adder ADD. The adder ADD and the previous addition The outputs of the adder ADD are sequentially added.

  On the other hand, when the select signal select1 from the counter CNT is “7”, the comparator COM outputs a signal to the delay device DELB. The delay device DELB delays the output signal from the comparator COM to the timing at which all sets of multiplication results are added, and outputs the write signal write to the output register OUT. The delay unit DELA delays the input signal start just before the first set of multiplication values are added, outputs a reset signal reset to the adder ADD, and initializes it beforehand with “0”.

  FIG. 3 is a diagram illustrating an example of a circuit that connects the product-sum calculator of FIG. 2 to a bus. In FIG. 1, the bus 16 of FIG. 1 has a control bus CB, a data bus DB, and an address bus AB. When an access occurs in the product-sum operation unit in FIG. 2, an address assigned to the product-sum operation unit is output to the address bus AB, and a signal indicating the timing at which a valid address flows is output to the control bus CB.

  Then, the gate G1 detects the effective address, and the comparators C00 to C17 compare the detected addresses with the addresses assigned to the corresponding registers (registers R00 to R07), respectively, and correspond to the addresses when they match. The write signal write _ * _ * (write_0_0 to write_1_7) to be sent is sent to the product-sum calculator of FIG. Further, the comparator C20 compares the detected address with the address for issuing the input signal start, and when they match, sends the input signal start to the product-sum calculator of FIG.

  The gate G4 detects data transmitted from the data bus DB and a signal indicating the timing at which valid data is detected from the control bus CB, and outputs the input data of the data bus DB as an input signal input. Further, the gate G2 detects the effective address, and the comparator C30 compares the detected address with the address of the output register OUT of the product-sum calculator, and if they match, the output value output of the output register OUT is output from the gate G3. Output to the data bus DB.

FIG. 4 is a diagram illustrating operation waveforms in the product-sum calculator of FIG. 2 when “a _{0 to} a ₇ ” is updated. In this example, “b _{0 to} b ₇ ” are held in the registers R10 to R17 in advance. “P _i ” is a multiplication value “a _i × b _i ” of each set of elements, and “S _i ” represents a product-sum operation value up to the i-th set.

In the operation waveform diagram of FIG. 4, first, “a ₀ ” is input as the input signal input, and “a ₀ ” is written to the register R 00 at the next clock rising timing in response to the write signal write — _{0 — 0} . Similarly, _"a 1 ~a _7" are sequentially input as the input signal input The _"a 1 ~a _7" is written to the register R01~ register R07. Then, the input signal start is output to the counter CNT at the rising timing of the clock next to the input of “a ₇ ”.

In response to the input signal start, the counter CNT outputs each signal incremented from 0 to 7 at each rising edge of the clock to the selectors SELA and SELB and the comparator COM. First, in response to the select signal select1 “0”, the selector SELA selects the data “a ₀ ” in the register R00, and the selector SELB selects the data “b ₀ ” in the register R10 and outputs it to the multiplier MUL. Subsequently, at the rising timing of the next clock, the multiplier MUL multiplies “a ₀ ” and “b ₀ ” and outputs the multiplication value “p ₀ = a ₀ × b ₀ ” to the adder ADD.

The delay unit DELA outputs a reset signal reset to the adder ADD in response to the start signal start, and initializes the adder ADD to “0” before the first set of multiplication values “p ₀ ” is input. Keep it. Therefore, the adder ADD first outputs an addition value “S ₀ = 0 + p ₀ ” between the initial value “0” and the multiplication value “p ₀ ” output from the multiplier MUL. Similarly, at the next clock, the adder ADD outputs “p _i = a _i × b _i ” from the multiplier MUL and the output value “p _i−1 ” from the adder ADD of the previous clock. ”And“ S _i = p _i−1 + p _i ”are output. Further, the comparator COM outputs a comparison signal to the delay device DELB when the output signal of the counter CNT becomes 7, and the delay device DELB has a timing at which all sets of multiplication results “p _{0 to} p ₇ ” are added. The write signal write to the output register is output.

As described above, the product-sum operation unit of FIG. 2 starts the product-sum operation after all the input update data “a _{0 to} a ₇ ” are stored in the register. Therefore, it takes time until the operation result is obtained. It was. Accordingly, the product-sum calculator of FIG. 2 takes 20 cycles from the start of input of the data “a _{0 to} a ₇ ” until the product-sum operation value “S ₇ ” is calculated. Next, a case where only one data among “a _{0 to} a ₇ ” is updated will be described.

FIG. 5 is a diagram illustrating operation waveforms in the product-sum operation circuit of FIG. 2 when only “a ₂ ” of “a _{0 to} a ₇ ” is updated. In this example, “b _{0 to} b ₇ ” are held in the registers R 10 to R 17 in advance, and “a _{0 to} a ₇ ” except for “a ₂ ” are held in the registers R 00 to R 07 except for the register R 02 in advance. Note that “p _i ” and “S _i ” are the same as those in the operation waveform diagram of FIG.

In the operation waveform diagram of FIG. 5, first, “a ₂ ” is input as the input signal input, and “a ₂ ” is written to the register R 02 at the next clock rising timing in response to the write signal write — 0 — ₂ . Then, the input signal start is output to the counter CNT at the rising timing of the clock next to the input of “a ₂ ”, and the counter CNT outputs the signals incremented from 0 to the selectors SELA, SELB and the comparator COM. To do. In the same manner as in FIG. 4, the selectors SELA and SELB select the data sets held in the registers corresponding to the select signals select1 of “0 to 7” and sequentially output them to the multiplier MUL. Sequentially outputs the multiplication value “p _i (= a _i × b _i )” of each set of data to the adder ADD. The adder ADD sequentially adds all sets of multiplication values “p _i ” and outputs a product-sum operation value “S ₇ ” to the output register OUT.

As described above, the product-sum operation unit of FIG. 2 performs the product-sum operation on all the data held in the register even if only “a ₂ ” of “a _{0 to} a ₇ ” is updated. I was doing it again. Further, since the product-sum operation unit in FIG. 2 performs the product-sum operation again on all the data to be calculated, the operation is started after all the data is written to the register.

As a result, the product-sum operation unit shown in FIG. 2 recalculates the product-sum operation after all the data stored in the register is stored in the register, so that all the input update data is stored in the register. The data transfer time up to and the calculation time of all data of multiplication and addition are required, and it takes time until the product-sum operation value is obtained. Therefore, in the product-sum calculator of FIG. 2, even if only “a ₂ ” is updated, the product-sum operation value “S ₇ ” is calculated after the data “a ₂ ” starts to be input. It took 13 cycles.

<First Embodiment>
Therefore, the arithmetic circuit according to the present embodiment includes a first register that holds a first value having N elements, a second register that holds a second value having N elements, And an output register for holding a product-sum operation value obtained by multiply-accumulating the first and second values. The arithmetic circuit according to the present embodiment includes a subtracter that subtracts an element of the first value in the first register corresponding to the element from one element of the input first value, A multiplier for multiplying the output of the multiplier by an element of the second value in the second register corresponding to the element of the input first value, and the product-sum operation value of the output of the multiplier and the output register And an adder for adding and outputting to the output register.

The product-sum operation unit according to the present embodiment calculates a product-sum operation value based on the following Equation 2. In Equation 2, the value “a ′ = (a ₀ ′, a ₁ ′, a ₂ ′,..., A _n−1 ′)” is an old value “a = (a ₀ , a ₁ , A ₂ ,..., A _n-1 ) ”, the j-th element is updated. The elements other than the jth value “a” and “a ′” are the same without change. “S” is the product-sum operation value of “a” and “b” (hereinafter, the previous product-sum operation value), and “S ′” is the product-sum operation value of “a ′” and “b” ( Hereinafter, the product-sum calculation value after update) is represented.

In Equation 2, the updated product-sum operation value “S ′” is obtained by adding the difference value between “S ′” and “S” to the previous product-sum operation value “S”. Specifically, the updated product-sum operation value “S ′” is obtained by multiplying the multiplication value “a _j × b _j ” of the j-th element of the values “a” and “b” from the previous product-sum operation value “S”. A value obtained by subtracting and adding the multiplication value “a _j ′ × b _j ” of the j-th element of the values “a ′” and “b” (S ′ = S− (a _j × b _j ) + (a _j ′ × b _j )). This arithmetic expression is summarized as “S ′ = S + (a _j ′ −a _j ) × b _j ”. Therefore, the updated product-sum operation value “S ′” is calculated by adding the difference value “(a _j ′ −a _j ) × b _j ” to the previous product-sum operation value “S”.

  Comparing Expression 1 and Expression 2, when some elements of the value are updated, the amount of calculation of Expression 2 is smaller than that of Expression 1. Therefore, Equation 2 can calculate the updated product-sum operation value “S” with fewer processing cycles than Equation 1.

FIG. 6 is a diagram illustrating an example of a product-sum calculator in the present embodiment when “n = 8” in Expression 2. Similar to the product-sum operation value of FIG. 2, in the product-sum operation unit of FIG. 6, each element a ₀ ′ to a ₇ ′ of the value “a ′” is stored in the registers R00 to R07 and each element b of the value “b” is stored. ₀ ~b ₇ is stored in the register R10-R17. Further, the product-sum calculator in the present embodiment holds the previous data “a _{0 to} a ₇ , b _{0 to} b ₇ ” in the registers R 00 to R 17, and the previous product-sum operation value “S” in the output register. To do.

  In the product-sum operation unit of FIG. 6, the number s10 of the set to be updated represents a set corresponding to the input update data input as the input signal input. The logical sum s0 from write_0_0 to write_0_7 represents the presence or absence of input update data stored in any of the registers R00 to R07. When the logical sum s0 from write_0_0 to write_0_7 is at H level, the input update data is in the registers R00 to R07. Indicates that it is stored in any of the above, and in the case of the L level, it is not stored in any of them. Similarly, the logical sum s1 of write_1_0 to write_1_7 represents the presence or absence of input update data stored in any of the registers R10 to R17.

  In the product-sum calculator of FIG. 6, input update data of either the value “a” or the value “b” is input as the input signal input. Then, the difference value between the input update data input and the previous data based on the input update data is calculated, and the difference value is added to the previous product-sum operation value to calculate the updated product-sum operation value.

  First, when data is input as the input signal input, the selector SEL1 uses the delay unit DEL2 and the subtractor SUB1 to store the previous data stored in advance in the register corresponding to the set number s10 to be updated before writing the input update data. In addition, the selector SEL2 outputs to the delay device DEL3 and the subtractor SUB2. At the same time, the register corresponding to the input update data responds to the write signals write_0_0 to write_1_7, and the input update data is written into the register.

  Subsequently, the subtractor SUB1 outputs a subtraction value obtained by subtracting the previous data output from the selector SEL1 from the input update data input to the selector SEL3. The delay unit DEL2 delays the previous data output from the selector SEL1 in accordance with the output of the subtractor SUB1, and outputs the delayed data to the selector SEL3. Further, the delay unit DEL1 delays the logical sum s0 of write_0_0 to write_0_7 in accordance with the output of the subtractor SUB1, and outputs it to the selector SEL3 as the select signal select3. The selector SEL3 outputs the previous data of the set of input update data output from the delay unit DEL2 when the select signal select3 is at the H level, and outputs the output from the subtractor DEL2 when the select signal select3 is at the L level. Output to the multiplier MUL1. The same applies to the selector SEL4.

As described above, since the data of either the value “a” or the value “b” is input, for example, when the data of the value “a” is updated, the logical sum s0 of write_0_0 to write_0_7 is H level and from write_1_0 The logical sum s1 of write_1_7 is at the L level. In this case, the multiplier MUL1 outputs the subtraction value (a _j ′ −a _j ) from the subtractor SUB1 by the selector SEL3 related to the value “a” and the delay DEL3 from the selector SEL4 related to the value “b”. Multiply the previous data (b _j ). On the other hand, when the data of the value “b” is updated, the logical sum s0 of write_0_0 to write_0_7 is L level, the logical sum s1 of write_1_0 to write_1_7 is H level, and the multiplier MUL1 is the selector for the value “a”. Multiply the previous data (a _j ) from the delay unit DEL2 by the SEL3 and the subtraction value (b _j ′ −b _j ) from the subtractor SUB2 by the selector SEL4 related to the value “b”.

Then, the multiplier MUL1 outputs the multiplication result to the adder ADD1 as a difference value from the previous product-sum operation value. This difference value corresponds to “(a _j ′ −a _j ) × b _j ” (when the data of the value “a” is updated) in the above-described Expression 2. Subsequently, the adder ADD1 adds the difference value and the previous product-sum operation value held in the output register OUT, and outputs the result to the output register OUT. However, when input update data is input in successive clock cycles, if the previous product-sum operation value is input from the output register, it will not be in time for the next adder ADD1. Therefore, when update data is input in successive clock cycles, the selector SEL5 inputs the output from the adder ADD1 directly to the adder ADD1 instead of the output register OUT.

  The continuous input detection circuit EC1 surrounded by a dotted line is a circuit that determines whether or not input update data is generated in successive clock cycles. When the delay DEL6 and the AND circuit AND1 detect that the logic s0 from write_0_0 to write_0_7 or the logical sum s1 from write_1_0 to write_1_7 is detected by the delay unit DEL6 and the AND circuit AND1, the continuous input detection circuit EC1 selects the select signal select5 at H level. Is output. That is, when input update data is generated in successive clock cycles, an H level select signal select5 is output to the selector SEL5, and otherwise, an L level select signal select5 is output to the selector SEL5. The selector SEL5 inputs the previous output from the adder ADD1 to the adder ADD1 when the select signal select5 is at the H level and the output from the output register OUT when the select signal select5 is at the L level.

  Then, the delay unit DEL5 delays the H level signal of the OR circuit LD1 indicating that data has been input to the timing at which the product-sum operation value is calculated, and outputs the write signal write to the output register OUT. In the product-sum calculator of FIG. 6, it is assumed that the input registers (registers R00 to R17) and the output register OUT are initialized to “0” in the initial state. After these registers are once initialized, it is not necessary to perform initialization again while the product-sum operation value of each data held in the input register is held in the output register.

As described above, the product-sum operation unit of FIG. 6 has a difference value ((()) from the previous product-sum operation value based on the updated arbitrary element data (input update data) with respect to the previous product-sum operation value. The updated product-sum operation value is calculated by adding a _j ′ −a _j ) × b _j ). For this reason, the product-sum operation unit of FIG. 6 does not need to perform the product-sum operation again on the element data of all values to be calculated, and does not wait for all the input update data to be stored in the corresponding registers. The calculation can be started. Thereby, the product-sum operation unit shown in FIG. 6 can calculate the product-sum operation value with fewer processing cycles than the product-sum operation unit shown in FIG.

  By the way, the product-sum operation unit in FIG. 6 has an input register and an output register in the same manner as the product-sum operation unit in FIG. However, the product-sum operation unit of FIG. 2 can perform the operation even when there is no input register and output register, whereas the product-sum operation unit of the present embodiment performs the operation when there is no input register and output register. Can not. This is because, in the product-sum calculator of FIG. 2, the input update data may be output to the selectors SELA and SELB without passing through the input register, and the output of the adder ADD is output without passing through the output register OUT. May be. On the other hand, since the product-sum operation unit of the present embodiment uses the previous data and the previous product-sum operation value for the operation, the input register and the output register that hold the data in advance are indispensable.

  FIG. 7 is a diagram showing a circuit for connecting the product-sum calculator of FIG. 6 to the bus. In the figure, the same reference numbers are assigned to the same parts as those of the bus connection circuit of FIG. The bus connection circuit of the product-sum operation unit in the present embodiment further generates three signals (write signals write_0_0 to write_0_7s0, logical sum s1 of write_1_0 to write_1_7, and the number s10 of the set to be updated) in FIG. Output to the arithmetic circuit.

  In the bus connection circuit of FIG. 7, the OR circuit L10 generates a logical sum s0 from write_0_0 to write_0_7 based on the logical sum of the write signals write_0_0 to write_0_7. Specifically, when any one of the write signals write_0_0 to write_0_7 is at H level, the logical sum s0 from write_0_0 to write_0_7 becomes H level. Similarly, the logical adder L20 generates a logical sum s1 from write_1_0 to write_1_7 based on the logical sum of the write signals write_1_0 to write_1_7. In addition, the logical adders L00 to L07 output the logical sum of a set of signals corresponding to each logical sumr (for example, write_0_0 and write_1_0 in the case of the logical sumr L00) to the encoder E1. The encoder E1 digitizes the logical adder that outputs the H level signal as the number s10 of the set to be updated, and outputs it to the product-sum calculator of FIG.

FIG. 8 is a diagram illustrating operation waveforms in the product-sum calculator of FIG. 6 when “a ₀ ′ to a ₇ ′” is updated as input update data. Here, a product-sum operation is performed on the input update data “a ₀ ′ to a ₇ ′” and “b _{0 to} b ₇ ” which is the previous data. In the example of the figure, the previous data “a _{0 to} a ₇ ” is stored in the registers R 00 to R 07, the previous data “b _{0 to} b ₇ ” is stored in the registers R 10 to R 17, and the previous product-sum operation value is stored in the output register. “S ₇ ⁸ ” is held in advance. “D _i ” is a subtraction value “d _i (= a _i ′ −a _i )” of the previous data “a _i ” corresponding to the input update data from the input update data “a _i ′”, and “q _i ”is a multiplication value“ q _i (= d _i (= a _i ′ −a _i ) × b _i ) of element data of the set value “b _i ” corresponding to the input update data and the subtraction value “d _i ”. Is. “S ₇ ^8-i ” represents a product-sum operation value up to the “i” -th set.

The register R00 holds the previous data “a ₀ ” in advance. Then, when “a ₀ ′” is input as the input signal input, the selector SEL 1 stores the register R 00 in advance based on the number s 10 (= 0) of the set to be updated corresponding to the input update data “a ₀ ”. The previous data “a ₀ ” to be held is output to the delay unit DEL2 and the subtracter SUB1 at the rising timing of the next clock. At the same time, “a ₀ ′” is written to the register R00 in response to the write signal write_0_0.

The subtractor SUB1 subtracts the previous data “a ₀ ” output from the selector SEL1 from the input update data “a ₀ ′”, and selects the subtraction value “d ₀ (= a ₀ ′ −a ₀ )”. Output to SEL3. Since the input update data “a ₀ ′” corresponds to the register R00, the logical sum s0 of write_0_0 to write_0_7 becomes H level, and the delay unit DEL1 outputs the H level select signal select1 to the selector SEL3. Therefore, the selector SEL3 selects the output “d ₀ ” from the subtractor SUB1 based on the H-level select signal select1, and outputs it to the multiplier MUL1.

On the other hand, the selector SEL2 selects the previous data “b ₀ ” held in the register R10 based on the number s10 (= 0) of the set to be updated, and outputs it to the subtractor SUB2 and the delay device DEL3. In this case, since the input update data “a ₀ ′” does not correspond to the registers R10 to R17, the L level select signal select4 is output to the selector SEL4, and the selector SEL4 receives the delay device DEL3 based on the select signal select4. The previous data “b ₀ ” from is selected and output to the multiplier MUL1.

Then, at the next clock rising timing, the multiplier MUL1 multiplies the subtraction value “d ₀ ” output from the selector SEL3 by the previous data “b ₀ ” output from the selector SEL4. The value “q ₀ (= d ₀ (= a ₀ ′ −a ₀ ) × b ₀ )” is output to the adder ADD1. In this example, although a plurality of data a ₀ ′ to a ₇ ′ are input in successive clock cycles, the input update data “a ₀ ′” is the first input. Therefore, the continuous input detection circuit EC1 outputs an L-level select signal select5 to the selector SEL5, and the selector SEL5 outputs the previous product-sum operation value “S ₇ ⁸ ” output from the output register OUT to the adder ADD1. input.

At the next clock rise timing, the adder ADD1 adds the difference value “q ₀ ” from the previous product-sum operation result input from the multiplier MUL1 and the previous product-sum operation value “S ₇ ⁸ ”. The added value “S ₇ ⁷ (= S ₇ ⁸ + q ₀ )” is output to the output register OUT. As a result, the product-sum operation value “S ₇ ⁷ ” reflecting the input update data “a ₀ ′” is written to the output register OUT.

The same applies to the input update data “a ₁ ′ to a ₇ ′” input subsequent to “a ₀ ′”. However, since the calculation of “a ₁ ′ to a ₇ ′” corresponds to the case where the input update data is generated in continuous clock cycles, the adder ADD1 uses the input update data “a _i ′ (i = 1 to 7). The difference value “q _i ” based on “)” and the previous product-sum operation value “S ₇ ^8-i ” output from the adder ADD 1 are added and output to the output register OUT. The delay device DEL5 outputs a write signal “write” to the output register OUT each time a product-sum operation value reflecting each input update data is output to the output register OUT.

As described above, the product-sum operation unit according to the present embodiment, even when a plurality of pieces of data are continuously input, the difference value based on the respective input update data by the pipeline processing of the input and the operation is previously calculated. The product-sum operation values after updating corresponding to the input update data are calculated each time. For this reason, the product-sum operation value of the present embodiment can start the operation without waiting for a plurality of input update data “a ₀ ′ to a ₇ ′” to be stored in the register. Data transfer time is not required until update data is stored in the register. As a result, the product-sum operation unit of FIG. 2 takes 20 cycles after the data “a ₀ ′ to a ₇ ′” starts to be input for the operation of the product-sum operation value. The calculator can calculate the product-sum operation value in 12 cycles.

FIG. 9 is a diagram illustrating operation waveforms in the product-sum operation unit in FIG. 6 when only “a ₂ ′” is updated as input update data. As in FIG. 8, the previous data “a _{0 to} a ₇ ” is stored in the registers R 00 to R 07, the previous data “b _{0 to} b ₇ ” is stored in the registers R 10 to R 17, and the previous product-sum operation is performed in the output register. The value “S ₇ ” is held in advance. “D _i ” and “q _i ” are the same as those in FIG. 8, “S ₇ ” represents the previous product-sum operation value, and “S ₇ ′” represents the updated product-sum operation value.

When “a ₂ ′” is input as the input signal input, the selector SEL 1 holds in advance the register R 02 based on the number s 10 (= 2) of the set to be updated corresponding to the input update data “a ₂ ′”. The previous data “a ₂ ” to be output is output to the delay unit DEL2 and the subtracter SUB1 at the rising timing of the next clock. At the same time, “a ₂ ′” is written to the register R02 in response to the write signal write_0_2.

The subtractor SUB1 subtracts the previous data “a ₂ ” output from the selector SEL1 from the input update data “a ₂ ′”, and selects the subtraction value “d ₂ (= a ₂ ′ −a ₂ )”. Output to SEL3. Then, the selector SEL3 selects the output “d ₂ ” from the subtractor SUB1 based on the H level select signal select3 from the delay device DEL1, and outputs it to the multiplier MUL1. On the other hand, the selector SEL4 selects the previous data “b ₂ ” from the delay device DEL3 based on the L level select signal select4 from the delay device DEL4, and outputs it to the multiplier MUL1.

At the next clock rising timing, the multiplier MUL1 multiplies the subtraction value “d ₂ ” output from the selector SEL3 by the previous data “b ₂ ” output from the selector SEL4, and the multiplied value. “Q ₂ (= (d ₂ (= a ₂ ′ −a ₂ ) × b ₂ )” is output to the adder ADD 1. This example corresponds to a case where no input update data is generated in successive clock cycles. The selector SEL5 inputs the previous product-sum operation value “S ₇ ” output from the output register OUT to the adder ADD1, and the adder ADD1 performs the previous product-sum operation at the rising timing of the next clock. The value “S ₇ ” and the output “q ₂ ” from the multiplier MUL 1 are added, and the added value “S ₇ ′ (= S ₇ + q ₂ )” is output to the output register OUT.

As described above, the product-sum operation unit of the present embodiment does not need to perform the product-sum operation again on the element data of all values to be calculated, and the input update data “a ₂ ′” is stored in the register R02. Since the calculation can be started without waiting for the calculation, the product-sum calculation value can be calculated with fewer processing cycles, particularly when only a part of the element “a ₂ ′” is updated. As a result, the product-sum operation unit in FIG. 2 takes 13 cycles after the data “a ₂ ′” starts to be input for the calculation of the product-sum operation value. The product-sum operation value can be calculated in 5 cycles.

  Therefore, the product-sum calculator of the present embodiment does not require the data transfer time until all the element data to be calculated are stored in the register and the calculation time of all the element data. The product-sum operation value can be calculated with fewer processing cycles than the product-sum operation unit.

<Second Embodiment>
In the first embodiment, the product-sum operation unit that calculates the product-sum operation value of the two values “a” and “b” has been described. However, in the second embodiment, the value “c” is further provided. A product-sum operation unit that calculates the product-sum operation value of the values “a”, “b”, and “c” added with the above will be described. The product-sum operation unit according to the second embodiment calculates a product-sum operation value based on the following Equation 3.

The value “a”, the value “a ′”, and the value “b” in Equation 3 are the same as those in Equation 2. However, in Equation 3, “S” is the product-sum operation value of “a”, “b”, and “c” (hereinafter, the previous product-sum operation value), and “S ′” is “a ′” and “ The product-sum operation value of “b” and “c” (hereinafter, the product-sum operation value after update) is represented. In Equation 3, the updated product-sum operation value “S ′” is obtained by adding the difference value “(a _j ′ −a _j ) × b _j × c _j ” to the previous product-sum operation value “S”. To be calculated.

FIG. 10 is a diagram illustrating an example of a product-sum calculator in the present embodiment when “n = 8” in Equation 3. 6, in the product-sum calculator of FIG. 6, each element a _{0 to} a ₇ of the value “a” is stored in the registers R 00 to R 07, and each element b _{0 to} b ₇ of the value “b” is stored in the registers R 10 to R 10. In R17, each element c _{0 to} c ₇ of the value “c” is stored in the registers R20 to R27. In addition, the product-sum calculator in the present embodiment holds the previous data in the input register (registers R00 to R27) and the previous product-sum operation value in the output register OUT.

  In the product-sum calculator of FIG. 10, the same reference numbers are assigned to the same parts as those of FIG. The product-sum operation unit shown in the figure further includes registers R20 to R27, logical sum s2 of write_2_0 to write_2_7, selectors SEL6 and SEL7, subtractor SUB3, delay units DEL7 and DEL8. The logical sum s2 from write_2_0 to write_2_7 represents the presence or absence of input update data stored in any of the registers R20 to R27. In addition, in the product-sum operation unit of the same figure, update data of values “a”, “b”, and “c” is input as the input signal input.

The operation of the product-sum calculator of FIG. 10 is the same as that of FIG. In the same 10 product-sum operation unit, any one of the values “a”, “b”, and “c” is input. For example, when data of the value “a ′” is input, the logic of write_0_0 to write_0_7 The sum s0 is at the H level, the logical sum s1 from write_1_0 to write_1_7, and the logical sum s2 from write_2_0 to write_2_7 is at the L level. Accordingly, the multiplier MUL1 includes the subtraction value (a _j ′ −a _j ) from the subtractor SUB1 by the selector SEL3 related to the value “a” and the previous time from the delay DEL3 by the selector SEL4 related to the value “b”. The data (b _j ) is multiplied by the previous data (c _j ) from the delay device DEL 7 by the selector SEL 7 related to the value “c”.

Then, the multiplier MUL1 outputs the multiplication result to the adder ADD1 as a difference value from the previous product-sum operation value. This difference value corresponds to “(a _j ′ −a _j ) × b _j × c _j ” in Expression 3 described above. The adder ADD1 adds the difference value and either the output register OUT or the previous output from the adder ADD1, and outputs the result as an updated product-sum operation value to the output register OUT.

  As described above, the product-sum operation unit of the present embodiment also uses the product-sum operation of FIG. 6 for the product-sum operation value of three values obtained by adding the value “c” to the values “a” and “b”. In the same way as the unit, the difference between the previous product-sum operation value based on the updated arbitrary element data (input update data) is added to the previous product-sum operation value by pipeline processing of input and operation By doing so, an updated product-sum operation value is calculated. For this reason, the product-sum operation unit does not need to perform the product-sum operation again on the element data of all the values “a”, “b”, and “c” to be calculated, and stores all the input update data in the corresponding registers. The computation can be started without waiting for it.

  Thereby, the product-sum operation unit of the present embodiment also calculates the data transfer time until all the element data to be calculated are stored in the register, even when calculating the product-sum operation value of the three values, and By not requiring calculation time for all the element data, the product-sum operation value can be calculated with fewer processing cycles. In the present embodiment, the case where the product-sum operation of three values is performed has been described. However, the product-sum operation unit of the present embodiment is also effective when performing the product-sum operation of four or more values. It is.

<Third Embodiment>
In the first embodiment, the product-sum operation unit to which any element data of the values “a” and “b” is input has been described. In the third embodiment, the values “a” and “b” are described. The sum-of-products calculator to which the same set of element data is simultaneously input will be described.

The product-sum operation unit of the third embodiment calculates a product-sum operation value based on the following equation 4. In Expression 4, the values “a” and “a ′” are the same as those in Expression 2, and the values “b ′ = (b ₀ ′, b ₁ ′, b ₂ ′,..., A _n−1 ′)” are the previous time. It is assumed that the j-th element is updated with respect to the previous data which is the old value “b = (b ₀ , b ₁ , b ₂ ,..., B _n−1 )” obtained by the product-sum operation. “S” is the product-sum operation value of “a” and “b” (hereinafter, the previous product-sum operation value), and “S ′” is the product-sum operation value of “a ′” and “b ′”. (Hereinafter referred to as an updated product-sum operation value).

In Equation 4, as in Equation 2, the updated product-sum operation value “S ′” is added to the previous product-sum operation value “S” by adding the difference value between “S ′” and “S”. Ask. Specifically, the updated product-sum operation value “S ′” is obtained by multiplying the multiplication value “a _j × b _j ” of the j-th element of the values “a” and “b” from the previous product-sum operation value “S”. A value obtained by subtracting and adding the multiplication value “a _j ′ × b _j ′” of the j-th element of the values “a ′” and “b ′” (S ′ = S− (a _j × b _j ) + (a _j '× b _j ')). Accordingly, the updated product-sum operation value “S ′” is obtained by adding the difference value “− (a _j × b _j ) + (a _j ′ × b _j ′)” to the previous product-sum operation value “S”. Is calculated.

  Comparing Expression 1 and Expression 4, when some elements of the value are updated, the amount of calculation of Expression 4 is smaller than Expression 1. Therefore, Equation 4 can calculate the updated product-sum operation value “S” with fewer processing cycles than Equation 1.

FIG. 11 is a diagram illustrating an example of a product-sum calculator in the present embodiment when “n = 8” in Equation 4. Similar to the product-sum operation unit in FIG. 6, in the product-sum operation unit in FIG. 6, the elements a _{0 to} a ₇ of the value “a” are stored in the registers R 00 to R 07 and the elements b ₀ of the value “b” ~b ₇ is stored in the register R10-R17. In the product-sum operation unit shown in the figure, the previous data is stored in each input register, and the previous product-sum operation value is held in the output register OUT. Furthermore, since the updated data of the same set of values “a” and “b” are simultaneously input to the product-sum calculator of FIG. 23, the input signal input_0 corresponding to the value “a” and the value “b” And an input signal inout_1 corresponding to.

  In the product-sum calculator of FIG. 11, when input update data related to the value “a” is input as the input signal input_0, the selector SEL1 corresponds to the number s10 of the set to be updated before writing the input update data. The previous data held in the register in advance is output to the selector SEL8 and the multiplier MUL3. At the same time, the registers corresponding to the input update data are written in the corresponding registers R00 to R07 in response to the write signals write_0_0 to write_0_7.

  Similarly, when the data of the same set as the input signal input_0 and the data related to the value “b” is input as the input signal input_1, the selector SEL2 updates the number of the set to be updated before writing the input update data. The previous data held in advance in the register corresponding to s10 is output to the selector SEL9 and the multiplier MUL3. At the same time, the registers corresponding to the input update data are written to the corresponding registers R10 to R17 in response to the write signals write_1_0 to write_1_7.

  Subsequently, the selector SEL8 selects either the input update data input_0 or the previous data corresponding to the input update data output from the selector SEL1 based on the select signal select8 (logical sum s0 of write_0_0 to write_0_7). Output to the multiplier MUL2. Specifically, the selector SEL8 outputs the input update data input_0 to the multiplier MUL2 when the select signal select8 is at the H level and the previous data output from the selector SEL1 when the select signal select8 is at the L level. The same applies to the selector SEL9.

As described above, the product-sum operation unit of the present embodiment inputs the same set of data of the values “a” and “b” at the same time, so the logical sum s0 from write_0_0 to write_0_7 and the logical sum of write_1_0 to write_1_7. s1 becomes H level at the same time. In this case, the multiplier MUL2 multiplies the input update data input_0 and input_1 by multiplication (a _j ′ × b _j ′), and the multiplier MUL3 multiplies the previous data corresponding to both input update data by the multiplication value ( a _j × b _j ) are output to the subtracter SUB4.

Then, subtractor SUB4 is the multiplier MUL2 multiplies values of the two input update data is outputted from the _{(a j '× b j'} ), multiplied values of the previous data is output from the multiplier MUL3 _{(a j} × b _j ) is subtracted and output to the adder ADD1 as a difference value from the previous product-sum operation result. This difference value corresponds to “− (a _j × b _j ) + (a _j ′ × b _j ′)” in Expression 4 described above. The adder ADD1 adds the difference value and either the output register OUT or the previous output from the adder ADD1, and outputs the result as an updated product-sum operation value to the output register OUT.

  As described above, the product-sum operation unit according to the present embodiment has an input and a product-sum operation value in the case of simultaneously updating any of the same set of element data (input update data) of the values “a” and “b”. By adding the difference value from the previous product-sum operation value based on the input update data to the previous product-sum operation value by the operation pipeline processing, the updated product-sum operation value can be sequentially calculated. For this reason, the product-sum operation unit does not need to perform the product-sum operation again on all the sets of element data to be calculated, and does not wait for all the input update data to be stored in the corresponding register. can do.

  As a result, the product-sum operation unit according to the present embodiment, when updating any element data of the same set of values “a” and “b” at the same time, until all the element data to be calculated are stored in the register. Therefore, the product-sum operation value can be calculated with fewer processing cycles.

<Fourth embodiment>
In the first embodiment, the product-sum operation unit having one set of input registers and output registers has been described. However, in the fourth embodiment, a plurality of input registers and output registers (hereinafter referred to as register sets) are used. A product-sum operation unit that holds In the fourth embodiment, for example, m sets of input registers (registers R00_i to R17_i (0 ≦ i ≦ m−1)) and output registers (OUT_i) are included. Then, a product-sum operation of the values “a” and “b” of each register set is performed by an arithmetic unit shared by each register set.

  FIG. 12 is a diagram illustrating an example of a product-sum calculator in the fourth embodiment. The product-sum calculator of FIG. 6 further has a register set number s20 to be updated. The register set number s20 to be updated is an identification number of the register set subject to the product-sum operation. Further, in the product-sum operation unit in the figure, as the input signal input, the updated data of any of the register set values “a” and “b” designated by the register set number s20 to be updated is input.

  In the product-sum operation value of FIG. 12, when data is input as the input signal input, the register set subject to product-sum operation is selected based on the register set number s20 to be updated. The previous data held in the registers R00_i to R17_i of the register set designated by the register set number s20 to be updated is output to the delay units DEL2, DEL3 and the subtracters SUB1, SUB2 via the selectors SEL1, SEL2. At the same time, the input update data is written to the register. Thereafter, the processing up to the calculation of the difference value of the multiplier MUL1 is the same as that of the product-sum operation unit of FIG.

  Subsequently, the adder ADD1 adds the difference value output from the multiplier MUL1 and the previous product-sum operation value based on the select signal select11 output from the continuous input detection circuit EC2. The continuous input detection circuit EC2 determines whether or not the register set number c20 to be updated is the same as the previous clock cycle, in addition to whether or not data is input in successive clock cycles. The continuous input detection circuit EC2 outputs an H level select signal select11 to the selector SEL11 when the two conditions are true, and outputs an L level to the selector SEL11 when either or both of the two conditions are not true. The select signal select11 is output.

  The selector SEL11 inputs the output from the adder ADD1 to the adder ADD1 again when the H level select signal select11 is output, and from the delay unit DEL9 when the L level select signal select11 is output. The previous product-sum operation value held in the output register OUT_i based on the input register set number s20 to be updated is input to the adder ADD1. In other words, the adder ADD1 outputs the previous output of the adder ADD1 when input update data is generated in successive clock cycles and the register set number is the same as the previous clock cycle, otherwise Takes the output of the output register OUT_i corresponding to the register set number as the previous product-sum operation value.

  Then, the delay unit DEL10 delays the register set number s20 to be updated at the timing when the product-sum operation value corresponding to the input update data is calculated, and selects and writes the output register OUT_i based on the register set number s20 to be updated. Output signal write.

  As described above, the product-sum operation unit according to the present embodiment has a plurality of register sets, and calculates the product-sum operation value of the register set corresponding to the updated arbitrary element data (input update data). In addition, by adding the difference value from the previous product-sum operation value based on the input update data to the previous product-sum operation value by the pipeline processing of input and operation, the updated register set is updated. A product-sum operation value can be calculated. For this reason, the product-sum operation unit does not need to perform the product-sum operation again on the element data of all values to be calculated, and also starts the operation without waiting for all the input update data to be stored in the corresponding register. can do.

  As a result, the product-sum calculator of the present embodiment does not require the data transfer time until all the element data to be calculated are stored in the register, and the calculation time of all the element data. The product-sum operation value of the values “a” and “b” of each register set can be calculated at a high speed with fewer processing cycles.

<Fifth Embodiment>
FIG. 13 and FIG. 14 are diagrams illustrating an example of a product-sum calculator in the fifth embodiment. This embodiment has the arithmetic circuit in FIG. 13 and m arithmetic circuits in FIG. The arithmetic circuit in FIG. 13 outputs the input signals data_0 and data_i to the arithmetic circuits in FIG. The input signal data_0 is the previous data of the first register set (registers R00 to R07) corresponding to the input update data, and the input signal data_i is the second register set (registers R10_i to R17_i (1 ≦ 1) corresponding to the input update data. i ≦ m)).

  In the fifth embodiment, a product-sum operation unit having one set of first register sets (registers R00 to R07), m sets of second register sets (registers R10_i to R17_i), and an output register OUT_i. State. In the fifth embodiment, for example, m product sums obtained by multiplying and summing the values of m second register sets and the values of the first register set shared by the second register sets, respectively. The calculated value is output to the output register OUT_i. The product-sum operation unit in the present embodiment is effective, for example, when obtaining a product of a matrix and a vector. In this case, the first register set corresponds to a vector, and the m second register sets correspond to an “m × 8” matrix.

Equation 5 represents the second register set as an “m × 8” matrix (b ₁ , ₀ , b ₁ , ₁ ,..., B _{m, 7} ), and the first register set as a vector (a ₀ , a ₁ , .., A ₇ ) is an expression representing the operation of the product of a matrix and a vector. In the calculation of Equation 5, each matrix row and vector calculation “(b _{i, 0} × a ₀ ) + (b _{i, 1} × a ₁ ) +... + (B _{i, 7} × a ₇ )” is performed, Calculated as “output_i”.

  FIG. 13 is an arithmetic circuit that outputs the previous data data_0 and data_i of each register set corresponding to the input update data. In the arithmetic circuit shown in the figure, the value of either the first register set (registers R00 to R07) or the second register set (registers R10_i to R17_i) is input. In the arithmetic circuit shown in the figure, when data is input as the input signal input, before the input update data is written, the selectors SELm0 to mm hold in advance the registers corresponding to the number s10 of the set to be updated in each register set. The previous data data_0 and data_i are output. At the same time, the register corresponding to the input update data responds to the write signals write_0_0 to write_m_7, and the input update data is written into the register.

  FIG. 14 is an arithmetic circuit that calculates the product-sum operation value of the first register set and one of the m second register sets. For example, in the case of an operation for obtaining a product of a matrix and a vector, the arithmetic circuit shown in FIG. The logical sum s0 from write_0_0 to write_0_7 indicates the presence / absence of input update data stored in any of the registers R00 to R07, and the logical sum si from write_i_0 to write_i_7 is input update data stored in any of the registers R10_i to R17_i. Indicates the presence or absence of

  In the arithmetic circuit of FIG. 14, first, in addition to the input update data input, the previous data data_0 of the first register set corresponding to the input update data input is changed to the previous data data_i of the second register set corresponding to the input update data. Is entered. For example, when data corresponding to the first register set is input, the logical sum s0 of write_0_0 to write_0_7 is H level, and the logical sum si of write_i_0 to write_i_7 is L level. In this case, the selector SEL3 outputs the subtraction value of the previous data data_0 from the input update data input input from the subtractor SUB1 to the multiplier MUL1, and the selector SEL4 converts the input update data input from the delay device DEL3. The previous data data_i of the corresponding second register set is output to the multiplier MUL1.

  The multiplier MUL1 multiplies the inputs from the selectors SEL3 and SEL4 and outputs the result as a difference value to the adder ADD1. Subsequently, the adder ADD1 adds the difference value and either the output from the output register OUT_i or the previous adder ADD1, and outputs the result as an updated product-sum operation value to the output register OUT_i.

  FIG. 15 is a diagram illustrating a circuit that connects the circuits of FIGS. 13 and 14 to a bus. In the figure, the same reference numbers are assigned to the same parts as the bus connection circuit of FIG. The bus connection circuit in the present embodiment further outputs the logical sum si of write_i_0 to write_i_7 of m (1 ≦ i ≦ m) second register sets to the corresponding arithmetic circuit (FIG. 14). In FIG. 15, the circuits from s1 to s (m-1) are omitted and are represented by the sm circuit. In addition, the logical adders L00 to L07 output logical sums of sets of write signals write_0_i, write_1_i,..., Write_m_i corresponding to the respective logical adders to the encoder E2. The encoder E2 digitizes a logical adder that outputs an H level signal as a set number s10 to be updated, and outputs it to the arithmetic circuit of FIG.

  Further, the comparator C30 compares whether the detected address corresponds to the address of the m output registers OUT_i (1 ≦ i ≦ m) in FIG. 14, and outputs a read signal to the gate G3 if they match. The AND circuit AND2 outputs a select signal select20 for selecting the output register OUT_i corresponding to the detected address to the selector SEL20. Specifically, the logical product AND2 is, for example, a logical product value of a predetermined number of digits under the address of each output register OUT_i given consecutive addresses and a value holding “1” in each digit of the predetermined number Is output to the selector SEL20 as the select signal select20. Then, the selector SEL20 outputs the value output_i held by the output register OUT_i corresponding to the detection address from the gate G3 to the data bus DB based on the select signal select20.

  As described above, the sum-of-products calculator in this embodiment has a plurality of sets of second registers and output registers and a shared first register set, and updated arbitrary element data (input update data). This is also effective when calculating a plurality of sets of product-sum operation values corresponding to. The product-sum operation unit according to the present embodiment adds a difference value with the previous product-sum operation value based on the input update data to each of a plurality of sets of previous product-sum operation values by operation and pipeline processing. By doing so, it is possible to calculate the product-sum operation value after updating the plurality of sets. For this reason, the product-sum operation unit does not need to perform the product-sum operation again on the element data of all values to be calculated, and also starts the operation without waiting for all the input update data to be stored in the corresponding register. can do.

  Thereby, the product-sum operation unit according to the present embodiment calculates all the product-sum operation values of the plurality of second register sets and the shared first register set. By not requiring the data transfer time until the element data is stored in the register and the operation time of all the element data, it is possible to calculate the product-sum operation value for each of the plurality of sets with fewer processing cycles. As described above, the product-sum operation unit in the present embodiment can, for example, obtain a product of a matrix and a vector at high speed.

<Sixth embodiment>
In the first embodiment to the fifth embodiment, the product-sum operation unit that calculates the product-sum operation value has been described. However, the arithmetic circuit of the present invention is not limited to the product-sum operation, and is effective for other operations. Therefore, in the sixth embodiment, an arithmetic circuit other than the product-sum operation will be described.

In the present embodiment, for example, the value “a = (a ₀ , a ₁ , a ₂ ,..., A _n−1 )” and the value “b = (b ₀ , b ₁ , b _{2 ,. -1} ) "will be described with respect to a logical sum / exclusive OR operation circuit (hereinafter referred to as an AND / XOR operation circuit) that performs exclusive OR operation on each logical product of each set. The AND / XOR operation circuit generally calculates an AND / XOR operation value based on the following equation (6).

In Expression 6, the function f is a function for obtaining a logical product, and “A” is a value obtained by further exclusive-ORing the logical product of each pair of the value “a” and the value “b”. In the arithmetic circuit based on Expression 6, for example, when only some of the elements of the value “a” are updated, the logical product and exclusive OR are re-performed for all the elements of the values “a” and “b”. It was.

Therefore, the arithmetic circuit according to the present embodiment obtains an AND / XOR arithmetic value based on the following Expression 7. In Equation 7, the value “a ′ = (a ₀ ′, a ₁ ′, a ₂ ′,..., A _n−1 ′)” is the old value “a = (a ₀ , a ₁ , a _2, ..., it is assumed that the j-th element is updated for the previous data is a _n-1) ". “A” is an AND / XOR operation value of the value “a” and the value “b” (hereinafter, the previous AND / XOR operation value), and “A ′” is the value “a ′” and the value “b”. "AND / XOR operation value (hereinafter, updated AND / XOR operation value)".

In Expression 7, the updated AND · XOR operation value “A ′” is obtained by calculating the logical product (f (a _j , b _j )) of the “value“ a ”and“ b ”and the value“ a ′ ”. "Exclusive OR with the logical product (f (a _j ', b _j )) of the _jth element of" b "" and the previous AND / XOR operation value "A". (A ′ = A ^ (f (a _j , b _j )) ^ (f (a _j ′, b _j ))). This arithmetic expression can be summarized as “A ′ = A ^ (f (a _j ^ a _j ′, b _j ))”. Therefore, the updated AND / XOR operation value “A ′” is obtained by exclusive OR of the previous AND / XOR operation value “A” and “f (a _j ^ a _j ′, b _j )”. It is done.

  Comparing Expression 6 and Expression 7, when some elements of the value are updated, the amount of calculation of Expression 7 is smaller than Expression 6. Therefore, Equation 7 can calculate the updated AND · XOR operation value “A ′” with fewer processing cycles than Equation 6.

FIG. 16 is a diagram illustrating an example of a circuit in the present embodiment when “n = 8” in Expression 7. In the arithmetic circuit shown in the figure, the elements a _{0 to} a ₇ having the value “a” are stored in the registers R 00 to R 07, and the elements b _{0 to} b ₇ having the value “b” are stored in the registers R 10 to R 17. Similarly, the arithmetic circuit in the present embodiment holds the previous data in the registers R00 to R17 and the previous AND / XOR operation value in the output register. Also, updated data of either the value “a” or the value “b” is input as the input signal input.

In addition, Expression 7 “A ^ f (a _j ^ a _j ′, b _j )” of the arithmetic circuit in FIG. 16 and Expression 2 “S + (a _j ′ −a _j ) × b of the product-sum operation unit in FIG. _In “ _j ”, the logical product of Expression 7 corresponds to the integration of Expression 2, and the exclusive OR of Expression 7 corresponds to the addition and subtraction of Expression 2. Therefore, the arithmetic circuit in FIG. 16 is different from the product-sum arithmetic circuit in FIG. 6 in that the exclusive ORs XOR1 and XOR2 are substituted for the subtracters SUB1 and SUB2, the logical ANDer AND3 is substituted for the multiplier MUL1, Instead of the adder ADD1, an exclusive OR circuit XOR3 is provided.

In the arithmetic circuit of FIG. 16, for example, when data (a _j ′) of value “a ′” is input as the input signal input, the exclusive OR XOR1 outputs the input update data input and the selector SEL1. The exclusive OR with the previous data (a _j ) corresponding to the inputted update data is calculated and output to the selector SEL3 (a _j ^ a _j '). Then, the selector SEL3 selects the output from the exclusive OR circuit XOR1 based on the H level select signal select3 from the delay device DEL1, and outputs it to the AND circuit AND3. On the other hand, the selector SEL4 selects the previous data (b _j ) corresponding to the input update data, which is an input from the delay device DEL3, based on the L level select signal select4, and outputs the selected data to the AND circuit AND3.

Subsequently, the AND circuit AND3 calculates the logic between the output (a _j ^ a _j ′) from the exclusive OR circuit XOR1 by the selector SEL3 and the previous data (b _j ) from the delay device DEL3 by the selector SEL4. The product is calculated and output to the exclusive OR XOR3. This output corresponds to “f (a _j ^ a _j ′, b _j ” in the above-described expression 7. Then, the exclusive OR XOR3 outputs the output from the AND AND3 and the output register OUT or the previous time. XOR with one of the outputs from the XOR3 is output to the output register OUT as the updated AND / XOR operation value.

  As described above, the arithmetic circuit according to the present embodiment also obtains the AND / XOR operation value of the value “a” and the value “b” by the pipeline processing of the input and the operation, and the previous AND / XOR operation. An updated AND / XOR operation value can be obtained based on the value. Therefore, the arithmetic circuit according to the present embodiment does not need to recalculate element data of all values to be calculated, and does not wait for all input update data to be stored in the corresponding register. Can start. As a result, the arithmetic circuit according to the present embodiment determines the data transfer time until all the element data to be calculated are stored in the register when the AND / XOR calculation value of the value “a” and the value “b” is obtained. And by not requiring the calculation time of all the element data, the AND / XOR calculation value can be calculated with fewer processing cycles.

  Thus, the arithmetic circuit of the present invention is also effective for arithmetic circuits other than product-sum operations. Such an arithmetic circuit is generalized as follows.

  First, the arithmetic circuit has a register for holding a first value (a) and a second value (b) having N elements, and “first operation (integration, And a register for holding the operation result values (S, A) obtained by performing “second operation (addition / subtraction, exclusive OR)”.

Further, the arithmetic circuit determines that “the one element (a _j ′ (= input update data)) of the input first value and the element (a _j ) of the first value corresponding to the element” "First operation unit for performing second operation (addition / subtraction, exclusive OR)", "output of first operation unit, and second value corresponding to input first value element" And a second arithmetic unit that performs “first operation (integration, logical product)” on the element (b _j ). Further, the arithmetic circuit performs “second operation (addition / subtraction, exclusive OR)” on the output of the second arithmetic unit and the operation result value (S, A) of the output register and outputs the result to the output register. And a third computing unit.

Then, the calculation by the second arithmetic unit described above is “the first value element (a _j ) in the first register corresponding to the input first value element and the second value corresponding to the element. A value that cancels the result of the “first operation (integration, logical product)” with respect to the value element (b _j ) based on the second operation (1) ”,“ element of the input first value ( a _j ') and the second value element (b _j ) corresponding to the element (b _j ) result of "first operation (integration, logical product)" (2) "and" second operation (addition / subtraction, Exclusive logical OR) ”(3) satisfies the distribution rule.

  The above generalized configuration will be described below in correspondence with the first embodiment and the sixth embodiment. First, in the product-sum operation unit of the first embodiment, the first operation corresponds to integration, and the second operation corresponds to addition / subtraction. The calculation result value “S” corresponds to a product-sum calculation value obtained by further adding the integrated values of the element data of the values “a” and “b”.

For (1), “the first value element (a _j ) in the first register corresponding to the input first value element” and “the second value element (b) corresponding to the element (b) _j ) ”and the result of the integration is“ a _j × b _j ”. Then, the value of canceling based on the subtraction of _{"a j} × _{b j",} the value becomes "0" by subtracting the _{"a j} × _{b j",} ie, "- _{(a j} × _{b j)"} Indicates. Then, with respect to (2), the result of integration with respect to “input first value element (a _j ′)” and “second value element (b _j ) corresponding to the element” is “a _j ′ × b _j ”, (3) is“ − (a _j × b _j ) + (a _j ′ × b _j ) ”.

The operation of the second arithmetic unit in the first embodiment is “(a _j ′ −a _j ) × b _j ”, and the operation is (3) “− (a _j × b _j ) + (a _j ′ × b _j ) ”is satisfied. Therefore, the arithmetic circuit in the first embodiment corresponds to the above configuration.

  Subsequently, in the product-sum operation unit of the sixth embodiment, the first operation corresponds to a logical product, and the second operation corresponds to an exclusive OR. The operation result value “A” corresponds to an AND / XOR operation value obtained by further exclusive-ORing each logical product of the element data of the value “a” and the value “b”.

For (1), “the first value element (a _j ) in the first register corresponding to the input first value element” and “the second value element (b) corresponding to the element (b) The result of the logical product for “ _j )” is “f (a _j , b _j )”. Then, the value of canceling based on exclusive OR "f (a _{j, b j)"} is a value that is a exclusive OR of the "f (a _{j, b j)"} is "0" . In the exclusive OR operation, the exclusive OR of the same value is “0”. Therefore, the _{"f (a j, b} j)" is a value for canceling based on the exclusive OR equivalence, or _{"f (a j, b} j)". For (2), the result of the logical product of “the input first value element (a _j ′)” and “the second value element (b _j ) corresponding to the element” is “ _{f (a j ', b j} ) for "a is, (3)" _{(f (a j, b j} )) ^ (f (a j' is _{a, b} j)) ".

The operation “f (a _j ^ a _j ′, b _j )” of the second arithmetic unit in the sixth embodiment is the same as (3) “(f (a _j , b _j )) ^ The distribution law is satisfied for (f (a _j ′, b _j )) ”. Therefore, the arithmetic circuit in the sixth embodiment corresponds to the above configuration.

  The product-sum operation unit of the first embodiment and the operation circuit of the sixth embodiment are generalized as described above. Therefore, the arithmetic circuit of the present invention is also effective for other arithmetic circuits corresponding to the generalized configuration described above, and the arithmetic circuit similarly has fewer arithmetic results for input data in which an arbitrary value is updated. It can be obtained at high speed in the processing cycle.

  The above embodiment is summarized as follows.

(Appendix 1)
A first register holding a first value having N elements;
A second register holding a second value having N elements;
An output register for holding a product-sum operation value obtained by performing a product-sum operation on the first value and the second value;
A first subtractor for subtracting the element of the first value in the first register corresponding to the element from one of the elements of the input first value;
A multiplier that multiplies the output of the first subtractor with the element of the second value in the second register corresponding to the element of the input first value;
An adder that adds the output of the multiplier and the product-sum operation value of the output register to output to the output register;
An arithmetic circuit comprising:

(Appendix 2)
In Appendix 1,
A first selector for selecting the first value element in the first register corresponding to the inputted first value element and outputting the selected first value element to the first subtractor; Arithmetic circuit to perform.

(Appendix 3)
In Appendix 1 or 2,
A second subtracter for subtracting the element of the second value in the second register corresponding to the element from one of the elements of the input second value;
The multiplier multiplies the output of the second subtracter by the element of the first value in the first register corresponding to the input second element. Arithmetic circuit.

(Appendix 4)
In Appendix 3,
When the element of the first value is input, the output of the first subtracter is selected and output to the multiplier, and when the element of the second value is input, it corresponds to the element An arithmetic circuit, wherein the element of the first value in the first register is selected and output to the multiplier.

(Appendix 5)
In Appendix 1 or 2,
A third register holding a third value having N elements;
The output register holds a product-sum operation value obtained by performing a product-sum operation on the third value in addition to the first value and the second value,
In addition to the element of the second value in the second register corresponding to the element of the input first value and the output of the first subtractor, the multiplier An arithmetic circuit that multiplies the element of the third value in a register.

(Appendix 6)
In Appendix 1 or 2,
The first register holds a plurality of sets of the first value;
The second register holds a plurality of sets of the second values;
The output register holds the product-sum operation value of each of the first and second values of the plurality of sets;
The first subtracter receives a first element in the first register of the first set corresponding to the element from one element of the first value of the first set among the plurality of sets input. Subtract elements of the value of
The multiplier multiplies the output of the first subtracter with a second value element in the second register of the first set corresponding to a first value element of the first set. And
The adder adds the output of the multiplier and the product-sum operation value of the output register of the first set.

(Appendix 7)
In Appendix 1 or 2,
The second register holds a plurality of sets of the second values;
The output register holds the product-sum operation value of a first value and each of the plurality of sets of second values;
For each of the plurality of sets, the multiplier is configured to output a second subtractor in each second register of the plurality of sets corresponding to the output of the first subtractor and the element of the input first value. Multiply by the value element,
The adder adds, for each of the plurality of sets, the output of the multiplier and the product-sum operation value of the output register of each of the plurality of sets, and outputs the result to the output register.

(Appendix 8)
A first register holding a first value having N elements;
A second register holding a second value having N elements;
An output register for holding a product-sum operation value obtained by performing a product-sum operation on the first value and the second value;
A first multiplier for multiplying one of the elements of the inputted first value by one of the elements of the inputted second value corresponding to the element;
The element of the first value in the first register corresponding to the element of the input first value and the element of the second register corresponding to the element of the input second value A second multiplier for multiplying the element of the second value;
A subtractor for subtracting the output of the second multiplier from the output of the first multiplier;
An adder that adds the output of the subtracter and the product-sum operation value of the output register to output to the output register;
An arithmetic circuit comprising:

(Appendix 9)
A first register holding a first value having N elements;
A second register holding a second value having N elements;
An output register that holds N first calculation values that have been first calculated with respect to the first value and the second value, and further holds a calculation result value that has been second calculated;
A first arithmetic unit that performs the second operation on one element of the input first value and the element of the first value in the first register corresponding to the element When,
A second that performs the first operation on the output of the first calculator and the element of the second value in the second register corresponding to the element of the input first value; With the calculator of
A third computing unit that performs the second computation on the output of the second computing unit and the computation result value of the output register and outputs the second computation to the output register;
Have
The calculation by the second calculator is performed by calculating an element of the first value in the first register corresponding to the element of the input first value and an element of the second register corresponding to the element. A value for canceling the result of the first operation on the element of the second value based on the second operation; an element of the input first value; and a value in the second register corresponding to the element An arithmetic circuit characterized by satisfying a distribution law for the second operation on the result of the first operation on an element of a second value.

(Appendix 10)
In Appendix 9,
The arithmetic circuit is characterized in that the first operation is a logical product and the second operation is an exclusive OR.

(Appendix 11)
In Appendix 9,
The arithmetic circuit, wherein the first operation is a product and the second operation is addition / subtraction.

11: CPU, 12: DMAC, 13: Memory, 14: Product-sum calculator, 15: Other hardware

Claims (7)

A first register holding a first value having N (N ≧ 2) elements;
A second register holding a second value having N elements;
An output register for holding a product-sum operation value obtained by performing a product-sum operation on the first value and the second value;
In the first phase, the N elements of the first and second values are sequentially selected and output so that the elements are paired, and in the second phase subsequent to the first phase Selecting and outputting an element of a first value in the first register corresponding to an input element indicating one of the elements of the input first value, and the first corresponding to the input element A first selector for selecting and outputting an element of the second value in the two registers;
A first subtracter for subtracting an element of the first value corresponding to the input element output by the first selector from the input element;
A multiplier,
An adder that adds the output of the multiplier and the product-sum operation value of the output register and outputs the sum to the output register;
In the first phase, the multiplier outputs the second value that is paired with N elements of the first value and elements of the first value, which are sequentially output by the first selector. Are sequentially multiplied and output to the adder, and the adder adds the output of the multiplier and the output of the output register N times to obtain the first value and the second value. The product-sum operation value with the value of is output to the output register,
In the second phase, the multiplier multiplies the output of the first subtracter by the element of the second value corresponding to the input element output by the first selector, and Output to the adder, the adder adds the output of the multiplier and the output of the output register once, and the product of the first value and the second value in which the input element is updated An arithmetic circuit which outputs a sum operation value to the output register. In claim 1,
The first selector selects, in the second phase, a second value element in the second register corresponding to an input element indicating one of the elements of the input second value. And selecting and outputting the element of the first value in the first register corresponding to the input element,
A second subtracter for subtracting an element of the second value corresponding to the input element output by the first selector from an input element indicating one of the elements of the input second value; And further,
In the second phase, the multiplier multiplies the output of the second subtracter by the element of the first value corresponding to the input element output by the first selector, and Output to the adder, the adder adds the output of the multiplier and the output of the output register once, and the product of the first value and the second value in which the input element is updated An arithmetic circuit which outputs a sum operation value to the output register. A first register holding a first value having N (N ≧ 2) elements;
A second register holding a second value having N elements;
An output register for holding a product-sum operation value obtained by performing a product-sum operation on the first value and the second value;
Selecting and outputting an element of the first value in the first register corresponding to a first input element indicating one of the elements of the input first value, and the first input element; And selecting and outputting a second value element in the second register corresponding to a second input element indicating one of the elements of the input second value. And
A first multiplier for multiplying the first input element and the second input element;
The first value element corresponding to the first input element output by the first selector and the second value corresponding to the second input element output by the first selector. A second multiplier for multiplying the elements of
A subtractor for subtracting the output of the second multiplier from the output of the first multiplier;
An adder that adds the output of the subtracter and the product-sum operation value of the output register once and outputs the product-sum operation value of the first value and the second value to the output register When,
An arithmetic circuit comprising: A first register holding a first value having N (N ≧ 2) elements;
A second register holding a second value having N elements;
An output register that holds N first calculation values that have been first calculated with respect to the first value and the second value, and further holds a calculation result value that has been second calculated;
In the first phase, the N elements of the first and second values are sequentially selected and output so that the elements are paired, and in the second phase subsequent to the first phase Selecting and outputting an element of a first value in the first register corresponding to an input element indicating one of the elements of the input first value, and the first corresponding to the input element A first selector for selecting and outputting an element of the second value in the two registers;
A first computing unit that performs the second computation on the input element and the element of the first value corresponding to the input element output by the first selector;
A second computing unit;
A third computing unit that performs the second computation on the output of the second computing unit and the computation result value of the output register and outputs the second computation to the output register;
Have
The calculation by the second calculator is performed by calculating an element of the first value in the first register corresponding to the element of the input first value and an element of the second register corresponding to the element. A value for canceling the result of the first operation on the element of the second value based on the second operation; an element of the input first value; and a value in the second register corresponding to the element Satisfy the distribution law for the second operation on the result of the first operation on the second value element;
In the first phase, the second computing unit makes a pair of the N elements of the first value and the elements of the first value, which are sequentially output by the first selector. A first operation is sequentially performed on N elements having a value of 2, and the result is output to the third arithmetic unit. The third arithmetic unit outputs the output of the second arithmetic unit and the output register. Performing the second operation on the output N times, and outputting the operation result value of the first value and the second value to the output register,
In the second phase, the second computing unit outputs the output of the first computing unit and the element of the second value corresponding to the input element output by the first selector. The first calculation is performed and output to the third calculation unit, and the third calculation unit performs the second calculation once for the output of the second calculation unit and the output of the output register. The operation circuit outputs the operation result value of the first value and the second value in which the input element is updated to the output register. The claim 1, further comprising:
A third register holding a third value having N elements;
The output register holds a product-sum operation value obtained by performing a product-sum operation on the third value in addition to the first value and the second value,
In the first phase, the first selector sequentially selects and outputs the N elements of the first, second, and third values so that the elements are paired, and the first selector In the second phase, in addition to the first and second value elements corresponding to the input element, the third value element in the third register corresponding to the input element is selected and output,
In the first phase, the multiplier is configured to output N elements of the first value and the second elements that are paired with the elements of the first value, which are sequentially output by the first selector. N elements of the value of 3 are sequentially multiplied and output to the adder, and the adder adds the output of the multiplier and the output of the output register N times to obtain the first value and A product-sum operation value of the second value and the third value is output to the output register;
In the second phase, the multiplier multiplies the output of the first subtracter and the elements of the second and third values corresponding to the input element output by the first selector. Output to the adder, the adder adds the output of the multiplier and the output of the output register once, and the input element is updated, the first value, the second value, An arithmetic circuit that outputs a product-sum operation value with the third value to the output register. In claim 1,
The first register holds a plurality of sets of the first value;
The second register holds the plurality of sets of the second values;
The output register holds the product-sum operation value of the first and second values of each of the plurality of sets;
In the first phase, the first selector sequentially selects and outputs the N elements of the first and second values for each of the plurality of sets such that the elements are paired. In the second phase, the first value element in the first register of the target set corresponding to the input element is selected and output, and the first of the target set corresponding to the input element is output. Select and output the second value element in register 2;
The first subtracter subtracts the element of the first value of the target set output by the first selector from the input element;
In the first phase, the multiplier outputs, for each of the plurality of sets, a product-sum operation value of the first value and the second value to the output register,
In the second phase, the multiplier outputs an output of the first subtracter and an element of the second value of the target set corresponding to the input element output by the first selector. Multiply and output to the adder, and the adder adds the output of the multiplier and the output of the output register of the target set once, and the input element is updated in the first set of the target set. And a product-sum operation value of the value of the target set and the second value of the target set are output to the output register of the target set. The second register according to claim 1, wherein the second register holds a plurality of sets of the second value,
The output register holds the product-sum operation value of the first value and the second value of each of the plurality of sets;
In the first phase, the first selector selects the N elements of the first value and the N elements of the second value of each of the plurality of sets as a pair. In the second phase, the first value element in the first register corresponding to the input element is selected and output, and each of the plurality of sets is selected. Selecting and outputting a second value element in the second register corresponding to the input element;
In the first phase, the multiplier pairs the N elements of the first value and the elements of the first value of each of the plurality of sets, which are sequentially output by the first selector. The N elements of the second value are sequentially multiplied and output to the adder, and the adder outputs the output of the multiplier and the output of the output register for each of the plurality of sets. Adding N times, and outputting a product-sum operation value of the first value and the second value of each of the plurality of sets to the output register;
In the second phase, the multiplier includes an output of the first subtracter and an element of the second value corresponding to the input element of each of the plurality of sets output from the first selector. And the adder adds the output of the multiplier and the output of the output register once for each of the plurality of sets, and the input element is updated. An arithmetic circuit that outputs a product-sum operation value of the first value and the second value of each of the plurality of sets to the output register.

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