KR960028472A - Code Generator of PT Vector Quantizer - Google Patents

Code Generator of PT Vector Quantizer Download PDF

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Publication number
KR960028472A
KR960028472A KR1019940038205A KR19940038205A KR960028472A KR 960028472 A KR960028472 A KR 960028472A KR 1019940038205 A KR1019940038205 A KR 1019940038205A KR 19940038205 A KR19940038205 A KR 19940038205A KR 960028472 A KR960028472 A KR 960028472A
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South Korea
Prior art keywords
code
vector
adder
carry
value
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KR1019940038205A
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Korean (ko)
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KR0169659B1 (en
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윤성욱
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배순훈
대우전자 주식회사
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Priority to KR1019940038205A priority Critical patent/KR0169659B1/en
Publication of KR960028472A publication Critical patent/KR960028472A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/94—Vector quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03891—Spatial equalizers
    • H04L25/03898—Spatial equalizers codebook-based design
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

본 발명은 PTS VQ엔코더의 코드발생기에 관한 것으로, 램억세스부(10)와; 계산부(20); 프리패치부(30); 및 코드발생기(40)를 구비한 PTSVQ 엔코더에 있어서, 계산결과값을 입력하여 시프트(shift)시키는 시프트 레지스터(41)와; 계산결과에 따라 카운트업하여 소정 값이 되면 캐리를 발생하는 가산기(44); 상기 가산기(44)의 캐리나 완료신호에 따라 상기 시프트된 레지스터값을 출력하는 출력버퍼(45); 및 상기 캐리와 완료신호의 논리합신호를 지연시켜 상기 시프트 레지스터(41) 및 가산기(44)를 클리어(clear)시키는 지연기(42)를 구비하여 입력벡터에 따라 부호책으로부터 가변비트율의 인덱스 코드를 발생한다.The present invention relates to a code generator of a PTS VQ encoder, comprising: a RAM access unit (10); A calculator 20; Prefetch unit 30; And a PTSVQ encoder having a code generator (40), comprising: a shift register (41) for inputting and shifting a calculation result value; An adder 44 which counts up according to a calculation result and generates a carry when a predetermined value is reached; An output buffer 45 for outputting the shifted register value in accordance with a carry or completion signal of the adder 44; And a delay unit 42 for delaying the logic sum signal of the carry and completion signals to clear the shift register 41 and the adder 44, thereby obtaining an index code of a variable bit rate from a code book according to an input vector. Occurs.

Description

피티에스 벡터양자화 부호기의 코드발생기Code Generator of PT Vector Quantizer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명이 적용되는 PTSVQ 엔코더를 도시한 블럭도.1 is a block diagram showing a PTSVQ encoder to which the present invention is applied.

Claims (1)

영상데이타를 읽어와 입력벡터(Vin)를 형성하는 램억세스부(10)와; 상기 부호책(5)으로부터 부호벡터를 미리 읽어와 좌측 부호벡터(VL)와 우측 부호벡터(VR)를 출력하고, 결과신호에 따라 선택된 가지(branch)의 노드를 중심으로 다시 우측 부호벡터와 좌측 부호벡터를 읽어오고, 단자 노드(terminal node)에 도달하면 완료신호(complete)를 발생하는 프리패치부(30); 상기 입력벡터(Vin)를 프리 패치된 좌측 부호벡터(VL) 및 우측 부호벡터(VR)와 왜곡치를 계산하여 왜곡치가 적은 쪽의 가지를 선택하도록 상기 결과신호를 출력하는 계산부(20); 및 상기 계산부(20)의 결과신호에 따라 해당 부호벡터의 인덱스 코드를 생성하여 상기 완료신호(complete)에 따라 출력하는 코드발생기(40)를 구비하는 PTS VQ 엔코더에 있어서, 상기 코드발생기(40)는 계산결과값을 입력하여 시프트(shift)시키는 시프트 레지스터(41)와; 계산결과에 따라 카운트업하여 소정 값이 되면 캐리를 발생하는 가산기(44); 상기 가산기(44)의 캐리나 완료신호에 따라 상기 시프트된 레지스터값을 출력하는 출력버퍼(45); 및 상기 캐리와 완료신호의 논리합신호를 지연시켜 상기 시프트 레지스터(41) 및 가산기(44)를 클리어(clear)시키는 지연기(42)를 구비한 것을 특징으로 하는 피티에스 벡터양자화 부호기의 코드발생기.A RAM access unit 10 reading image data to form an input vector Vin; The code vector is read in advance from the code book 5 and the left code vector VL and the right code vector VR are output, and the right code vector and the left are again centered on the node of the branch selected according to the result signal. A prefetch unit 30 that reads a sign vector and generates a completion signal when it reaches a terminal node; A calculation unit (20) for calculating the distortion value with the pre-patched left sign vector (VL) and right sign vector (VR) from the input vector (Vin), and outputting the result signal to select a branch having the least distortion value; And a code generator (40) for generating an index code of a corresponding code vector according to the result signal of the calculation unit (20) and outputting the index code of the corresponding code vector according to the completion signal (complete). Is a shift register 41 for inputting and shifting a calculation result value; An adder 44 which counts up according to a calculation result and generates a carry when a predetermined value is reached; An output buffer 45 for outputting the shifted register value in accordance with a carry or completion signal of the adder 44; And a delay unit (42) for clearing the shift register (41) and the adder (44) by delaying the logical sum signal of the carry and completion signals. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038205A 1994-12-28 1994-12-28 Circuit for generating codes in pts vq encoder KR0169659B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038205A KR0169659B1 (en) 1994-12-28 1994-12-28 Circuit for generating codes in pts vq encoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038205A KR0169659B1 (en) 1994-12-28 1994-12-28 Circuit for generating codes in pts vq encoder

Publications (2)

Publication Number Publication Date
KR960028472A true KR960028472A (en) 1996-07-22
KR0169659B1 KR0169659B1 (en) 1999-03-20

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KR0169659B1 (en) 1999-03-20

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