KR960028549A - Fast Affine Inverter for Fractal Image Coding - Google Patents

Fast Affine Inverter for Fractal Image Coding Download PDF

Info

Publication number
KR960028549A
KR960028549A KR1019940038644A KR19940038644A KR960028549A KR 960028549 A KR960028549 A KR 960028549A KR 1019940038644 A KR1019940038644 A KR 1019940038644A KR 19940038644 A KR19940038644 A KR 19940038644A KR 960028549 A KR960028549 A KR 960028549A
Authority
KR
South Korea
Prior art keywords
data
affine
transform coefficient
affine transformation
control signal
Prior art date
Application number
KR1019940038644A
Other languages
Korean (ko)
Other versions
KR0170934B1 (en
Inventor
최한호
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019940038644A priority Critical patent/KR0170934B1/en
Publication of KR960028549A publication Critical patent/KR960028549A/en
Application granted granted Critical
Publication of KR0170934B1 publication Critical patent/KR0170934B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/99—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals involving fractal coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Compression Of Band Width Or Redundancy In Fax (AREA)

Abstract

본 발명은 프랙탈 영상 부호화에 있어서 고속 아핀 변환(Affine Transform)장치를 제안하고 있는데, 동일크기의 픽셀블럭(pixeblock)으로 나뉘어진 프레임(Frame)의 프랙탈(Fractal) 영상 부호화를 위한 아핀 변환(Affine Transformation) 장치는, 상기 각 블럭과 대응되어 있으며, 상기 대응되어 있는 블럭 내 픽셀 데이타(D)를 순차적으로 입력받고, 제1변환계수(A) 및 제2변환계수(B)를 입력받아, 제1제어신호(C1)에 응답하여, 상기 픽셀 데이타(D)의 아핀 변환을 식 W = A * D + B에 따라서 수행하고, 상기 변환으로 얻어진 아핀 변환 데이타(W)를 출력하는 다수개의 연산부와, 상기 다수개의 연산부와 각각 대응되어 있으며, 상기 대응되어 있는 연산부로부터 제공되는 아핀 변환 데이타(W)를 기록하며, 제2제어신호(C2)에 응답하여, 상기 기록하고 있는 아핀 변환 데이타(W)를 출력하는 다수개의 레지스터부와, 상기 다수개의 연산부로부터 제공되는 다수개의 아핀 변환 데이타(W)의 수렴도를 기설정된 계산식에 따라서 판정하고, 상기 판정결과 상기 다수개의 아핀 변환 데이타(W)의 수렴도가 기설정 범위를 벗어나는 경우에 제1제어신호(C1)를 출력하고, 반대인 경우에 제2제어신호(C2)를 출력하는 제어부를 포함하며, 상기 픽셀 데이타(D)는 NX1의 매트릭스 형태이며, 상기 제1변환 계수(A)는 NXN의 매트릭스 형태이고, 상기 제2변환 계수(B)는 NX1의 매트릭스 형태이다.The present invention proposes a fast affine transform device for encoding a fractal image. An affine transform is used to encode a fractal image of a frame divided into pixelblocks of the same size. The apparatus corresponds to each of the blocks, sequentially receives pixel data D in the corresponding block, receives a first transform coefficient A and a second transform coefficient B, and A plurality of arithmetic units which perform affine transformation of the pixel data D according to a formula W = A * D + B in response to a control signal C1, and output affine transformation data W obtained by the transformation; The affine transformation data W corresponding to the plurality of arithmetic units, respectively, is recorded, and the affine transformation data W provided from the corresponding arithmetic unit is recorded, and the affine transformation data W is recorded in response to the second control signal C2. Output A convergence degree of a plurality of register parts and a plurality of affine conversion data W provided from the plurality of calculation units is determined according to a predetermined calculation formula, and the convergence degree of the plurality of affine conversion data W is determined based on a predetermined calculation result. A control unit for outputting a first control signal C1 when out of a setting range, and outputting a second control signal C2 in the opposite case, wherein the pixel data D is in the form of a matrix of NX1. The first transform coefficient A is in the form of a matrix of NXN, and the second transform coefficient B is in the form of a matrix of NX1.

Description

프랙탈 영상 부호화를 위한 고속 아핀 변환장치Fast Affine Inverter for Fractal Image Coding

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 프랙탈 영상 부호화 및 복호화 장치의 동작을 도식적으로 설명하기 위한 블럭도, 제2도는 본 발명에 따른 프랙탈 영상 부호화를 위한 아핀 변환장치의 동작을 도식적으로 설명하기 위한 블럭도, 제3도는 본 발명에 따른 프랙탈 영상 부호화를 위한 아핀 변환장치를 구성하는 매트릭스 계산부의 블록도1 is a block diagram schematically illustrating the operation of a conventional fractal image encoding and decoding apparatus, FIG. 2 is a block diagram schematically illustrating the operation of an affine transformation apparatus for fractal image encoding according to the present invention, and FIG. FIG. Is a block diagram of a matrix calculation unit constituting an affine transform apparatus for fractal image encoding according to the present invention.

Claims (2)

동일크기의 픽셀블럭(pixelblock)으로 나뉘어진 프레임(Frame)의 프랙탈(Fractal) 영상 부호화를 위한 고속 아핀 변환(Affine Transformation) 장치에 있어서, 상기 각 블럭과 대응되어 있으며, 상기 대응되어 있는 블럭내 픽셀 데이타(D)을 순차적으로 입력받고, 제1변환계수(A) 및 제2변환계수(B)를 입력받아, 제1제어신호(C1)에 응답하여, 상기 픽셀 데이타(D)의 아핀 변환을 하기식A fast affine transform apparatus for encoding a fractal image of a frame divided into pixelblocks of the same size, the pixel corresponding to each block and corresponding pixel in the block The data D is sequentially input, the first transform coefficient A and the second transform coefficient B are input, and the affine transformation of the pixel data D is performed in response to the first control signal C1. Formula W =A*D +B에 따라서 수행하고, 상기 변환으로 얻어진 아핀 변환 데이타(W)를 출력하는 다수개의 연산부와; 상기 다수개의 연산부와 각각 대응되어 있으며, 상기 대응되어 있는 연산부로 부터 제공되는 아핀 변환 데이타(W)를 기록하며, 제2제어신호(C2)에 응답하여, 상기 기록하고 있는 아핀 변환 데이타(W)를 출력하는 다수개의 레지스터부와; 상기 다수개의 연산부로부터 제공되는 다수개의 아핀 변환데이타(W)의 수렴도를 기설정된 계산식에 따라서 판정하고, 상기 판정결과 상기 다수개의 아핀 변환 데이타(W)의 수렴도가 기설정 범위를 벗어나는 경우에 제1제어신호(C1)를 출력하고, 반대인 경우에 제2제어신호(C2)를 출력하는 제어부를 포함하며, 상기 픽셀 데이타(D)는 NX1의 매트릭스 형태이며, 상기 제1변환 계수(A)는 NXN의 매트릭스 형태이고, 상기 제2변환 계수(B)는 NX1의 매트릭스 형태인 것을 특징으로 하는 프랙탈 영상 부호화를 위한 고속 아핀 변환장치A plurality of arithmetic units which perform according to W = A * D + B and output the affine transformation data W obtained by the transformation; The affine transformation data W corresponding to the plurality of arithmetic units, respectively, is recorded in the affine transformation data W provided from the corresponding arithmetic operation unit, and in response to a second control signal C2. A plurality of register units for outputting the plurality of registers; When the convergence degree of the plurality of affine transformation data W provided from the plurality of calculation units is determined according to a predetermined calculation formula, and when the convergence degree of the plurality of affine transformation data W is out of a preset range as a result of the determination A control unit for outputting a first control signal C1 and outputting a second control signal C2 in the opposite case, wherein the pixel data D is in the form of a matrix of NX1, and the first transform coefficient A ) Is a matrix form of NXN, and the second transform coefficient (B) is a fast affine transform apparatus for fractal image coding, characterized in that the matrix form of NX1. 제1항에 있어서, 상기 연상부는, 상기 픽셀 데이타(D), 또는 NX1의 아핀 변환 데이타(W)를 제공받아 선택적으로 출력하되, 상기 픽셀 데이타(D)의 입력을 알려주는 부가정보인 시작신호(S)가 입력되는 경우에는 상기 픽셀 데이타(D)를 출력하는 선택부와; 상기 제1변환 계수(A)를 입력받으며, 상기 제1 제어신호(C1)에 응답하여, 상기 선택부로 부터 제공되는 데이타와 상기 제1변환 계수(A)를 승산하고, 상기 승산결과로 얻어진 NX1의 데이타(R)를 출력하는 매트릭스 승산부와; 상기 제2변환 계수(B)를 입력받으며, 상기 매트릭스 승산부로부터 제공되는 NX1의 데이타(R)와 상기 제2변환 계수(B)를 덧셈하고, 상기 덧셈 결과로 얻어진 아핀 변환 데이타(W)를 상기 선택부, 상기 제어부 및 상기 대응되는 레지스터부로 출력하는 매트릭스 덧셈부를 포함하는 것을 특징으로 하는 프랙탈 영상 부호화를 위한 고속 아핀 변환장치The start signal according to claim 1, wherein the associating unit receives the pixel data (D) or the affine transformation data (W) of NX1 and selectively outputs the start signal, which is additional information indicating an input of the pixel data (D). A selection unit which outputs the pixel data D when (S) is input; NX1 obtained by receiving the first transform coefficient A, multiplying the first transform coefficient A by data provided from the selection unit in response to the first control signal C1, and obtaining the multiplication result. A matrix multiplier for outputting data R; The second transform coefficient B is input, the data R of NX1 and the second transform coefficient B provided from the matrix multiplier are added, and the affine transform data W obtained as a result of the addition is added. And a matrix adder for outputting to the selector, the control unit and the corresponding register unit.
KR1019940038644A 1994-12-29 1994-12-29 High-speed affine transformation apparatus in the fractal encoding KR0170934B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038644A KR0170934B1 (en) 1994-12-29 1994-12-29 High-speed affine transformation apparatus in the fractal encoding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038644A KR0170934B1 (en) 1994-12-29 1994-12-29 High-speed affine transformation apparatus in the fractal encoding

Publications (2)

Publication Number Publication Date
KR960028549A true KR960028549A (en) 1996-07-22
KR0170934B1 KR0170934B1 (en) 1999-03-20

Family

ID=19404864

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940038644A KR0170934B1 (en) 1994-12-29 1994-12-29 High-speed affine transformation apparatus in the fractal encoding

Country Status (1)

Country Link
KR (1) KR0170934B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1465035A (en) * 2001-06-21 2003-12-31 Hi股份有限公司 Information processor

Also Published As

Publication number Publication date
KR0170934B1 (en) 1999-03-20

Similar Documents

Publication Publication Date Title
US4829465A (en) High speed cosine transform
KR960003648B1 (en) Devices and method of dealing picture data
US5331585A (en) Orthogonal transformation processor for compressing information
EP0661886A2 (en) Method and apparatus for fast digital signal decoding
KR880001165A (en) 1-D cosine transform calculation device
US6052703A (en) Method and apparatus for determining discrete cosine transforms using matrix multiplication and modified booth encoding
JPH11225334A (en) Dispersion value calculation accelerator for mpeg-2 image decoder
KR19990022657A (en) Discrete Cosine Transformation Computation Circuit
KR950010640A (en) Signal processing equipment
JPS622721A (en) Coding and decoding device for picture signal
JPH10504408A (en) Apparatus and method for performing inverse discrete cosine transform
JPH05260313A (en) Data processing method of discrete cosine transform (dct), dct method, and dct data processing circuit
KR960028549A (en) Fast Affine Inverter for Fractal Image Coding
US5359549A (en) Orthogonal transformation processor for compressing information
KR930701899A (en) Image data conversion process and device
KR960028491A (en) Fast Affine Transformation Device for Fractal Image Coding
KR960028492A (en) Fast Affine Transformation Device for Fractal Image Coding
KR950009679B1 (en) Method for correcting blockwise transmitted discrete values
JP2960328B2 (en) Apparatus for providing operands to "n + 1" operators located in a systolic architecture
KR960028483A (en) Affine Transformation Device for Fractal Image Coding
KR960028484A (en) Affine Transformation Device for Fractal Image Coding
JP2790911B2 (en) Orthogonal transform operation unit
KR910008454B1 (en) Transformation circuit
KR960028550A (en) Affine Inverter for Fractal Image Coding
JP2923527B2 (en) Image data encoding / decompression device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20111004

Year of fee payment: 14

FPAY Annual fee payment

Payment date: 20121002

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee