KR960014197B1 - Distributed arithmetic unit - Google Patents

Abstract

a multi-input part(100) inputting 12 bit input pixel and performing the bit sequence conversion of the 8 pixel value; an one-dimensional converting part(200) performing the discrete cosine transforming of the output signal of the multi-input part; a 2 bit parallel bit sequential procession transforming part(300) performing the procession transform processing of the output signal of the one-dimensional converting part(200); an one-dimensional transform part(400) performing the discrete cosine transform operation of the output signal of the 2 bit parallel bit sequential procession transforming part(300); and an output part(500) outputting the output signal of the one-dimensional transform part(400) as 12 bit parallel data.

Description

8 × 8 2D Discrete Cosine Transform / Inverse Transformation Processor Using Pipeline Distributed Operations

1 is a block diagram of an 8x8 two-dimensional discrete cosine transform apparatus using a conventional distributed operation.

2 is a block diagram of an 8x8 two-dimensional discrete cosine transform / inverse transform processing apparatus using pipelined dispersion operation of the present invention.

3 is a detailed block diagram of a second input unit;

4 is a detailed block diagram of a one-dimensional transform unit of the second-stage pipeline structure of FIG.

5 is an explanatory view of the principle of use of the look-up table of FIG.

FIG. 6 is a block diagram of a pipeline carry storage divisional processing unit having multiple inputs and outputs.

FIG. 7 is a detailed block diagram of the pipeline carry-on accumulator of FIG.

8 is a detailed block diagram of a pipeline bit sequential adder of FIG.

9 is a detailed block diagram of a 2-bit parallel bit sequential matrix transform unit of FIG.

10 is a basic cell block diagram of a bit sequential matrix conversion unit of FIG.

* Explanation of symbols for the main parts of the drawings.

100: input unit 110, 120: delay and bit sequential converter

130: code extension 200,400: one-dimensional transform unit of the two-stage pipeline structure

210: 2-bit adder / subtracter 220: Forward / reverse motion selector

230,230 ': Lookup table 240,240': Pipeline carry storage accumulator

241: carry storage bit processor 248: half-added

220, 246,247, 250, 256, 280: Multiplexer

261, 262: pipeline bit sequential adder

242,243,244, 264,266: Full adder 265,267, 268: Latch

300: 2-bit parallel bit sequential matrix converter 310: matrix converter bone cell

311, 313: shift register 312: multiplexer

500: output unit

The present invention relates to an 8x8 two-dimensional discrete cosine transform / inverse transform processing apparatus using pipeline distributed computation that enables high-performance processing of compression algorithms for international standard image and multimedia data based on pipeline distributed computation.

FIG. 1 is a block diagram of an 8x8 two-dimensional discrete cosine transforming apparatus using conventional distributed arithmetic. As shown in FIG. 1, a 12-bit data input is inputted to store 8 pixels for 8 cycles and a bit through a shift register. An input unit 1 for converting in sequence, a transverse one-dimensional transform unit 2 for receiving the output signal of the input unit 1 and performing discrete cosine transform processing in a distributed arithmetic method and outputting it in bit order; A serial / parallel converter 3 for converting the drawn symbol of the directional one-dimensional converter 2 into a parallel form, and an output signal of the serial / parallel converter 3, stored therein, and then the order of the input rows and columns A matrix conversion memory (4) for converting and outputting the data, a parallel / serial conversion section (5) for converting the output signals of the matrix conversion memory (4) in serial form, and outputting them in bit order; Distributed output by receiving output signal of (5) Inputs the longitudinal one-dimensional conversion unit 6, the longitudinal one-dimensional conversion unit 6, and the output signal of the longitudinal one-dimensional conversion unit 6 which perform discrete cosine conversion processing and output in bit order as a processing method. And an output unit 7 for receiving and storing 12-bit parallel data.

However, in the conventional apparatus as described above, a memory is used to matrix-transform the results of one-dimensional arithmetic processing, and for this purpose, intermediate results appearing in a sequential form must be converted into a parallel data form. It is difficult to pipeline the operation, and the one-dimensional conversion unit for discrete cosine conversion uses a parallel adder and a parallel accumulator.Therefore, the processing speed is delayed due to the propagation delay caused by the carry operation during parallel operation. There was a limit to the improvement, and the system had to be complicated by using a separate lookup table or two-step matrix decomposition to share the forward and reverse functions.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described drawbacks, and by using a parallel multiplexed input / output structure and a bit sequential matrix converter, the data conversion function of intermediate results is unnecessary, so that the entire conversion process can be performed in bit sequential processing. In addition, it is possible to process one pixel in one clock cycle by performing forward or reverse discrete cosine conversion in eight cycles by using sixteen parallel pipeline carry storage splitting and variance calculators. Using the conversion of, the forward and reverse discrete cosine transform functions can be performed by the same lookup table without any additional operation.

This invention is described in detail with reference to the accompanying drawings as follows.

2 is a block diagram of the entire 8x8 two-dimensional discrete cosine transform / inverse transform processing apparatus using the pipeline dispersion operation of the present invention. As shown in the drawing, a multi-input unit 100 for inputting eight input pixel values of 12 bits for eight cycles and simultaneously converting the eight inputted pixel values in two bits in parallel and outputting the two-stage pipe 8 horizontal parallel processing processors, each of which has a parallel structure, receives the output signal of the multi-input unit 100 and performs a horizontal discrete cosine transform or an inverse transform operation to output two bits in bit order. A two-bit parallel bit sequential matrix converter 300 for sequentially converting and outputting the two-dimensional output signal of the one-dimensional transform unit 200 in a line structure, and performing a matrix conversion process on the two-dimensional parallel The output signal of the bit sequential matrix converter 300 is composed of a one-dimensional transform unit 400 of the horizontal two-stage pipeline structure and a structure symmetrical with the multiple input unit 100 and the two-stage longitudinal direction Of pipeline structure Storing the output signal of the level converter 400 receives input and an output unit 500 for outputting in parallel data of 12 bits.

3 is a detailed block diagram of the multiple input unit 100 of FIG. As shown in the figure, eight delay and bit sequential converting units 110 for receiving delay and bit sequential conversion from the input bits of the even bit among the 12 bit input pixels, and the odd bit input pixels among the 12 bit input pixels. 8 delay and bit sequential converters 120 for receiving delay and bit sequential conversion, and output signals of the eight delay and bit sequential converters 110 and 120, respectively, It consists of eight code extension sections 130 that extend and output the bit sequence data _Doe to D _7e and the odd bit bit sequence data D _0o to D _7o . The eight delay and bit sequential converting units 110 and 120 and the code expansion unit 130 repeat the 8x1 discrete cosine transform eight times to perform one-dimensional discrete cosine transform on the 8x8 sized data. It has an input structure that performs it. In addition, the bit-sequential data _Doe -D _7e of even-numbered bits and the bit-sequential data D _0o to D _7o of odd bits, that is, output from the multiple input unit 100 as described above, that is, two bits of parallel data D _0. D ₇ ) is input to the one-dimensional transform unit 200 of the lateral two-stage pipeline structure, and the pipeline processing is performed to process the continuous processing in the eight cycle clock by the addition processing generated during the matrix operation in the discrete cosine transform. Is required.

4 is a detailed block diagram of the one-dimensional transformation unit 200 of the second-stage transverse two-stage pipeline structure. As shown, a 2-bit addition / subtraction unit for adding and subtracting 2-bit parallel data (D ₇ to D ₄ ) to the 2-bit parallel data (D ₀ to D ₃ ) output from the multiple input unit 100 ( 210 and the forward / reverse motion selector 220 for selecting and outputting the output signal of the 2-bit addition / subtraction unit 210 and the output signal of the multiple input unit 100 according to the forward or reverse operation modes, and the forward / reverse operation. A lookup table 230 that receives the output signal of the selector 220 as an input signal and outputs a signal according to the output signal, a pipeline carry storage accumulator 240 that accumulates an output signal of the lookup table 230, and The multiplexer 250 for selecting and outputting a signal output from a lower pipeline carry storage accumulator (CAS [0] to CAS [7]) among the pipeline carry storage accumulator 240 and the pipeline carry storage accumulator ( Upper Pipeline Carry-On Accumulator of 240 (CAS [8]) Pipeline bit sequential adder 260 for bit sequential addition of the signal output from CAS [15]) and the output signal of the multiplexer 250, and the lower output signal T ₀ of the pipeline bit sequential adder 260. Pipeline bit sequential adder 270 that adds and subtracts the upper level output signals T ₄ to T ₇ to ˜T ₃ ), and a signal that is added and subtracted by this pipeline bit sequential adder 270 and output. And a forward / reverse operation selector 280 that selects an output signal of the bit sequential adder 260 according to a forward or reverse operation mode and outputs the two bits of parallel data D ₀ to D ₇ .

Meanwhile, the one-dimensional transform unit 400 of the longitudinal two-stage pipeline structure is also configured in the same manner as the one-dimensional transform unit 200 of the two-direction pipeline structure.

Since the eighth cycle is a sign bit operation in the multi-variance operation, the result of the 2-bit addition / subtraction unit 210 is an input of the lookup table.The upper bit of the two bits always has a value of 0, and the lower bit has a value of the sign bit. did. For this purpose, the output from transverse transformation has a rounded 14-bit value.

5 is an explanatory view illustrating a principle of enabling the fourth lookup table 230 to operate regardless of the inverse transform and the forward transform. (A) of FIG. 5 is an 8 × 8 matrix of transform coefficients, and (b) and (c) of FIG. 5 are forward and inverse transform matrices through matrix decomposition. to be. In the forward conversion, 8 × 8 coefficients are transformed into 4 × 4 matrix coefficients (a) and (b) as shown in (b) of FIG. 5 through matrix decomposition. An input lookup table can be constructed, and in the reverse conversion, the 8 × 8 coefficients are converted into 4 × 4 matrix coefficients (a ') and (b') as shown in (c) of FIG. Each of the two coefficients can be combined to form eight two-input lookup tables. However, as can be seen from (b) and (c) of FIG. 5, the 4x4 matrix coefficients (b ') and (b') are identical to each other, and thus can be equally applied in forward and inverse transformation, but 4x4 The matrix coefficients (a ') and (a') differ from each other in three combinations of eight lookup tables, i.e., -fX-bY, -dx + dY, and bx-fY in the forward transform, and -bx-fY and dx in the inverse transform. Since -dY and -fx + bY are different, they cannot be applied equally in the forward and reverse conversion. However, since the three lookup tables have the same coefficient and the same sign, and only the positions of the input pixels (x) and (Y) are different from each other, the forward / reverse operation selector 220 which is a multiplexer according to the change of the forward and reverse operation modes is used. By changing the input pixels X and Y alternately, the same lookup table can be used.

In addition, when the 4x4 matrix coefficient (a ') (a') is to be realized as the same lookup table, the pipeline bit sequence adder (SPL) is used to divide the distributed calculation value using the multiplexer 250 according to the forward and reverse operation selection. 260 may be applied to implement.

Since this structure does not require an additional matrix transformation, there is no additional computation cycle at the input unit 100, so that the hardware structure is regular.

The pipeline bit sequential adder 270 is required to add and subtract the inverse transform matrix operation result again. The forward and reverse operation selector 280, which is a multiplexer, selects and outputs the forward conversion result and the reverse conversion result.

6 is a pipeline carry storage type divisional dispersion processing unit 230, 240, or 240 having multiple inputs and outputs, which is one of the eight divisional dispersion processors which constitute the one-dimensional transform unit of the two-stage pipeline structure of FIG. 260 is a block diagram for explaining the operation. As shown in FIG. 4, the four data D ₀ to D ₃ decomposed through the matrix decomposition process input two 8-bit data each by two bits, and divide the data into four bits again and receive two lookuptables applied to the address 230. ), (230 ') and two pipeline carry storage accumulators (240', 240 ') that accumulate and output the output signals of the two lookup tables 230 and 230', respectively, to a binary value. ) And a pipeline bit sequential adder 260 that bit-sequences the output signals AS ₁ , AS ₂ , BS ₁ , and BS ₂ of the two pipeline carry storage accumulators 240 and 240 ′. do. The contents of the lookup table store the values of aX ₁ + bX ₁ + 2 (aX ₂ , bX ₂ ) when the constants a and b and the inputs are X ₁ , X ₂ , Y ₁ and Y ₂ .

During one cycle, four bits are input from the lookup tables 230 and 230 'in parallel and output as 16 bits of historical data, and the pipeline carry storage accumulators 240 and 240' perform a cumulative operation without carry propagation delay. During accumulation, the pipeline carry storage accumulator (240,240 ') sequentially executes the 2-bit parallel output converted from the lowest bit output to the binary value, and the parallel output is performed with the 8 cycle time difference between the first stage and the second stage. do. The pipeline bit sequential adder 260 simultaneously computes the two-stage output signals AS ₁ , AS ₂ , BS ₁ , and BS ₂ of the pipeline carry storage accumulators 240 and 240 ′, thereby performing continuous two. The first pipeline output signal S ₁ and the second pipeline output signal S ₂ of the bit are output in parallel.

7 is a detailed block diagram of the pipeline carry storage accumulator 240 of FIG. As shown in FIG. 1, a first stage pipeline carry storage accumulator and a first stage pipeline carry storage accumulator for accumulating 16 bits of signals S ₀ to S ₁₅ output from the lookup table 230 for eight cycles. After selecting the output signal of, it consists of a two-stage pipeline carry storage accumulator that converts the carry storage numerical meter into a binary one for 8 cycles.

The first stage pipeline carry storage accumulator includes 16 carry storage bit processors configured as shown by reference numeral 241, and each bit processor includes a bit signal output from the lookup table 230 and a carry signal C of a higher bit processor. ) And the sum signal S of the 2-bit high-order bit processor are input from the full adder 242 to perform repeated accumulation operation for 8 cycles, thereby eliminating the carry propagation delay time.

At this time, the pipeline carry storage accumulator performs a cumulative operation and simultaneously converts the operation result converted into a binary numerical meter by the lowest two full adders 243 and 244 into two-bit output signals AS ₁₁ and AS ₁₂ . Will print.

On the other hand, in the ninth cycle after the eighth cycle operation, each bit processor 245 in the two-stage pipeline carry storage accumulator outputs the output signal of the one-stage pipeline carry storage bit processor through the multiplexers 246 and 247. Accumulate and transform operations, and select and carry the bit processor output signals of the two-stage pipeline carry storage accumulator in the same manner as in the first stage through the multiplexers 246 and 247 for the remaining seven cycles. Performs the operation of converting the stored numerical meter to the binary numerical meter, and outputs the result of the operation converted from the least significant bit into the binary value meter as a two-bit two-stage output signal (AS ₂₁ , AS ₂₂ ).

In the conversion operation for outputting the cumulative calculation and the carry storage numerical value to the binary numerical value, the code bit extension of the upper bit processing part is required, which is implemented by the connection method of the upper bit processor of FIG. In addition, the pipeline carry storage accumulator 240 ′ is configured in the same manner as the pipeline carry storage accumulator 240 as described above, and the 2-bit two-stage output signals BS ₁₁ and BS ₁₂ are applied to the BS _21. , BS ₂₂ ).

FIG. 8 is a detailed block diagram of the FIG. 6 pipeline bit sequential adder 260. As shown, the first pipeline bit sequential adder 261, which bit-orderly adds the output signals ASI ₁ , ASI ₂ , BSI ₁ , BSI _{2 of the} pipeline carry storage accumulators 240, 240 ′. And the output signals of the pipeline carry storage accumulators 240 and 240'and output from ASII ₁ and ASII ₂ , BSII ₁ and BSII ₂ and the first pipeline bit sequential adder 261. And a second pipeline bit sequential adder 262 that adds the carry output signal C ₁₂ in bit order. The first pipeline bit sequential adder 261 converts the output signals ASI ₁ , BSI ₁ and carry output signal C ₁₂ of the pipeline carry storage accumulator 240 (240 ′) into a multiplexer 263. A latch 265 for outputting the full adder 264 and the sum signal S of the full adder 264 to the first pipeline output SI ₁ , and the pipeline carry storage accumulator 240 ( A full adder 266 for adding the output signals ASI ₂ and BSI ₂ of the 240 'and the carry output signal C _{11 that} is the carry signal C of the full adder 264; A latch 267 for outputting the first pipeline output signal SI ₂ according to the sum signal S of the signal 266, and the carry output signal C ₁₂ according to the carry signal C of the full adder 266. ) Is configured as a latch 268 that outputs.

Further, the second pipeline bit sequential adder 262 is configured in the same way as the pipeline bit sequential adder 261.

However, the multiplexer 263 'of the two-stage pipeline bit sequential adder 262 selects the output signal of the latch 268 of the one-stage pipeline bit sequential adder 261 in the ninth cycle, and the two-stage pipe in the other cycle. The carry output signal C ₂₂ , which is an output signal of the latch 268 ′ in the line bit sequence adder 262, is selected and output.

FIG. 9 is a detailed block diagram of the 2-bit parallel bit sequential matrix converter 300 of FIG. 2, and the even-bit sequential data output from the one-dimensional transform unit 200 of the two-stage horizontal pipeline structure as shown in FIG. (X _0e -X _7e ) are outputted as even-matrix transformation output data (X _0e -X _7e ) from the first step to the third step by 2 bits each, and the one-dimensional conversion of the two-stage pipeline structure. The odd bit sequential data (X _0e -X _7e ) output from the unit 200 is changed into the odd bit matrix conversion output data (X _0e -X _7e ) by changing their order from the first step to the third step by two bits each. Configure the output.

FIG. 10 is a detailed block diagram of a matrix transformation basic cell in which a 2-bit parallel bit sequential matrix converter 300 performs matrix transformation by 2 bits. Here, 2 bits of even-bit sequential data (X _0e , X _1e ) are represented. An example of the matrix transformation base cell 310 for matrix transformation is shown.

That is, the shift register 311 which delays the even-bit sequential data X _1e , the output signal of the even-bit sequential data X _0e and the shift register 311 are input to the control signal CS. The multiplexer 312 outputs the input signal as its output signals M ₀ and M ₁ as it is or as an output signal M ₀ and M ₁ , and the output of the multiplexer 312. The shift register 313 delays the signal M _0. The output signal of the shift register 313 and the output signal of the multiplexer 312, M ₁ , are matrix conversion output signals t ₀ , ( t ₁ ) respectively. In addition, another horizontal transformation base cell which is matrix-transformed by two bits is also configured in the same manner as the matrix transformation base cell 310. Therefore, even-bit sequential data (X _0e ) output from the one-dimensional transform unit 200 of the lateral 2-stage pipeline structure is directly applied to the multiplexer 312 of the matrix transformation basic cell 310, and the lateral 2-stage pipeline structure is directly applied to the multiplexer 312. The even-bit sequential data X _1e output from the one-dimensional transform unit 200 of the pipeline structure is delayed while being shifted from the shift register 311 and applied to the multiplexer 312. Here, the control signal CS is shift register. It has a high potential and a low potential period as many as (311,323) shift bits. For example, when the shift bits of the shift registers 311 and 313 are 8 bits, the control signal CS applies the fixed and low potentials alternately for 8 cycles. Accordingly, during the eight cycles in which the control signal CS is high, the even-bit sequential data X _0e and the even-bit sequential data X _1e shifted 8 bits in the shift register 311 are output signals of the multiplexer 312. Even-bit sequential data (X _1e ) and even-bit sequential data (X _1e ) shifted eight bits in the shift register 311 during eight cycles, respectively outputted as (M ₀ , M ₁ ) and the control signal CS is low potential. _0e ) is output to the output signals M ₀ and M ₁ of the multiplexer 312, respectively. The output signal M ₀ of the multiplexer 312 thus output is shifted 8 bits in the shift register 313 and output as a matrix conversion output signal t ₀ , and the output signal M ₁ of the multiplexer 312 is a matrix. It is output directly to the conversion output signal t ₁ . On the other hand, the 2-bit parallel bit sequential matrix transformation unit 300 can be configured in a larger structure through the expansion of the number of bits.

As described in detail above, the present invention uses a parallel multiplexed input / output structure and a bit sequential matrix converter so that the data conversion function of intermediate results is unnecessary, so that the entire conversion process can be performed in bit sequential processing, and the carriage delay time is eliminated. And three-stage pipelini operation to improve the processing speed so that 5 × 10 ⁷ pixels can be processed per second. Also, 16 parallel pipeline carry storage division and dispersion operators can be used in one cycle. The discrete cosine transform in the forward and reverse directions is performed at the ratio of one pixel, and there is an effect that can be performed by the lookup table.

Claims (8)

A multi-input unit 100 for inputting 8 input pixel values of 12 bits for 8 cycles and simultaneously converting 8 inputted pixel values in 2-bit parallel order and outputting the multi-input unit 100. A one-dimensional transform unit 200 of a two-stage pipeline structure for performing a discrete cosine transform operation by receiving a signal and performing a common cosine transform and a two-bit parallel bit sequence, and a one-dimensional structure of the two-stage pipeline structure A 2-bit parallel bit sequential matrix converter 300 for receiving an output signal from the converter 200 and performing matrix conversion processing for each bit to output the same 2-bit parallel bit sequence as the input, and the 2-bit parallel bit sequential type A longitudinal direction that receives the output signal of the matrix transform unit 300 and performs a discrete cosine transform operation in the same manner as the one-dimensional transform unit 200 of the lateral two-stage pipeline structure and outputs it in 2-bit parallel bit order. It is composed of a one-dimensional conversion unit 400 of the two-stage pipeline structure, and a structure that is symmetrical to the multiple input unit 100 and receives and stores the output signal of the one-dimensional conversion unit 400 of the longitudinal two-stage pipeline structure An 8x8 two-dimensional discrete cosine transform / inverse transform processing apparatus using pipeline distributed arithmetic, characterized in that the output unit 500 outputs 12-bit parallel data. The multi-input unit 100 includes: eight delay and bit sequential converters 110 for receiving delay input and bit sequential conversion from input bits of 12-bit input pixels, and 12 bits. Eight delay and bit sequential converters 120 for receiving delay input and bit sequential conversion among the input pixels of the input pixels, and the eight delay and bit sequential converters 110, 120 characterized in that the configured receiving respectively the output signal of eight sign extension unit 130 which outputs a bit sequence data (D _0e ~ D _7e) and the odd number bit bit sequence data (D _0e ~ D _7e) of the even bits 8x8 two-dimensional discrete cosine transform / inverse transform processing apparatus using pipeline distributed computation. According to claim 1, wherein the one-dimensional conversion unit 200 of the two-stage horizontal pipeline structure is a two-bit parallel data (D ₀ ~ D ₃ ) from the two-bit parallel data (D ₀ ~ D ₃ ) output from the multiple input unit 100 ₇ to D ₄ ), respectively, to add and subtract each of the adder and subtractor 210 and the output signal of the adder / subtractor 210 and the outputs D ₀ to D ₇ of the multiple input unit 100 to operate in the forward / reverse direction. A forward / reverse motion selector 220 that selects and outputs a mode according to a mode, a lookup table 230 that receives an output signal of the forward / reverse motion selector 220 and outputs a signal according thereto, and the lookup table 230 A pipeline carry storage accumulator (240) for accumulating and outputting the output signal of the multiplexer, a multiplexer (250) for selecting and outputting a lower pipeline carry storage cumulative output signal of the pipeline carry storage accumulator (240), and Top pipeline cache of pipeline carrystore accumulator (240) Pipeline bit sequential adder 270 for bit sequential addition of a restoring cumulative output signal and the output signal of the multiplexer 250, and a pipe for adding and subtracting the output signal of the pipeline bit sequential adder 260, respectively. A forward / reverse operation selector for selecting and outputting a line bit sequential adder 270, an output signal of the pipeline bit sequential adder 270, and an output signal of the pipeline bit sequential adder 260 according to the forward / reverse operation modes. An 8x8 two-dimensional discrete cosine transform / inverse transform processing apparatus using pipeline distributed arithmetic, characterized in that consisting of (280). 4. The lookup table 230 is characterized by sixteen l2 input lookup tables (dx + dy, dx + dy, bx + fy, -fx-by, -dx-dy, -dx + dy, fx-by, bx-fy, ax + cy, ex + gy). , cx-gy, -ax-ey, ex-ay, gx + cy, gx-ey, cx + ay), and the forward / reverse motion selector 220 in the forward / reverse motion selector 220 according to the forward / reverse operation mode. ) Is added to the lookup table 230 and the result of the pipeline carry storage accumulator that accumulates the divided values is selectively added through the multiplexer 250 so that the same lookup table can be used for the forward and inverse transforms. An 8 × 8 two-dimensional discrete cosine transform / inverse transform processing apparatus using a distributed pipeline operation. According to claim 3, The four data (D ₀ ~ D ₃ ) by dividing the four by the address of the lookup table 230 (230 ') and the output signal of the lookup table 230 (230') Pipeline carry storage accumulator (240) (240 ') and the output signal of the pipeline carry storage accumulator (240) (240'), which are bit-sequentially added to the binary system by performing a cumulative operation. An 8x8 two-dimensional discrete cosine transform / inverse transform processing apparatus using pipeline distributed computing, characterized in that a pipeline carry storage type divisional dispersion processing unit is configured to have multiple inputs and outputs with a sequential adder (260). The carry carry accumulator 240 according to claim 5, wherein the pipeline carry storage accumulator 240 performs 16 operations of accumulating 16 bits of signals S ₀ to S ₁₅ outputted from the lookup table 230 for 8 cycles. And a two-stage pipeline carry storage accumulator configured as a processor 241, and a two-stage pipeline carry storage accumulator for performing the conversion operation after selecting the output signal of the first stage pipeline carry storage accumulator. 8 × 8 2D Discrete Cosine Transform / Inverse Transformation Processor Using Pipeline Distributed Operations. 6. The pipeline bit sequential adder 260 bit-sequences the output signals AS ₁₁ and AS ₁₂ and BS ₁₁ and BSA ₁₂ of the pipeline carry storage accumulator 240 and 240 '. A first pipeline bit sequential adder, output signals AS ₂₁ , AS ₂₂ , BS ₂₁ , BS ₂₂ , and the first pipeline bits of the pipeline carry storage accumulator 240, 240 ′. An 8x8 two-dimensional discrete cosine transform / inverse transform processing apparatus using a pipeline distributed arithmetic unit, characterized in that it comprises a second pipeline bit sequential adder that adds a carry output signal (C ₁₂ ) output from the sequential adder bitwise. According to claim 1, The two-bit parallel bit sequential matrix converter 300, each of the even-bit sequential data (X _0e ~ X _7e ) output from the one-dimensional transform unit 200 of the horizontal two-stage pipeline structure, respectively The order of two bits is changed from first to third stages and output as even-bit matrix transformation output data (T _0e to T _7e ) and output from the one-dimensional transformation unit 200 of the lateral two-stage pipeline structure. To _convert the odd bit sequential data (X _0e to X _7e ) into the odd bit matrix conversion output data (T _0e to T _7e ) by changing their order from the first step to the third step by two bits. 8x8 two-dimensional discrete cosine transform / inverse transform processing apparatus using pipeline distributed computation.