KR19980073563A - Discrete Cosine Transform and Inverse Transform Processor - Google Patents

Abstract

The present invention relates to a design technique of a DCT / IDCT processor of a distributed computing method. In a conventional processor, a DCT ROM and an IDCT ROM are used separately, and a large number of full adders are used to increase the size of hardware. But there was a lot of power consumption defects.

Therefore, in order to solve this problem, the present invention addresses a 2-bit pre-adder so that four 2-bit operands can be added to the butterfly block for the DCT mode of the preprocessor, and alternately by adding a full adder for IDCT in the post-processor. By the normal switching, the addition / subtraction of the determinant is performed sequentially.

Description

Discrete Cosine Transform and Inverse Transform Processor

The present invention relates to a design technology of a distributed computational DCT (DCT) Discrete Cosine Transform (DCT) / IDCT (IDCT) processor, and more particularly, to implement a DCT / IDCT determinant in implementing a large scale integrated circuit (VLSI) processor. Discrete cosine transform and inverse transform processor to share ROM with transform and reduce number of adders.

DCT is widely used today as a standard for image compression technologies such as JPEG, MPEG1, MPEG2, and HDTV, because of its high compression efficiency, high speed algorithm, and easy hardware implementation.

Two-dimensional DCT is a transformation from a two-dimensional pixel matrix to a two-dimensional spatial frequency coefficient matrix, where the transformed matrix contains many zero or near zero values in high frequency space. In addition, the transformed coefficient matrix is quantized using human visual characteristics of spatial frequency and transmitted by performing Run-Length Coding (HLC) and Huffman encoding for the elimination of contiguous zero values and compressed expression. Done. In this case, since the bit rate and the reproduced image quality conflict with each other according to the degree of quantization, an optimal value is selected according to an application field.

Many algorithms have been proposed to reduce the complexity of 2D DCT / IDCT operation and to increase the operation speed. Basically, they are largely divided into RCM (Row-Column Method) and NRCM (Not-Row-Column Method). However, since the NRCM has a complicated hardware implementation, RCM is mainly used.

In the RCM, the two-dimensional DCT / IDCT is typically configured as shown in FIG. 1 so that one-dimensional row (or column) DCT / IDCT is performed in the one-dimensional cosine transform / inverse transform unit 1 of the front end and the matrix transform unit 2 ), Matrix transformation is performed, and column (or row) DCT / IDCT is performed in the one-dimensional cosine transform / inverse transform unit 3 at the rear stage.

As a method of implementing 2D DCT / IDCT of FIG. 1, there are a method of implementing a multiplier and a method of implementing a distributed arithmetic structure. However, the multiplier implementation has a problem in that the hardware scales up when the speedup operation is required, and the concept of pipeline and parallel processing is introduced in a distributed arithmetic scheme that performs multiplication operations using ROMs, accumulators, and shifters. Area and high-throughput VLSI is being implemented.

The definition of 8x8 two-dimensional DCT and IDCT is as follows.

From this, 8 × 1 one-dimensional DCT and IDCT are separated as follows.

The above equation may be expressed by the following 4 × 4 determinant using the symmetry characteristic of the cosine coefficient.

In the case of implementing a one-dimensional DCT in hardware based on the DCT equation, a general hardware block includes a preprocessing unit that adds / subtracts large input data, multiplies the cosine coefficient by the output of the preprocessor, and adds the multiplication. It consists of an adder. In addition, when a one-dimensional IDCT is implemented in hardware based on an IDCT equation, its general hardware block includes a multiplier / adder for multiplying and adding input data and cosine coefficients, and a post-processing unit for adding / subtracting the result.

In this case, if the multiplication / addition function is implemented as a multiplier, the hardware scales and the high-speed operation is difficult. Therefore, the distributed operation method is used. The principle is as follows, and the N-bit 2's complement code is expressed as follows. .

Thus, matrix multiplication is a precomputed partial product. Is stored in the ROM in advance, and partial reads from the ROM are sequentially performed and accumulated using the input vector as an address. However, according to chen's high-speed algorithm, 64 ROMs and 32 adders are required.

FIG. 2 is a block diagram illustrating a general hardware block diagram of one-dimensional DCT / IDCT, and FIG. 3 is a detailed block diagram of a unit calculator of the main processor 20 performing a distributed operation in FIG. 2. In FIG. 2, the word shifters 11A-11H, the bit shifters 12A-12H, and the butterfly 13 are components of the preprocessor 10 and receive 8 input data in series and output 2 bits in parallel at the same time. . In the DCT mode, the butterfly 13 adds / subtracts 2 bits. In the IDCT mode, the ROMs 21A-21H are immediately addressed.

The ROMs 21A-21H and the accumulators 22A-22H perform multiplication operations in a distributed operation method as components of the main processor 20, and the remaining blocks are output in parallel as components of the post processor 30. After latching the accumulator results 22A-22H, the accumulator 22A-22H is sequentially output through the rounding circuit 36. Here, in the case of IDCT, the addition / subtraction is controlled in the correct order.

However, according to chen's fast algorithm, 8 × 1 one-dimensional DCT / IDCT is implemented by matrix multiplication of two 4 × 4 matrices and 4 × 1 input vectors, respectively.

However, in the discrete cosine conversion and inverse conversion processor according to the prior art, the ROM for the DCT and the ROM for the IDCT are used separately, and a large number of full adders are used, resulting in a large hardware and a large power consumption.

Accordingly, an aspect of the present invention is to provide a discrete cosine transform and inverse transform processor having a ROM capable of sharing a ROM for DCT and an ROM for IDCT, and reducing the number of full adders.

1 is a block diagram of a typical two dimensional DCT / IDCT processor.

2 is a general hardware block diagram of one-dimensional DCT / IDCT.

3 is a detailed block diagram of a unit calculating unit of a main processor of FIG. 2;

Figure 4 is an exemplary block diagram of a discrete cosine transform and inverse transform processor of the present invention.

5A is a detailed block diagram of an A-type ROM and an accumulator in the main processor of FIG. 4;

5B is a detailed block diagram of a B-type ROM and an accumulator in the main processor of FIG. 4.

* Description of the symbols for the main parts of the drawings *

110: preprocessing unit 111A-111H: word shifter

112A-112H: Beat Shifter 113: Butterfly

114,131A-131H, 135A, 135B: Multiplexer

120: main processor 121: ROM

121A-121H: ROM 122: Accumulation part

122A-122H: Accumulator 130: Post-processing unit

132A-132H: Registers 133A-133H: Switches

134A, 134B: Adder 136: Rounding part

4 is an exemplary block diagram illustrating an implementation of the discrete cosine transform and inverse transform processor according to the present invention. As shown in FIG. In order to add four 2bit operands to the butterfly block for the controller, a 2bit full adder is additionally added, and the ROM unit is added or subtracted by a predetermined bit (2bit) according to the mode (DCT / IDCT) or directly outputted. A preprocessor 110 for addressing 121; A main processor 120 configured to configure a DCT ROM and an IDCT ROM as a single ROM that can be shared, and perform multiplication operation in a distributed operation method by reducing the number of full adders; In addition to the full adder for the IDCT latching the output of the accumulator of the main processor 120 to perform the addition / subtraction of the determinant in sequence according to the alternating switching to the post-processing unit 130 to output by rounding If described in detail with reference to Figures 5a, 5b attached to the operation and effects of the present invention configured as described above are as follows.

An 8 × 1 first order DCT / IDCT definition can be expressed as a sum of 2 × 2 determinants from a 4 × 4 determinant, where the DCT and IDCT matrices are adjusted to be equal to the following equation.

If the above equation is implemented in hardware, the size of the ROM used is reduced from 32 16 word ROMs to 24 4 word ROMs. However, considering the circuit around the ROM, the effect is very small. It is not suitable because it is increased to 24 rather than 16.

Therefore, in order to improve the method of parallel processing by 2 bits by doubling the ROM and full adder for real time processing of the image signal in the related art, the ROM is addressed by combining the input vectors by 1 bit and combining the ROM by 2 bits. The size of the ROM increases from 24 four-words to twelve 16-words, but the total number of adders is reduced from 24 to twelve, reducing the overall footprint and power consumption. In other words, by converting the 2 × 2 determinant into a 2 × 4 determinant as follows, it is possible to process by 2 bits without adding a ROM or full adder, thereby reducing the installation area and power consumption.

DCT:

In the case of implementing the main processing unit 120, that is, the ROM unit 121 and the accumulator unit 122 corresponding to the dispersion operation unit based on the above equation, as shown in Figs. 4 and 5, 12 16-word ROMs and 12 full adders. Only possible. In this case, four 2-bit full adders are used in the preprocessing unit 110, and in the case of IDCT, one full adder (rombit + α) is additionally required, but it does not affect chip area as a whole.

That is, as can be seen from the above equation, when each input is simultaneously addressed by adjacent lower and upper 2 bits, the input vector becomes 2 × 1 to 4 × 1, and the matrix extends from 2 × 2 to 2 × 4. At this time, the upper bit should have a factor twice as large as the lower bit. Therefore, the process of adding the output of the upper bit ROM by adding the lower bit ROM and the upper bit ROM and shifting the lower bit ROM output to the right by 1 bit as one ROM address eliminates the need for a separate full adder. Power consumption is reduced. However, since DCT requires adding four input vectors before addressing the ROM, four more 2-bit adders are added to the preprocessing butterfly 113 structure, and one full adder is added to the postprocessing butterfly for IDCT. Compared to the overall improvement, it is not a big burden.

From the result of the DCT, In order to calculate the total adder that adds or subtracts the output of the accumulator as shown in FIG. 5A and the result adds or subtracts the result of the accumulator as shown in FIG. The overall operating principle of the present invention is similar to that of the prior art. However, the butterfly 113 for the DCT mode of the preprocessing unit 110 includes four 2bit full adders to add 2bit operands as shown in the determinant, and the IDCT in the main processing unit 120. A full adder was added for the mode, so that the addition and subtraction of the determinant was performed sequentially by alternating switching.

The accumulator for obtaining X0, X4, X2 and X6 in the DCT result formula is composed of one full adder 152 and a register 153 as shown in FIG. 5A, and for obtaining X1, X5, X3 and X7. The accumulator is composed of two full adders 163 and 164 and a register 165 since the process of adding the two ROMs 161 and 162 and accumulating the results as shown in FIG. 5B is necessary.

When the principle of the present invention is applied to a two-dimensional DCT / IDCT processor, the number of ROMs can be reduced from 64 to 24, and the number of full adders (rombit length + α) can be reduced from 32 to 26, respectively. have.

As described in detail above, in the present invention, in implementing a discrete cosine transform and inverse transform processor, a single ROM capable of sharing the ROM for the DCT and the ROM for the IDCT may be configured, and the amount of installed area of the chip may be reduced by reducing the number of full adders. It is expected to reduce the power consumption and reduce the power consumption.

Claims (2)

In converting and outputting serial input data of a predetermined unit in parallel, a full adder is further provided to add a predetermined operand to a butterfly block for the DCT mode, and added by predetermined bits according to the mode (DCT / IDCT). A preprocessing unit 110 for addressing the next ROM unit 121 in a manner of performing / subtracting or directly outputting; The DCT ROM and IDCT ROM are configured as a single shareable ROM, and the DCT ROM and IDCT ROM are configured as a single shareable ROM using the determinant characteristics according to the alternating switching, and the multiplication operation is performed by distributed operation. A main processor 120; It is characterized in that it comprises a post-processing unit 130 further comprises a full adder for IDCT latching the accumulator output of the main processing unit 120 and sequentially performing the addition / subtraction of the determinant according to the alternate switching. Discrete cosine transform and inverse transform processor. The method of claim 1, wherein the main processor 120 includes upper and lower bit ROMs to reduce the number of ROMs and full adders, and shifts the lower bit ROM outputs to the right by one bit to add the outputs of the upper bit ROMs. A discrete cosine transform and inverse transform processor, comprising a circuit configured to process a process into one ROM address.