JP3103913B2 - Barrel shifter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a barrel shifter,
For example, the present invention relates to a barrel shifter used for a decoding device that decodes variable-length encoded data.

[0002]

2. Description of the Related Art A barrel shifter shifts input data by a desired number of bits by one operation. For example, a barrel of a computer or a decoder for decoding variable-length encoded data. Used for equipment.

[0003] Specifically, for example, there are eight inputs and eight outputs.
The barrel shifter that shifts to the upper bit side is shown in FIG.
As shown, all bits (b₀~ B₇, B₇
Selects 1 bit from MSB (Most Significant Bit)
Selector circuit 110 and the bit b₀~ B₆7 bit
A selector circuit 120 for selecting one bit from the
B₀~ B_FiveSelect to select 1 bit from 6 bits of
Circuit 130 and bit b₀~ B_Four5 bits to 1 bit
A selector circuit 140 for selecting a bit and a bit b ₀~ B
_ThreeSelector circuit 15 for selecting one bit from the four bits of
0 and bit b₀~ B_TwoSelect 1 bit from 3 bits of
Selector circuit 160, and bit b₀~ B₁2 bits
A selector circuit 170 for selecting one bit from the
B₀And a selector circuit 180 for selecting
The selector circuits 110 to 180 control the shift amount.
Control signal S₀~ S_TwoAnd the control signal S₀~ S
_TwoWith the control signal S₀Is the LSB of a 3-bit binary number
For each bit, this barrel shifter
Is 000, for example, no bit shift (0 bit
Shift), 001 shifts 1 bit, and 010
Is shifted by 2 bits, and similarly in the case of 111, 7
Bit shift is performed.

[0004]

By the way, like the above selector circuits 110 to 180, a multi-input one-output selector circuit is configured by connecting two-input one-output selectors in multiple stages. For example, as shown in FIG. 7 described above, the selector circuit 110 includes four selectors 1 at the first stage for switching and selecting adjacent bits among the 8 bits (b _{0 to} b ₇ ).
11 to 114 and two selectors 11 of the second stage for switching and selecting each output of the adjacent selector of the first stage.
5 and 116, and one selector 117 at the third stage for switching and selecting each output of the selector at the second stage. Select the second stage selector 11
At 5 and 116, two bits are selected from the four bits selected at the first stage, and the third selector 117 selects one bit from the two bits selected at the second stage. .

Further, for example, the selector circuit 120
As shown in FIG. 7 of FIG. ₀~ B₆) Of
Four cells in the first stage for switching and selecting adjacent bits
And selectors adjacent to the first stage.
Select two outputs in the second stage to switch and select each output of the data
And the outputs of the second-stage selector.
One selector 127 at the third stage for switching selection
And the first-stage selectors 121 to 124
4 bits out of 7 bits, and the second stage selector
4 bits selected in the first stage in 125 and 126
And selects two bits, and sends it to the third-stage selector 127.
And select 1 bit from 2 bits selected in the second stage
It is supposed to. Note that one of the selectors 121
The input is connected to ground at bit Q₀~ Q
₇(Q₇Is the MSB) bit shift of the output data
This is because the empty bit generated by the above is set to 0.

Further, for example, the selector circuit 130
As shown in FIG. 7, 6 bits (b ₀~ B_Five) Of
The three first-stage cells for switching and selecting adjacent bits
And the selectors adjacent to the first stage.
Select two outputs in the second stage to switch and select each output of the data
And the outputs of the second-stage selector.
One selector 136 at the third stage for switching selection
And the first-stage selectors 131 to 133
To select 3 bits from 6 bits, and the second-stage selector
3 bits selected in the first stage in 134 and 135
, Two bits are selected, and the third-stage selector 136 selects
And select 1 bit from 2 bits selected in the second stage
It is supposed to.

That is, an 8-input / 1-output selector circuit 1
Numeral 10 is composed of seven 2-input / 1-output selectors.
The input one-output selector circuit 120 is composed of seven two-input one-output selectors, the six-input one-output selector circuit 130 is composed of six two-input one-output selectors,
Similarly, the selector circuits 140 to 180 are each composed of six, four, four, three, and three two-input one-output selectors. Therefore, this 8-input 8-output barrel shifter is composed of 40 2-input / 1-output selectors as shown in Table 1 below.

[0008]

[Table 1]

As shown in Table 1 above, for example, a 16-input / 16-output barrel shifter, a 32-input / 32-output barrel shifter, and a 64-input / 64-output barrel shifter have 152, 576, and 2208 2-input 1 barrels, respectively. It consists of an output selector.

Therefore, the conventional barrel shifter, for example, in the case of a so-called IC, when the number of input / output bits increases, 2
The number of selectors with one input and one output increases exponentially, and two inputs and one output
Considering that the output selector consists of four gates,
For example, a barrel shifter with 32 inputs and 32 outputs is 2304
(= 4 × 576) gate is required. That is, the number of gates that can be used by one IC is limited, and when the number of input / output bits increases, other circuits cannot be mounted at the same time, or it becomes difficult to implement an IC.

The present invention has been made in view of such circumstances, and can reduce the number of 2-input / 1-output selectors as compared with a conventional barrel shifter. It is an object of the present invention to provide a barrel shifter that can be mounted and that can operate at high speed.

[0012]

In order to solve the above-mentioned problems, a barrel shifter according to the present invention comprises M rows × N columns (M, N
Is an integer) two-input one-output selector SEL _ij (i = 1 to M, j = 1 to N, M ≦
2 ^N ), M input terminals DI _i for inputting data provided to the first column of selectors SEL _i1 , and M input terminals DI _i for outputting data provided to the Nth column of selectors SEL _iN output and terminal DO _i of a 2 ^j-1 inputs terminals T _kj respectively provided (k = 1~2 ^j-1) for each j row, the selector SEL _i1 in the first column, The selectors SEL _i1 for which i ≠ 1 are adjacent to the input terminals DI _i-1 and DI _i-1
The selector SEL _i1 with i = 1 switches and selects the bit of the data respectively input through _i.
11 via the signal input terminal DI ₁ inputted via the select switch the bits of the input data selector SEL _ij j-th row is j ≠ 1 is, i> is a 2 ^j-1 selector SEL _ij selects and switches the output of the selector SEL _{ij-1 in} the j-1st column and the output of the selector SEL _hj-1 (h = i-2 ^j-1 ), and the selector SEL _ij in which i ≦ 2 ^j-1 is _satisfied. Is the j
-1 column selector SEL _ij-1 output and input terminal T _kj (k
= I) switch and select the signal input via
The column selectors SEL _ij operate according to the same control signal, and output data obtained by bit-shifting the data input via the input terminal DI _i via the output terminal DO _i .

Further, the barrel shifter according to the present invention has a first
Enter the most significant bits or least significant bits of the input data to the input terminal T ₁₁ of the column, the input terminal T of the j-th column is _{j ≠ 1 kj (k = i} ) in the first j-1 column i ≧ M + 1- The output of the selector SEL _ij-1 which is 2 ^J is input.

[0014]

In the barrel shifter to which the present invention is applied, the selector SEL _i1 in the first column, i ≠ 1, switches and selects the bits of the data input via the input terminals DI _i-1 and DI _i adjacent to each other. and, a selector SEL _i1 is i = 1 of the first row, selects switches the bit data inputted through the signal input terminal DI ₁ inputted via the input terminal T _11, in j ≠ 1 The selector SEL _ij of a certain ^j- th column where i> 2 ^j−1 is used as the selector SEL _ij of the j-th column
The output of _{ij-1 and} the output of the selector SEL _hj-1 (h = i-2 ^j-1 ) are switched and selected, and i ≦ 2 of the j-th column where j ≠ 1.
^The selector SEL _{ij which} is j−1 switches and selects the output of the selector SEL _ij-1 of the j−1th column and the signal input through the input terminal T _kj (k = i), and selects the selector of each j column. SE
L _ij are operated by the same control signal, and the input terminals DI _i
The data obtained by bit-shifting the data inputted via the outputs through the output terminal DO _i.

[0015] In the barrel shifter according to the present invention, inputs the most significant bit or the least significant bit of the input data to the input terminal T ₁₁ of the first row, j ≠ 1 in which the input terminal T _kj of the j-th column ( In k = i), i ≧ M + 1-2 in the j−1th column
By inputting the output of the selector SEL _ij-1 which is ^J , the data obtained by cyclically shifting the input data is
Through the output terminal DO _i output.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the barrel shifter according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of a barrel shifter to which the present invention is applied, and FIG. 2 is a block diagram showing a circuit configuration of a receiving device of an image transmission system using the barrel shifter.

First, the above-mentioned receiving apparatus will be described.
As shown in FIG. 2, the receiving apparatus includes an error correction circuit 1 for performing error correction processing on received variable-length code data.
A variable-length decoding circuit (hereinafter referred to as IVLC) 10 for decoding the variable-length code data from the error correction circuit 1 to reproduce the code data, and inversely quantizing the code data from the IVLC 10 to output a DCT. An inverse quantization circuit 2 for reproducing data, and an inverse discrete cosine transform circuit (hereinafter referred to as IDCT) 3 for performing so-called inverse discrete cosine transformation of DCT output data from the inverse quantization circuit 2 to reproduce difference data between frames.
And an adder 4 for adding the difference data from the IDCT 3 to the image data of the previous frame to reproduce the image data of the current frame, and a frame for storing the image data from the adder 4 as the image data of the previous frame. It comprises a memory 5 and a digital / analog (hereinafter referred to as D / A) converter 6 for converting the image data from the adder 4 into an analog signal and reproducing a video signal.

Then, the video signal is converted into image data,
The difference between frames for each pixel (hereinafter referred to as difference data) is subjected to a discrete cosine transform, and variable-length code data obtained by variable-length coding is transmitted from a transmission device.
Variable length code data is received, and a video signal is reproduced from the received variable length code data.

Specifically, the error correction circuit 1 performs an error correction process on the received variable-length code data.

The IVLC 10 comprises a barrel shifter, a lead
For example, a variable length decoding circuit for decoding a so-called Huffman code provided with an only memory (hereinafter referred to as ROM) and the like, and a variable length of 2 to 18 bits continuously supplied from the error correction circuit 1, for example. The code data is bit-shifted by a barrel shifter so that the first bit of the variable-length code data is always the most significant bit (hereinafter referred to as MSB: Most Significant Bit), and the shifted variable-length code data is read into the ROM as a read address. Code data having a fixed length of, for example, 16 bits, which is stored in advance, is read, and variable-length code data is decoded.

The inverse quantization circuit 2 inversely quantizes the code data supplied from the IVLC 10 using a so-called quantization width at the time of transmission, and reproduces, for example, an 8 × 8 coefficient in the discrete cosine transform.

The IDCT 3 performs inverse discrete cosine transform of the coefficient supplied from the inverse quantization circuit 2 to reproduce difference data.

The adder 4 adds the difference data supplied from the IDCT 3 to the image data of the previous frame supplied from the frame memory 5, and reproduces the image data of the current frame.

The frame memory 5 stores the image data reproduced by the adder 4 and supplies it to the adder 4 as the image data of the previous frame.

The D / A converter 6 converts the image data supplied from the adder 4 into an analog signal and reproduces a video signal.

Next, a specific circuit configuration of the above-described IVLC 10 will be described. The IVLC 10 is, for example, shown in FIG.
As shown in (1), a buffer memory 11 for temporarily storing variable-length code data, a memory controller 12 for controlling the buffer memory 11, and a delay of the variable-length code data read from the buffer memory 11 by a predetermined number of bits. Delay units 13 and 14, a barrel shifter 15 for bit-shifting the variable-length code data delayed by the delay units 13 and 14 so that the leading bit becomes the MSB, and a variable length output from the barrel shifter 15 for each data. The code data is used as the read address and the RO storing the code data
M16, a synchronization signal detection circuit 17 for detecting a frame synchronization signal from the variable-length code data from the buffer memory 11, and a fixed shift amount generated based on the frame synchronization signal detected by the synchronization signal detection circuit 17. A fixed length shift amount generating circuit 18, a code length calculating circuit 19 for calculating the code length of the variable length code data output for each data from the barrel shifter 15, an output of the fixed length shift amount generating circuit 18, and a code length. A changeover switch 20 for switching and selecting an output of the arithmetic circuit 19; an adder 21 for obtaining a shift amount; and a delay unit 22 for delaying the output of the adder 21
Switch 2 for resetting the delay unit 22
3 is provided.

The buffer memory 11 temporarily stores the variable-length code data continuously supplied from the error correction circuit 1 shown in FIG. 2 as shown in FIG.
The stored variable-length code data is stored in the memory controller 12.
Under the control of, and supplies the read variable-length code data to the delay unit 13. That is,
A temporary difference in transmission speed occurs between the variable-length code data input to the IVLC 10 and the output code data, and the memory controller 12 controls the buffer memory 11 to absorb the difference.

Each of the delay units 13 and 14 is, for example, 16
Buffer memory 11
These variable-length code data are latched, and the latched variable-length code data is supplied to the barrel shifter 15 as 32-bit parallel data.

Here, the barrel shifter 15 will be described in detail. The M-input M-output barrel shifter to which the present invention is applied is a 2-input / 1-output selector SEL _ij (i = 1 to 1) arranged in a matrix of M rows × N columns (M and N are integers).
M, j = 1 to N, M ≦ 2 ^N ) and the selector SE in the first column
M input terminals DI _i for inputting data provided for L _i1 , M output terminals DO _i for outputting data provided for the N-th column selector SEL _iN , ^J-1 input terminals T provided respectively for
_kj (k = 1 to 2 ^j-1 ), and the selector SE in the first column
L _i1 is such that the selector SEL _i1 with i ≠ 1 switches and selects the bit of the data input via the adjacent input terminals DI _i-1 and DI _i , and the selector SEL _i1 with i = 1 _{receives the} input. via signal input through the terminal T ₁₁ and the input terminal DI ₁ select switches the bit of the input data of the j-th column is j ≠ 1 selector SEL _ij
Is that the selector SEL _ij with i> 2 ^j−1 is the output of the selector SEL _{ij-1 in} the j−1th column and the selector SEL _hj−1 (h =
i−2 ^j−1 ), and the selector SEL _{ij satisfying} i ≦ 2 ^j−1 is selected by the selector SEL _ij−1 of the j−1th column.
And the signal input via the input terminal T _kj (k = i) are switched and selected. The selectors SEL _ij of each j column operate by the same control signal and are input via the input terminal DI _i. the bit shifted data data, and outputs through the output terminal DO _i.

Specifically, for example, a barrel shifter which has eight inputs and eight outputs and shifts data consisting of eight bits of bits b _{0 to} b ₇ (b ₇ is MSB) to the upper bits is shown in FIG. 1, for example. Thus, 8 rows × 3 columns (M = 8, N
= 3) and two selectors SEL _ij (i = 1-8, j = 1-3) arranged in a matrix and selectors SEL ₁₁ -SEL _{81 in} the first column. and eight input terminals DI ₁ -DI ₈ for inputting data, a third column selectors SEL ₁₃ eight output terminals DO ₁ to DO ₈ to output the data provided for to SEL _83, first 1 provided for the column selector SEL ₁₁ (= 2 ^1-1 )
A number of input terminals T _11, a selector SEL ₁₂ of the second column, SE
Two (= 2 ^2-1 ) input terminals T ₁₂ , T ₂₂ provided for L ₂₂ and selectors SEL _{13 to} SE in the third column, respectively.
It has four (= 2 ^3-1 ) input terminals T _{13 to} T ₄₃ provided for the L ₄₃ , respectively.

Then, the selector S in the first column where i ≠ 1 is satisfied.
EL_{twenty one}Are input terminals DI adjacent to each other₁, DI_TwoThrough
Bit b input as₀And bit b₁Cut
Change and select the selector SEL₃₁Are the inputs adjacent to each other
Terminal DI_Two, DI_ThreeBits that are input via
b₁And bit b_TwoSwitch and select
Kuta SEL₄₁~ SEL₈₁Is the input terminal DI_ThreeOr
Bit b_TwoAnd input terminal DI_FourBit b from_Three, Enter
Force terminal DI_FourBit b from_ThreeAnd input terminal DI _Fivefrom
Bit b_Four, Input terminal DI_FiveBit b from_FourAnd input end
Child DI₆Bit b from_Five, Input terminal DI₆Bit from
B_FiveAnd input terminal DI₇Bit b from ₆, Input terminal D
I₇Bit b from₆And input terminal DI₈Bit b from
₇And the selector SEL where i = 1.
₁₁Is the input terminal T₁₁From the input terminal DI₁Through
Bit b input₀To select.

The selector SEL ₃₂ in the second column, i> 2 (= 2 ^2-1 ), outputs the output of the selector SEL _{31 in} the first column and the selector SEL ₁₁ (h = 3−2 ^2-1 = 1). ), The selector SEL ₄₂ switches the output of the selector SEL ₄₁ of the first column and the selector SEL ₂₁ (h = 4-2 ^2-1 =
2) The output is switched and selected.
EL ₅₂ to SEL _82, respectively, outputs of the selector SEL ₃₁ of the selector SEL _51, outputs of the selectors SEL ₄₁ of the selector SEL _61, outputs of the selector SEL ₅₁ of the selector SEL _71, and an output of the selector SEL ₈₁ The output of the selector SEL ₆₁ is switched and selected, and i ≦ 2 (= 2
The selector SEL ₁₂ is ^2-1), the selector S in the first column
The selector SEL ₂₂ switches and selects the output of the EL _{11 and} the signal input via the input terminal T ₁₁ (k = i = 1).
The output of the selector SEL _{21 in} the first column and the input terminal T ₂₂ (k =
i = 2) is switched and selected.

Then, each selector SEL in the first column₁₁~ S
EL₈₁Is the same control signal S₀Works by, for example
Control signal S₀Is 0, the input terminals DI₁~
DI ₈Select the bits supplied via
Control signal S₀When is 1, it
Each input terminal T₁₁And input terminal supplied via
DI₁~ DI₇Select the bits supplied via
That is, it is shifted by one bit to the upper bit side. In addition, input
Terminal T₁₁The signal supplied via is bit-shifted
Determine the value of the vacant bit that occurs when
For example, input terminal T ₁₁To ground and set its value to 0
0 is inserted into the empty bit, and the value is set to 1
Then, 1 is inserted into the empty bit.

Each of the selectors SEL in the second column₁₂~ SE
L₈₂Is the same control signal S₁Works by, for example,
Control signal S₁Is 0, the selector S of the first column is
EL ₁₁~ SEL₈₁Output, that is, the bit shift
Control signal S₁When is 1, input each
Terminal T₁₂, T_{twenty two}And the selector S
EL₁₁~ SEL₆₁Output, that is, a 2-bit serial
To shift. The input terminal T₁₂, T_{twenty two}Is supplied via
Is input terminal T described above.₁₁Signal supplied via
Similarly, if the value is 0, for example,
0 is inserted, and if the value is set to 1, 2 free bits
Is inserted into.

The third column selectors SEL _{13 to} SEL _13
83 is operated by the same control signal S _2, for example, when the control signal S ₂ is 0, the selector SE of each second column
When the output of L _{12 to} SEL ₈₂ is selected, that is, the bit shift is not performed and the control signal S ₂ is 1, the signal supplied via the input terminals T _{13 to} T ₄₃ and the selector SE
The outputs of L _{12 to} SEL ₄₂ are selected, that is, shifted by 4 bits. The signal supplied through the input terminal T ₁₃ through T _43, similar to the signal supplied through the input terminal T ₁₁ of the above, for example, its value is 0, the empty 4 bits 0
Is inserted, and conversely, 1 is added to the empty 4 bits whose value is 1.
Is inserted.

Thus, when the control signals S _{0 to} S ₂ are made to correspond to each bit of a 3-bit binary number with the control signal S ₀ being the LSB, the barrel shifter having eight inputs and eight outputs will have input terminals DI _{1 to} DI _The data input through ₈ is shifted to the upper bit side. If the value is, for example, 000, no bit shift is performed (0 bit shift), if it is 001, one bit is shifted, if 010, two bits are shifted. Similarly, 1
In the case of 11, it shifts by 7 bits. Then, the bits Q _{0 to} Q ₇ (Q ₇ is M
SB) are output via output terminals DO _{1 to} DO ₈ , respectively.

By the way, this 8-input / 8-output barrel shifter
Data, each bit of the input data (b ₀~ B₇)
Input terminal DI in order from the MSB₁~ DI
₈Input in response to
Do the shift.

For example, a 16-input 16-output barrel system
The lid, 32 input and 32 output barrel shifter, etc.
This is realized by expanding the barrel shifter with 8 inputs and 8 outputs.
Can be That is, for example, 16 inputs and 16 outputs
Barrel shifters are arranged in a matrix of 16 rows x 4 columns
2 input 1 output selector SEL_ij(I = 1 to 1
6, j = 1 to 4) and the selector SEL in the first column₁₁~ SE
L_{(16) 1}Enter the data provided for the 16
Input terminal DI₁~ DI₁₆And the selector SEL in the fourth column₁₄
~ SEL_{(16) 4}Output data provided for
6 output terminals DO₁~ DO₁₆And the selector S in the first column
EL₁₁One input terminal T provided for₁₁And the second
Column selector SEL₁₂, SEL_{twenty two}Provided for each
Two input terminals T₁₂, T_{twenty two}And the third column selector
SEL₁₃~ SEL₄₃The four
Input terminal T₁₃~ T₄₃And the selector SEL in the fourth column₁₄~ S
EL ₈₄Input terminals T provided respectively for₁₄
~ T₈₄And

Also, for example, a barrel input of 32 inputs and 32 outputs
The lids are arranged in a matrix of 32 rows × 5 columns.
Input 1 output selector SEL_ij(I = 1 to 32, j = 1
5) and the first column of selectors SEL₁₁~ SEL_{(32) 1}To
32 input terminals D for inputting data provided for
I₁~ DI₃₂And the fifth column selector SEL₁₅~ SEL
_{(32) 5}32 outputs that output the data provided for
Force terminal DO₁~ DO₃₂And the selector SEL in the first column₁₁To
One input terminal T provided for₁₁And the second column
Kuta SEL₁₂, SEL_{twenty two}2 provided for each
Input terminals T₁₂, T_{twenty two}And the third column selector SEL₁₃
~ SEL₄₃Input terminals provided for each
T₁₃~ T₄₃And the selector SEL in the fourth column₁₄~ SEL₈₄To
Eight input terminals T provided for each₁₄~ T
₈₄And the fifth column selector SEL₁₅~ SEL_{(16) 5}Against
16 input terminals T provided respectively.₁₅~ T_{(16) 5}
And

That is, the 8-input / 8-output barrel shifter can be constituted by 24 (= 8 × 3) 2-input / 1-output selectors, and the 16-input / 16-output barrel shifter is 64
(= 16 × 4) two-input / one-output selectors, and a 32-input / 32-output barrel shifter is 160
(= 32 × 5) two-input / one-output selectors. In other words, the barrel shifter to which the present invention is applied can greatly reduce the number of 2-input / 1-output selectors as compared with the conventional barrel shifter as shown in Table 1 above. Furthermore, the effect increases as the number of inputs and outputs increases. As a result, other circuits can be simultaneously mounted in a so-called integrated circuit, and high-speed operation can be performed.

The barrel shifter 15 is a 32-input, 32-output barrel shifter having the above-described configuration, and converts the variable-length code data based on the shift amount supplied from the delay unit 22 such that the MSB whose first bit is always output is provided. Bit shift so that

More specifically, the synchronization signal detection circuit 17 detects a frame synchronization signal from the variable-length code data read in 16-bit units from the buffer memory 11 and, for example, as shown in FIG. In the stage # 1, which is one shift operation period, for example, a trigger signal that is at a high level (hereinafter, referred to as an H level) is supplied to the fixed-length shift amount generation circuit 18,
As shown in B and C, a switching control signal which becomes H level in the stages # 2 to # 4 following the stage # 1 in which the frame synchronization signal is detected is supplied to the changeover switch 20, and becomes H level in the stage # 2. The switch control signal is supplied to the switch 23.

The fixed-length shift amount generating circuit 18 receives one signal based on the trigger signal supplied from the synchronization signal detecting circuit 17.
A frame synchronization signal consisting of 6 bits (FS shown in FIG. 4)
W) and predetermined data consisting of 8 bits and 4 bits following the FSW (FLC1, FLC shown in FIG. 4).
2) 16 bits, 8 which is a fixed length shift amount with respect to
Bits, 4 bits, as shown in FIG.
It occurs in each of the stages # 2 to # 4.

On the other hand, the code length calculation circuit 19 calculates a shift amount in which the first bit of the next variable length code data is MSB based on the current variable length code data output from the barrel shifter 15, that is, For example, the bit length from the MSB of the 32-bit output of the barrel shifter 15 to the bit conforming to the Huffman coding rule is detected, and the bit length is used as a shift amount via the changeover switch 20 via the adder 21
To supply.

More specifically, as shown in FIG. 5E, in stage # 1, variable-length code data VLC1 (see FIG. 4) consisting of 6 bits is shifted from barrel shifter 15 so that the first bit is MSB. 6 bits when supplied, and 14-bit variable-length code data VLC2 in stage # 5 is shifted and supplied so that the first bit is MSB.
In the stage # 6, the variable-length code data VLC6 consisting of 10 bits
10 bits are output when the data is supplied after being shifted so that

The changeover switch 20 is provided for the synchronization signal detection circuit 1
7 operates on the basis of the switching control signal supplied from the switching control signal 7. When the switching control signal is at the H level, the shift amount from the fixed length shift amount generating circuit 18 is selected. The shift amount from the length calculation circuit 19 is selected, and the selected shift amount is supplied to the adder 21. Therefore, from the changeover switch 20, as shown in FIG. 5F, in each of the stages # 1 to # 7, 6 bits,
A shift amount of 16 bits, 8 bits, 4 bits, 14 bits, 10 bits, and 18 bits is output.

The adder 21 is composed of, for example, a hexadecimal adder, and calculates the shift amount supplied through the changeover switch 20 and the shift amount of the current stage supplied from the delay unit 22 through the changeover switch 23. Addition is performed to determine the shift amount in the next stage. Specifically, as shown in FIG. 5H, in stage # 1, 6 bits supplied through the changeover switch 20 and 10 bits (shown in FIG. 5G) supplied through the changeover switch 23 are added. , 0 (= 16−
16) Find bits. In stage # 2, 16 bits supplied via the changeover switch 20 and 0 bit when the changeover switch 23 selects the ground side are added to obtain 0 (= 16-16) bits. In stage # 3, 8 bits supplied via the changeover switch 20 and 0 bits supplied via the changeover switch 23 are added to obtain 8 bits. Similarly,
In stage # 4, 4 bits and 8 bits are added and 1
Find 2 bits. In stage # 5, 14 bits and 12 bits are added to obtain 10 (= 26−16) bits. In stage # 6, 10 bits and 1
By adding 0 bits, 4 (= 20-16) bits are obtained. In stage # 7, 18 bits and 4 bits are added to obtain 6 (= 22−16) bits. Then, the adder 21 supplies the shift amount thus obtained to the delay unit 22.

The delay unit 22 uses the shift amount from the adder 21 as the shift amount in the next stage,
And to the adder 21 via the changeover switch 23.

The barrel shifter 15 includes a delay unit 22
From the control signal S ₀, S₁···When
Supplied from the delay units 13 and 14 as parallel data.
Variable-length code data, frame synchronization signals, etc.
To shift. As a result, from the barrel shifter 15, the variable length
The first bit of code data is always MSB
And output after bit shifting.

A table for decoding, for example, Huffman codes is stored in the ROM 16 in advance.
Reference numeral 16 designates, as a read address, variable-length code data bit-shifted so that the first bit supplied from the barrel shifter 15 becomes the MSB, reads out the code data obtained by decoding the variable-length code data, and To the inverse quantization circuit 2 shown in FIG. Then, as described above, in the inverse quantization circuit 2 to the D / A converter 6, processing such as inverse quantization and inverse discrete cosine transform is performed on the code data, and the video signal is reproduced.

Next, a so-called cyclic type barrel to which the present invention is applied.
The shifter will be described. This cyclic barrel shifter
Has a circuit equivalent to the barrel shifter described above,
The circuit connection is different. That is, traveling
Type barrel shifter has a first row of input terminals T₁₁Input data
Input the most significant bit or least significant bit of
Input terminal T of the j-th column_kj(K = i) in the j-1st column
i ≧ M + 1-2 ^JSelector SEL_ij-1Input
It is designed to help.

More specifically, for example, a cyclic barrel shifter having eight inputs and eight outputs and shifting to the upper bit side is as follows.
As shown in FIG. 6, enter the MSB of the input data to the input terminal T ₁₁ of the first row, the selector SEL _71, each output of the selector SEL ₈₁ and input to the input terminal T _12, T ₂₂ in the second column The selector SEL _{52 is connected} to the input terminals T _{13 to} T ₄₃ in the third column.
To SEL ₈₂ are respectively input. Then, for example, when shifting by 3 bits, the upper 3 bits pushed out as a result of the shifting are sequentially inserted into the vacated lower 3 bits to perform a cyclic bit shift. Note that the same circuits as those shown in FIG. 1 described above are denoted by the same reference numerals, and description thereof will be omitted.

Therefore, the cyclic type barrel shifter can greatly reduce the number of 2-input / 1-output selectors as compared with the conventional cyclic type barrel shifter. And high-speed operation can be realized.

It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that the present invention can be applied to, for example, a barrel shifter used for a multiplier of an electronic computer.

[0055]

As is clear from the above description, the present invention
Is M rows × N columns (M and N are integers).
Two-input one-output selector S arranged in a matrix
EL_ij(I = 1 to M, j = 1 to N, M ≦ 2^N) And the first
Column selector SEL_i1Enter the data provided for
M input terminals DI_iAnd the N-th column selector SEL
_iNM output terminals for outputting data provided for
DO_iAnd 2 provided for each j column, respectively.^j-1Pieces
Input terminal T_kj(K = 1 ~ 2^j-1) And the first row
Selector SEL_i1Is a selector SEL for which i ≠ 1_i1But
Input terminals DI adjacent to each other_i-1, DI_iThrough it
The input data bits are switched and selected, and i =
Selector SEL that is 1_i1Is the input terminal T₁₁Input via
Signal and input terminal DI₁Data entered via
Of the j-th column where j ≠ 1.
Kuta SEL_ijIs i> 2^j-1Selector SEL_ijBut
J-1st column selector SEL_ij-1Output and selector SE
L_hj-1(H = i-2^j-1), And select the output.
≦ 2^j-1Selector SEL_ijIs the j-1st select
TA SEL_ij-1Output and input terminal T_kjVia (k = i)
The input signal is switched and selected, and the selector S of each j column is selected.
EL_ijAre operated by the same control signal, and the input terminal DI
_iBit-shifted data input through
To the output terminal DO_iTo output via
As compared with the conventional barrel shifter, the two-input one-output
Can greatly reduce the number of
Other circuits can be mounted at the same time,
Operation can be enabled.

Further, the barrel shifter according to the present invention has a first
Enter the most significant bits or least significant bits of the input data to the input terminal T ₁₁ of the column, the input terminal T of the j-th column is _{j ≠ 1 kj (k = i} ) in the first j-1 column i ≧ M + 1- receives an output of the selector SEL _ij-1 is 2 ^J, by input data cyclically via the output terminal DO _i bit shifted data so as to output, as compared with the conventional recursive barrel shifter The number of two-input, one-output selectors can be greatly reduced. For example, other circuits can be mounted simultaneously in an integrated circuit, and high-speed operation can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a barrel shifter to which the present invention is applied.

FIG. 2 is a block diagram showing a circuit configuration of a receiving device using the barrel shifter.

FIG. 3 is a block diagram showing a specific circuit configuration of an IVLC constituting the receiving device.

FIG. 4 is a diagram schematically showing variable-length code data input to the IVLC.

FIG. 5 is a time chart for explaining the operation of the IVLC.

FIG. 6 is a block diagram showing a circuit configuration of a cyclic barrel shifter to which the present invention is applied.

FIG. 7 is a block diagram showing a circuit configuration of a conventional barrel shifter.

[Explanation of symbols]

SEL _ij・ ・ ・ Selector DI _i・ ・ ・ Input terminal DO _i・ ・ ・ Output terminal T _kj・ ・ ・ Input terminal

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 7/40 G06F 7/00

Claims (2)

(57) [Claims] 1. A matrix of M rows × N columns (M and N are integers).
2-input / 1-output selector SEL arranged in a matrix
_ij(I = 1 to M, j = 1 to N, M ≦ 2^N) And the first column of selectors SEL_i1The data provided for
M input terminals DI for input_iAnd the selector SEL in the Nth column_iNThe data provided for
M output terminals DO for output_iAnd 2 provided for each j column^j-1Input terminals
T_kj(K = 1 ~ 2^j-1), The first column of selectors SEL_i1Is a selector S for which i ≠ 1
EL_i1Are the input terminals DI adjacent to each other._i-1, DI_i
Switches the bits of the data input via
Selector SEL with i = 1_i1Is the above input terminal
T₁₁And the input terminal DI₁Through
And selects the bits of the data to be input, and the selector SEL in the j-th column where j 1_ijIs i> 2^j-1
Selector SEL _ijIs the selector SEL in the j-1st column
_ij-1Output and selector SEL_hj-1(H = i-2 ^j-1)of
Select output switching, i ≦ 2^j-1Selector SE
L_ijIs the selector SEL in the j-1st column_ij-1Output and input
Force terminal T_kjSwitch the signal input via (k = i)
And the selector SEL of each j column_ijAre driven by the same control signal.
Input terminal DI_iData entered via
The bit-shifted data is output to the output terminal DO. _iThrough
A barrel shifter characterized in that the output is performed. 2. An input terminal T in a first column.₁₁At the top of the input data
Input the least significant bit or the least significant bit, and input terminal T of the j-th column where j 1_kj(K = i) is the j-th
One row of i ≧ M + 1-2 ^JSelector SEL_ij-1Out of
The barrel system according to claim 1, wherein a force is input.
lid.