JP3622473B2 - Variable length code decoding device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for rapidly decoding a code encoded by an encoding method using a variable length code and additional information added thereto, and in particular, a multi-order such as a JPEG (Joint Photographic Experts Group) method. The present invention can be applied as a device that decodes a Huffman code in a video encoding system at high speed.
[0002]
[Prior art]
In a multi-tone image encoding method such as the JPEG method, an image is divided into blocks of 8 × 8 pixels, for example, and the following operations are performed.
[0003]
(1) The pixel value of the block is converted into 64 DCT coefficients by two-dimensional discrete cosine transform (DCT).
{Circle around (2)} The 64 DCT coefficients are quantized in the quantization step possessed by the quantization table.
(3) One of the 64 quantized DCT coefficients takes a difference from the DC coefficient of the previous block, and the difference is variable-length encoded by a Huffman code, and a variable length is added if necessary. An information bit is added after the variable length code to obtain a code bit string.
(4) 63 AC coefficients out of 64 quantized DCT coefficients are arranged in a zigzag scan order, and the number of consecutive zeros in this array and the value of the next nonzero coefficient are taken as a set. A code bit string is obtained by performing variable length coding and adding variable length additional information bits after the variable length code as necessary.
[0004]
The decoding apparatus restores the image by following the encoding process in reverse.
[0005]
For example, Japanese Patent Laid-Open Nos. 4-133522, 3-247020, 4-23521, and 5-63586 are disclosed as apparatuses for decoding codes encoded by the above-described encoding method. JP-A-9-130265 and JP-A-9-130266.
[0006]
FIG. 11 is a diagram for explaining these conventional decoding apparatuses. In FIG. 11, 11 and 12 are latches for holding an input code bit string, 13 is a barrel shifter, 14 is a conversion circuit, and 15 is data for the subsequent stage. An output latch for temporarily holding, an accumulation circuit 16, and an EOB detection latch 17 for temporarily holding EOB detection data.
[0007]
The code bit string is composed of a variable length code (Huffman code) followed by additional bits, and the variable length code represents a bit length of the additional bits or a combination of a bit length and a run length of zero. The conversion circuit 14 decodes the variable length code of the code bit string, generates the bit length of the variable length code, the bit length of the additional bits, the run length of zero, etc., and takes out the desired data through the latch 15 and the subsequent additional bits To send to the department. The accumulator circuit 16 knows the total bit length of the variable length code and additional bits from the conversion circuit 14, and controls the shift of the barrel shifter 13 and the latch. Further, the EOB detection latch 17 notifies that the next DC coefficient comes upon detection of EOB.
[0008]
That is, in the conventional configuration, a plurality of registers or latches 11 and 12 for holding a plurality of bits in a code bit string are provided, and a valid bit string necessary for decoding is selected from a code bit string held in the register by a selector or barrel shifter 13. Use to remove. Then, this effective bit string is input to the conversion circuit 14 constituted by ROM or PLA, and a part of the output of the conversion circuit 14 is output as decoded data. The other part of the output of the conversion circuit 14 is used to control the updating of the contents of the registers 11 and 12 and the extraction of the next valid bit string by the selector 13, and the other part of the output of the conversion circuit 14 is used. Thus, extraction of additional information bits added after the variable length code is controlled.
[0009]
By the way, in the decoding of the code by the above multi-tone image coding method, it is necessary to use different conversion circuits for the decoding of the variable length code of the DC coefficient and the decoding of the variable length code of the AC coefficient. The decoding device cannot properly use the conversion circuit properly. In the decoding circuit disclosed in Japanese Patent Laid-Open No. 4-133522, the conversion circuit is switched by detecting an EOB (End of Block) code in the code string. However, when the 63rd AC coefficient is non-zero Since the EOB code is not output at the end of the block, switching cannot be performed correctly.
[0010]
Also, the decoded data output from the variable length code decoding device is input to the next-stage inverse quantization device, which outputs information indicating what number of DCT coefficients the currently output decoded data is. Therefore, it is necessary to manage a quantization table used for inverse quantization in the inverse quantization apparatus.
[0011]
[Problems to be solved by the invention]
The present invention has been made in view of the above circumstances, and an object of the present invention is to make it possible to easily and reliably distinguish between a variable length code of an AC coefficient and a variable length code of a DC coefficient.
[0012]
[Means for Solving the Problems]
The variable length code decoding apparatus according to the present invention includes a first register for holding a code bit string input in parallel with a plurality of bits, and a new code bit string written to the first register until then. A second register for holding the code bit string held in the first register, a selector for taking out the code bit string to be decoded from the code bit strings held in the first and second registers, and With the code bit string as input, the decoded data, the code length of the variable length code, the bit length of the variable length additional information bit, the code length of the variable length code and the bit length of the variable length additional information bit are added. The conversion circuit to output and the decoded code length output from the conversion circuit are used to update the contents of the first and second registers, and the position to extract the code bit string to be decoded next is selected. And a control circuit that requests a new code bit string from the preceding apparatus outputting the code to the apparatus, a zero run length of the AC coefficient included in the decoded data, and an EOB (End of Block) code The DCT coefficient position register for managing the DCT coefficient currently decoded in the block using the DCT coefficient position register, the DCT coefficient position register using the output of the DCT coefficient position register and the DC coefficient conversion circuit A device for switching the conversion circuit, and a register for outputting the output of the selector, the output of the conversion circuit, and the output of the DCT coefficient position register to the subsequent device.
[0013]
By configuring the decoding device as described above, one variable length code can always be interpreted and decoded in one clock cycle, and the decoding speed can be guaranteed. Further, additional information bits added to the variable length code can be easily taken out by a circuit in the next stage. Further, by providing the DCT coefficient position register, the DC coefficient conversion circuit and the AC coefficient conversion circuit can be appropriately switched. Furthermore, since the output of the DCT coefficient position register is output to the subsequent circuit, the inverse quantization circuit can easily obtain the required quantization step value from the quantization table using this value.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Examples of the present invention will be described below.
[0015]
FIG. 1 shows the overall configuration of a variable-length decoding apparatus (previous stage for detecting additional bits) according to an embodiment of the present invention. In this figure, the variable-length decoding apparatus includes a first register 101 and a second register 102. , A code selector circuit 103, a conversion circuit 104, a decoding start circuit 105, a code selection control circuit 106, a DCT coefficient position register 107, and an output register 108.
[0016]
The code bit string CodeIn input from the preceding apparatus is held in the first register 101. The number of bits of the first register 101 must be equal to or greater than the value obtained by adding the maximum code length of the variable length code and the maximum bit length of the variable length additional information bits. In a general JPEG encoding method, the maximum code length is 16 bits and the maximum additional information bit length is 11 bits. Therefore, the number of bits of the register 101 is 27 bits or more. In this embodiment, the number of bits of the register 101 is 32 bits so that the electronic circuit can be easily mounted. This register can be realized by connecting the multiplexer 111 and the flip-flop 111 as shown in FIG. 2 and arranging them in parallel. The loading of the code bit string to the first register 101 is controlled by a load signal.
[0017]
The second register 102 is configured in the same manner as the first register 101. When a new code bit string is loaded into the first register 101, the code bit string held in the first register 101 until then is stored. Load it. This loading operation is performed when the decoding of the code bit string held in the second register 102 is completed.
[0018]
The code 32 bits of the first register 101 and the code 32 bits of the second register 102 are concatenated and input to the code selector 103 as a 64-bit code string bit 63-0. In this embodiment, it is assumed that codes are packed in order from the MSB side of a 32-bit code string. In this case, the upper 32 bits of the 64 bits are the 32 bits of the code of the second register 102, the lower 32 bits are the 32 bits of the code of the first register 101, and the MSB side of the first and second registers is the code after the connection. They are concatenated so that they are on the MSB side of the bit string.
[0019]
As shown in FIG. 3, the selector circuit 103 cuts out and outputs a 27-bit code code 26-0 from the input 64-bit code sequence bit 63-0 in response to a 5-bit select signal. When the select signal is “00000”, bits 63-37 are output, and whenever the value of the select signal increases by 1, the code at the position shifted to the lower one bit is cut out. When the select signal is “11111”, bit 32 is output. Output -6. The selector circuit 103 can be realized by connecting multiplexers in multiple stages in parallel.
[0020]
Of the 27-bit code string output from the selector circuit 103, the upper 16 bits including the variable length code are input to the conversion circuit 104 that performs conversion using the Huffman code table. As an example of input and output of the conversion circuit 104, FIG. 4 shows input and output of a conversion table that is generally used when decoding the luminance component of an image in JPEG image encoding.
[0021]
The most significant bit of the input table-in 16-0 of the conversion circuit 104 inputs a signal for switching between a DC coefficient conversion table and an AC coefficient conversion table. The remaining 16 bits of the input are the upper 16 bits of the output of the selector circuit 103. In the example of FIG. 4, there is a word in which only an input pattern of less than 16 bits is shown as an input bit from the selector circuit 103, which indicates that the insufficient lower-order bits are don't care. For example, the input pattern of the third row is “011”. If the upper 3 bits of the input code string are “011”, the output is right regardless of the remaining 13-bit value. '00101 0000 0010' shown in FIG.
[0022]
The output of the conversion circuit 104 includes decoded data, the code length of the variable length code, the bit length of the variable length additional information bit, and the decoded code obtained by adding the code length of the variable length code and the bit length of the variable length additional information bit Four pieces of long information are required. However, since it is possible to easily obtain the remaining one of the three other than the decoded data if the two are known, it is not always necessary to output all three from the conversion circuit 104. In the output signal table-out12-0 in the example of FIG. 4, the upper 5 bits are the decoded code length obtained by adding the code length of the variable length code and the bit length of the variable length additional information bit, and the next 4 bits are the AC coefficient sequence The decoded data indicating the run length of zero in the middle, and the least significant 4 bits are the bit length of the additional information bits.
[0023]
As an example of a method for mounting the conversion circuit 104 using a decoding table, there is a method in which an input / output relationship as shown in FIG. 4 is given to a logic synthesis tool and a logic circuit that satisfies this relationship is automatically synthesized. In the case of the decoding table in the example of FIG. 4, it can be implemented with a small and high-speed circuit in which the number of logic cells is 700 or less and the delay time from input to output is 15 stages or less of logic cells.
[0024]
As an example of another mounting method of the conversion circuit 104, there is mounting by a memory circuit such as a ROM or a RAM. In this case, 17 bits of address input and 13 bits of data output are required to implement the decoding table of the example of FIG. Therefore, the circuit scale is 13 bits × 131072 words. When implemented using a RAM, there is an advantage that a plurality of encoding / decoding tables can be handled by rewriting the contents of the RAM at an appropriate timing during the operation of the circuit.
[0025]
A configuration example of the decryption activation circuit 105 is shown in FIG. The decryption activation circuit 105 includes a state logic 112 and a latch 113. FIG. 6 shows an example in which the State changes according to the Start signal. In this example, when the Start signal becomes L, the State becomes “00”. When the Start signal becomes H, the State changes from “01” → “10” → “11” from the next clock cycle, and then the Start signal. State stays at “11” until becomes L. When State is “00”, the circuit is in a stopped state. When the State is '01' and '10', the first two words (64 bits) code string is loaded into the first register 101 and the second register 102, and decoding is not started. When State is “11”, one code is decoded in one cycle, and a new code string is loaded into the first register 101 and the second register 102 as necessary.
[0026]
A configuration example of the code selection control circuit 106 is shown in FIG. The sign selection control circuit 106 includes an adder 116, a first start logic 114, a second start logic 115, and a latch 117. The selector circuit 103 is switched by the select signal output from the control circuit 106, and the first register 101, the second register 102, and the device that outputs the code bit string in the preceding stage of the decoding device are controlled by the load signal. . The select signal is updated every cycle by adding the upper 5 bits table-out12-8 of the output of the conversion circuit 104. The load signal outputs the carry out of the adder 116. When the decoding device is activated, the select signal and the load signal are output as shown in FIG.
[0027]
A configuration example of the DCT coefficient position register 107 is shown in FIG. The DCT coefficient position register 107 includes a NAND circuit 118, an AND circuit 121, NOR circuits 119 and 120, an OR circuit 122, a latch 123, an adder 124, and an incrementer 125. The output CoefPosition of the DCT coefficient position register 107 is updated every cycle by adding “1” to the output table-out7-4 of the conversion circuit 104. When the decryption device is activated, CoefPosition = '000000' until State becomes '11'. In addition, since the conversion circuit 4 outputs table-out7-0 = '00000000' to EOB (End of Block), CoefPosition = '000000' is set in this case as well. Also, when CoefPosition = '000000', DC / AC = '0', otherwise DC / AC = '1', and the DC coefficient conversion table and AC coefficient conversion table of the conversion circuit 104. Switch. As indicated by a broken line in FIG. 1, the code bit string (TableIn16-0) from the code selector circuit 103 may be directly supplied to the DCT coefficient position register 107 to detect EOB and set DC / AC = '0'. .
[0028]
The output of the selector circuit 103, the output of the conversion circuit 104, and the output of the DCT coefficient position register 107 are synchronized with the output register 108 and output to the next stage circuit. The register 108 can be configured by connecting flip-flops in parallel.
[0029]
FIG. 10 shows a configuration example of a circuit connected to the next stage of this circuit. The circuit in the next stage includes a DCT coefficient selector circuit 126, a differential code decoding circuit 127, a multiplexer 128, a multiplier 129, a quantization coefficient output circuit 130, and a run length code decoding circuit 131. Using the code length output from the conversion circuit 104 and the additional information bit length, a DCT coefficient quantized from the code bit string output from the selector circuit 103 is obtained. In the case of a DC coefficient, the DCT coefficient is restored from the difference from the previous block. The output of the DCT coefficient position register 107 is used to obtain a quantization step from the quantization table, and the multiplier 129 performs inverse quantization. As described above, by providing the DCT coefficient position register 107 in the variable length code decoding apparatus, the circuit of the next stage can be made simple and a circuit capable of high speed operation can be obtained.
[0030]
【The invention's effect】
According to the present invention, one variable length code can always be interpreted and decoded in one clock cycle, and the decoding speed can be guaranteed regardless of the code length. Further, additional information bits added to the variable length code can be easily taken out by a circuit in the next stage. Further, by providing the DCT coefficient position register, the DC coefficient conversion circuit and the AC coefficient conversion circuit can be appropriately switched. Further, since the output of the DCT coefficient position register is output to the next-stage circuit, the inverse quantization circuit can easily obtain the necessary quantization step value from the quantization table using this value.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention as a whole.
FIG. 2 is a block diagram illustrating a configuration example of a 1-bit register configuring the first and second registers.
FIG. 3 is a block diagram illustrating a configuration example of a code selector circuit.
FIG. 4 is a diagram illustrating an example of an input / output relationship of a conversion circuit.
FIG. 5 is a block diagram illustrating a configuration example of a decoding start circuit.
FIG. 6 is a waveform diagram showing input / output signal waveforms of a decoding start circuit.
FIG. 7 is a block diagram illustrating a configuration example of a code selection control circuit that controls the first and second registers and the selector circuit;
FIG. 8 is a diagram for explaining an operation at the time of activation of a code selection control circuit;
FIG. 9 is a block diagram illustrating a configuration example of a DCT coefficient position register.
FIG. 10 is a block diagram showing the whole circuit connected to the next stage of the variable length code decoding apparatus of the present invention.
FIG. 11 is a block diagram showing a conventional technique.
[Explanation of symbols]
Reference Signs List 101 First register 102 that holds a sign bit string Second register 103 that holds a sign bit string 103 Sign selector circuit 104 Conversion circuit 105 Decode start circuit 106 Sign selection control circuit 107 DCT coefficient position register 108 Output register

Claims (4)

In a variable length code decoding apparatus that encodes a set consisting of a run length of a DCT coefficient of zero AC component and a value of a DCT coefficient of a non-zero AC component following this,
A first register holding a sign bit string input in parallel in a plurality of bits;
When a new code bit string is written in the first register, a second register that holds the code bit string held in the first register until then,
A selector for extracting a code bit string to be decoded from code bit strings held in the first register and the second register;
Decoding by adding the code bit string to be decoded as input and decoding data, variable length code length, variable length additional information bit length, variable length code length and variable length additional information bit length A conversion circuit for outputting a completed code length;
A control circuit for updating the contents of the first register and the second register using the decoded code length output from the conversion circuit and instructing the selector of the extraction position of the code bit string to be decoded next;
For each set consisting of the run length of the DCT coefficient of the zero alternating current component and the value of the DCT coefficient of the nonzero alternating current component included in the decoded data, the run length of the DCT coefficient of the zero alternating current component is The number of DCT coefficients of the zero AC component shown and the number of DCT coefficients of the non-zero AC component, which is obtained by accumulating the number of DCT coefficients currently being decoded , is the number of DCT coefficients currently decoded in the block. A DCT coefficient position register for storing DCT coefficient position data indicating whether it is a DCT coefficient, and resetting the current DCT coefficient position data to an initial value by an EOB (End of Block) code ;
Means for switching between a DCT coefficient conversion circuit for a DC component and a DCT coefficient conversion circuit for an AC component using the output of the DCT coefficient position register;
A variable-length code decoding apparatus comprising: a register that outputs an output of the selector, an output of the conversion circuit, and an output of a DCT coefficient position register to a subsequent apparatus. 2. The variable length code decoding apparatus according to claim 1, wherein the conversion circuit is constituted by a logic circuit satisfying an input / output relationship. 2. The variable length code decoding apparatus according to claim 1 , wherein the conversion circuit is constituted by a rewritable memory circuit. A variable-length additional bit representing a difference in the quantized data of the DCT coefficient of the DC component of the image block, a variable-length code for the DC component assigned to the bit length of the additional bit, and a non-zero DCT coefficient of each AC component Variable-length additional bits representing the quantized data, and the variable length code for the AC component assigned to the combination of the bit length of this additional bit and the run length of the AC component for which the quantized data of the DCT coefficient is zero From the code bit string that is successively constructed in a predetermined order, and from the code bit string based on the information from the preceding stage and the preceding stage part that sequentially cuts out the set of the variable length code and the additional bit of the variable length A variable-length code decoding apparatus comprising a subsequent stage that extracts and decodes the variable-length additional bits;
The front part is
A first register holding a sign bit string input in parallel in a plurality of bits;
When a new code bit string is written in the first register, a second register that holds the code bit string held in the first register until then,
A selector for extracting a code bit string to be decoded from code bit strings held in the first register and the second register;
Data relating to code length of variable length code and bit length of additional information bit of variable length, and data relating to zero run length of quantized data of DCT coefficient of AC component included in decoded data with code bit string to be decoded as input A conversion circuit that outputs
A control circuit for updating the contents of the first register and the second register using data relating to the bit length output from the conversion circuit and instructing the selector of the extraction position of the code bit string to be decoded next;
Included in the decoded data for each variable length code for the AC component, the AC component of the number and the non-zeros which follow the DCT coefficients of the AC component of the zero indicating the run length of the D CT coefficients of the AC component of the zero DCT coefficient position information indicating which DCT coefficient of the frequency component being decoded is the DCT coefficient in the block obtained by sequentially accumulating 1 which is the number of DCT coefficients of A DCT coefficient position register for resetting current DCT coefficient position data to an initial value by an EOB (End of Block) code ;
A code bit sequence to be decoded, a register that outputs data relating to a code length of a variable length code and a bit length of a variable length additional bit, and an output of the DCT coefficient position register to the subsequent stage Variable length code decoding device.

Images