JP4013680B2 - Decoding device and decoding method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a decoding device for a variable length code such as a Huffman code, and more particularly to a decoding device having a high decoding speed.
[0002]
[Prior art]
Data compression and data encoding techniques are widely used to increase the speed at the time of data transmission and the efficiency at the time of storage. There are various methods for compressing and encoding image data, and one of them is a method combining DCT (Discrete Cosine Transform) and variable length encoding such as Huffman code. A representative example of this method is the JPEG method.
[0003]
Image coding by a method combining such DCT and variable length coding will be described with reference to FIG. In the case of a full-color image, a plurality of color components are separated into single color components such as Y-Cb-Cr, RGB, and YMCK, and each color component is processed independently. An 8 × 8 pixel region in the image is converted into a sequence of 64 coefficients by DCT, quantization, and zigzag transformation.
[0004]
In this sequence, one codeword symbol of a variable length bit sequence is assigned to consecutive zeros and non-zero coefficients appearing thereafter. When non-zero coefficients are consecutive, one codeword symbol is assigned to one coefficient. A set of bit strings of the code word is a code file. The encoding process has been described above. By following this process in reverse, the code file can be decoded and an image can be obtained.
[0005]
As a conventional example of an apparatus for performing decoding of such a system, there is a decoding apparatus disclosed in Japanese Patent Laid-Open No. 5-63586. This apparatus will be described with reference to FIG. The code input unit 11 includes storage means (not shown) and holds a plurality of bits being processed in the code bit string.
[0006]
The code cutout unit 12 includes a selection circuit (not shown) for cutting out a portion of the bit string held by the code input unit 11 that has not been decoded. The code cutout unit 12 is implemented by a circuit such as a barrel shifter. The extracted code bit string is input to the table T for decoding.
[0007]
The table T is implemented by a ROM (Read Only Memory), a RAM (Random Access Memory), a PLD (programmable logic device) that performs the same operation, a combinational logic circuit, or the like. The output of the table T is output to an inverse quantization circuit and an IDCT (Inverse Discrete Cosine Transform) circuit via a decoding result output unit 15 at the subsequent stage.
[0008]
The code length of the decoded variable-length code is also output from the table T, and this value is cumulatively added by the code position management unit 13 to determine the next code word cut-out position or to the code input unit 11 for the next code bit string. Used to capture
[0009]
When such a device is operated in synchronization with a clock signal, one symbol can be decoded in one clock cycle. In addition to this publication, there are many examples of decoding one symbol in one clock cycle by accumulating and adding the bit lengths of decoded codes having a code cutout unit and a decoding table.
[0010]
As another conventional example, there is a technique disclosed in JP-A-9-246988. This technique includes a plurality of decoding tables (decoding RAMs) for decoding a plurality of symbols in one cycle. However, since the output of the first table is used as the input of the second table, the critical path (signal propagation path with the longest delay time) of the circuit becomes long, and the frequency of the operation clock is increased. I can't. For example, if the circuit of the previous example decodes one symbol in one clock cycle at 100 MHz and the circuit of this example decodes two symbols in one clock cycle at 50 MHz, the output speed of the decoding result does not change.
[0011]
As another conventional example, there is a technique disclosed in JP-A-8-265165. In this technique, in order to decode two symbols in one cycle, both the rising edge and falling edge of the clock signal are used, and the clock frequency cannot be increased. Rather, the operation speed decreases because the circuit becomes complicated.
[0012]
As another conventional example, there is a technique disclosed in Japanese Patent Application Laid-Open No. 9-261076. In this technique, in order to decode a plurality of symbols by one decoding table access, the table has decoding information for a bit string in which a plurality of symbols appear continuously.
[0013]
For example, in the JPEG (Joint Photographic coding Experts Group) method, the number of entries in the table when decoding one symbol per cycle as in the above example is about 160. However, if 2 symbols are decoded in one cycle by the method of this example, 160 × 160 = 25600 entries are required. If 3 symbols are decoded in 1 cycle, 160 × 160 × 160 = 4096000 entries are required, and the table becomes huge. .
[0014]
As another conventional example, there is a technique disclosed in Japanese Patent Laid-Open No. 7-249994. This example will be described with reference to FIG. In this example, one table for the first symbol and a plurality of tables for the second symbol are provided in order to decode two symbols per cycle.
[0015]
That is, the code input unit 21 includes storage means (not shown), and holds a plurality of bits being processed in the code bit string. The code cutout unit 22 includes a selection circuit (not shown) for cutting out a portion of the bit string held by the code input unit 21 that has not been decoded.
[0016]
The table for the second symbol is a code bit string corresponding to the predicted bit length of the first symbol so that the second symbol can be decoded before the bit length of the first symbol is known. Several are prepared by shifting.
[0017]
When the bit length of the first symbol is determined, only one is selected by the selector 24 from the outputs of the plurality of tables for the second symbol, and the result is the decoding result of the second symbol. The output from the selector 24 is output to an inverse quantization circuit and an IDCT (Inverse Discrete Cosine Transform) circuit via a decoding result output unit 25 at the subsequent stage.
[0018]
Further, the code length of the decoded variable length code is also output from the table, and this value is cumulatively added by the code position management unit 23 via the selector 24 to determine the cutout position of the next codeword or the code input unit. 21 is used to capture the next code bit string.
[0019]
In this example, since the critical path of the circuit is not so long, high speed operation can be expected. However, in order to decode the JPEG code with this circuit, 24 decoding tables for the second symbol are required.
[0020]
[Problems to be solved by the invention]
A circuit that decodes one symbol in one clock cycle as in the above-described conventional example can be achieved relatively easily, but it has been difficult to obtain a higher decoding speed. There is a problem that the critical path becomes long and the clock frequency cannot be increased, so that the output speed of the decoding result does not change much, or the circuit scale becomes enormous and the performance effect corresponding to the cost cannot be obtained. Accordingly, an object of the present invention is to provide a decoding device that can increase the clock frequency and increase the output speed of the decoding result while suppressing an increase in circuit scale to some extent.
[0021]
[Means for Solving the Problems]
The present invention has been made to solve such problems. That is, the present invention provides a decoding apparatus for decoding code data obtained by allocating codewords composed of variable-length bit strings to predetermined information and decoding information is output with respect to one codeword input. A first decoding table, a second decoding table that outputs decoding information for a plurality of codewords in response to an input of a codeword pattern in which a plurality of codewords having a zero run less than a predetermined amount are continuous, and a first decoding table Selecting means for selecting one of the output and the output of the second decoding table.
[0022]
In addition, a combination of DCT (Discrete Cosine Transform) and variable-length code is used, and is encoded by an image encoding method in which variable-length bit codewords are assigned to consecutive zero coefficients of a sequence of DCT coefficients and subsequent non-zero coefficients. In the decoding device for decoding the encoded data, the first decoding table that outputs the decoding information when one of the codewords of all types appears, and the information that is less than a predetermined amount of zero run A second decoding table that outputs decoding information for a plurality of codewords in response to an input of a codeword pattern in which a plurality of codewords assigned to is continuous, an output of the first decoding table, and an output of the second decoding table And a selection means for selecting one of the above.
[0023]
In addition, when the above decoding apparatus is used, code data is given to both the first decoding table and the second decoding table and decoding is performed in parallel, and a plurality of codewords are simultaneously decoded by the second decoding table. In the decoding method, the output of the second decoding table is selected by the selection unit, and when the decoding cannot be performed by the second decoding table, the output of the first decoding table is selected by the selection unit.
[0024]
In the present invention, codeword symbols assigned to a large number of DCT coefficients are decoded one symbol at a time in the first decoding table, and codeword symbols assigned to a small number of DCT coefficients are decoded in the second decoding table. Since a plurality of symbols are decoded together, the output result is information corresponding to a large number of DCT coefficients, and the output speed of the decoding result is increased.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a decoding device according to this embodiment. That is, the decoding apparatus includes a code input unit 1, a code cutout unit 2, a first decoding table T1, a second decoding table T2, a selector 4 for switching the outputs of the decoding tables T1 and T2, a decoding result output unit 5, a code The location management unit 3 is configured.
[0026]
The code input unit 1 reads a code bit string in order from the top of the code file, holds a plurality of bits, and applies the plurality of bits to the code cutout unit in parallel. When the held bit string is decoded, the decoded bit string is discarded and a new bit string is read. In order to continuously provide the code bit string to the code cutout unit, it is configured by two or more stages of shift registers connected in cascade.
[0027]
The code cutout unit 2 cuts out processed bits and unprocessed bits from the bit string provided from the code input unit 1. Since the output to the subsequent table is used as an address for table access, output is performed so that the head of the unprocessed bit becomes the most significant bit of the address. Mount with a barrel shifter.
[0028]
The code position management unit 3 manages which position of the bit string passed from the code input unit 1 to the code cutout unit 2 is the boundary between the processed bit and the unprocessed bit. For this purpose, every time the codeword symbol is decoded, the bit length of the decoded code is cumulatively added. The code position management unit 3 gives the shift amount of the barrel shifter to the code cutout unit 2. Further, a signal instructing the code input unit 1 to read a new bit string is given.
[0029]
In the first decoding table T1, decoding results can be obtained when only one word of all types of codeword symbols appears. The table is implemented by a ROM (Read Only Memory), a RAM (Random Access Memory), a PLD (programmable logic device) that performs the same operation, a combinational logic circuit, or the like.
[0030]
The bit string input from the code cutout unit 2 is used as the address input of the decoding table T1. The output includes the bit length of the decoded codeword symbol, the number of zero runs, the bit length of additional bits added after the codeword symbol, the total bit length of the codeword and additional bits, and the like.
[0031]
In the case of JPEG (Joint Photographic coding Experts Group) code assignment, there are about 160 types of codeword symbols. If this is simply implemented in a ROM, a large number of addresses holding the same data exist, which is inefficient. By providing information on 160 types of valid entries in the decoding table and generating a combinational logic circuit that operates in the same manner as a ROM using a logic synthesis software tool, the circuit scale can be reduced.
[0032]
In the second decoding table T2, a decoding result can be obtained when a plurality of codeword symbols having a small zero run appear continuously. The input of the table T2 is a bit string of the code, and the output is the bit length of the decoded code word symbol, the number of zero runs, the bit length of the additional bits added after the code word symbol, and the sum of a plurality of code words and additional bits Is a signal indicating whether or not simultaneous decoding of a plurality of symbols was possible.
[0033]
As an example, let us consider a case where simultaneous decoding is performed when a symbol whose zero run is zero appears twice consecutively in JPEG code assignment. There are 10 types of zero run zero symbols. There are 10 × 10 = 100 patterns when two of these appear in succession.
[0034]
When this is implemented in ROM, the number of input bits increases, so a ROM with a large number of words is required. However, when a combinational logic circuit is generated with a logic synthesis tool as described above, the circuit scale is determined by the number of entries in the table. The scale can be reduced. Therefore, the first table and the second table are almost the same scale circuit.
[0035]
The selector 4 for switching the output of the decoding table uses the output of the first decoding table T1 and the output of the first decoding table T1 according to the “signal indicating whether or not simultaneous decoding of a plurality of symbols has been performed” output from the second decoding table T2. 2 is switched to the output of the decoding table T2.
[0036]
That is, if the second decoding table T2 can decode a plurality of symbols, the output of the second decoding table T2 is output. If the second decoding table T2 cannot decode a plurality of symbols, the first symbol is output. The output of the decoding table T1 is output.
[0037]
The decoding result output unit 5 outputs the code bit string output from the code cutout unit 2 and the output from the selector 4 to the subsequent stage in synchronization. In the subsequent stage, a sequence of DCT (discrete cosine transform) coefficients is restored from these values, and further, inverse quantization and IDCT (inverse discrete cosine transform) are performed to restore the image.
[0038]
Here, as shown in FIG. 2, how many DCT coefficients are obtained when one codeword symbol is decoded is determined by the number of consecutive zeros (zero run). When a codeword symbol with many zero runs is decoded, a large number of DCT coefficients are obtained, and when a codeword symbol with zero runs is zero, only one DCT coefficient is obtained.
[0039]
Therefore, in the present embodiment, by using the decoding device as described above, a plurality of codeword symbols with few zero runs can be decoded together in one cycle, and one codeword symbol with many zero runs is decoded in one cycle. To do.
[0040]
That is, a first decoding table for obtaining a decoding result when only one type of codeword symbol appears, and a decoding result for obtaining a codeword symbol with few zero runs continuously. A second decoding table, and a code bit string is input to both tables at the same time. If there is information corresponding to the second table, the output of the second table is set as a decoding result, and the second table contains If there is no corresponding information, the output of the first table is taken as the decoding result.
[0041]
As a result, codeword symbols assigned to a large number of DCT coefficients are decoded one symbol at a time in the first decoding table, and codeword symbols assigned to a small number of DCT coefficients are converted to a plurality of codeword symbols in the second decoding table. Since symbols are decoded together, the output result is information corresponding to a large number of DCT coefficients, and the output speed of the decoding result is increased.
[0042]
Next, the present embodiment is compared with the prior art. This embodiment (FIG. 1) is compared with the prior art (1) (FIG. 5) and the prior art (2) (FIG. 6). These configurations are assumed to operate at approximately the same clock frequency because the critical path lengths are approximately the same.
[0043]
When decoding a JPEG code, the prior art {circle over (1)} requires one table. In the case of the prior art (2), the number of necessary tables is determined by the bit length of the first symbol, and in the case of the JPEG system, 24 tables are required. In the case of the present embodiment, if two symbols with zero run are zero are decoded together, a two-sided table is required as in the above-described example. Therefore, comparing the circuit scale,
This embodiment: Conventional technique {circle around (1)}: Conventional technique {circle around (2)} = 2: 1: 25
It becomes.
[0044]
Next, the decoding speed is compared. The decoding speed depends on how many zeros appear in the sequence of DCT coefficients, that is, the image to be processed. Evaluation is made in the case of the worst value such that zero hardly appears in the DCT coefficient.
[0045]
The case where there is no zero at all is shown in FIG. The number of processing cycles in each configuration is the prior art {circle around (1)} = 64 cycles, the prior art {circle around (2)} = 33 cycles, and the present embodiment = 33 cycles.
[0046]
In this embodiment, the number of cycles becomes the worst value when the second table does not function at all. An example of such a case is shown in FIG. The number of processing cycles in each configuration is the prior art (1) = 43 cycles, the prior art (2) = 22 cycles, and the present embodiment = 43 cycles.
[0047]
Considering the case of FIG. 3 and FIG. 4 together, the worst value of the number of cycles is the prior art (1) = 64 cycles, the prior art (2) = 33 cycles, and the present embodiment = 43 cycles. Therefore, when comparing the decoding speed,
The present invention: Conventional technique (1): Conventional technique (2) = 1.5: 1: 2
It becomes.
[0048]
In summary, considering the common configuration of one symbol per cycle as in the conventional example (1), the decoding speed of the conventional technique (2) is doubled, but the circuit scale is 25 times larger. Therefore, an effect commensurate with the increase in circuit scale has not been obtained. In the present technology, the circuit scale is suppressed to twice the decoding speed of 1.5 times.
[0049]
【The invention's effect】
According to the decoding apparatus of the present invention, since a plurality of symbols having a small number of zero runs are decoded together, a sequence of DCT coefficients can be obtained with a small number of cycles, and a decoding result image can be obtained at high speed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating an embodiment.
FIG. 2 is an explanatory diagram of an image encoding method combining DCT and Huffman code.
FIG. 3 is an explanatory diagram for comparing decoding speeds.
FIG. 4 is an explanatory diagram for comparing decoding speeds.
FIG. 5 is a configuration diagram showing a conventional example (No. 1).
FIG. 6 is a configuration diagram showing a conventional example (No. 2).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Code input part, 2 ... Code extraction part, 3 ... Code position management part, 4 ... Selector, 5 ... Decoding result output part, T1 ... 1st decoding table, T2 ... 2nd decoding table

Claims (4)

In a decoding device for decoding code data obtained by allocating and encoding a code word consisting of a variable-length bit string for predetermined information,
A first decoding table for outputting decoding information in response to input of one codeword;
A second decoding table for outputting decoding information for a plurality of code words in response to an input of a code word pattern in which a plurality of code words having a zero run less than a predetermined amount are continuous;
A decoding device comprising: selection means for selecting one of the output of the first decoding table and the output of the second decoding table. A code encoded by an image encoding method using a combination of DCT (Discrete Cosine Transform) and a variable-length code, and assigning a variable-length bit codeword to consecutive zero coefficients of a sequence of DCT coefficients and subsequent non-zero coefficients. In a decoding device for decoding data,
A first decoding table that outputs decoding information when one of the codewords of all types appears;
A second decoding table that outputs decoding information for a plurality of codewords in response to an input of a plurality of codeword patterns in which a plurality of codewords assigned to information having a zero run less than a predetermined amount;
A decoding apparatus comprising: a selecting unit for selecting one of the output of the first decoding table and the output of the second decoding table. In a decoding method for decoding code data obtained by allocating and encoding a code word consisting of a variable-length bit string for predetermined information,
A first decoding table that outputs decoding information in response to an input of one codeword, and outputs decoding information for a plurality of codewords in response to an input of a codeword pattern in which a plurality of codewords having zero runs less than a predetermined amount are continuous Using a decoding device comprising: a second decoding table; and a selection means for selecting one of the output of the first decoding table and the output of the second decoding table;
Code data is supplied to both the first decoding table and the second decoding table to perform decoding in parallel, and when a plurality of codewords are simultaneously decoded by the second decoding table, the selection means Select the output of the second decoding table,
The decoding method, wherein when the decoding cannot be performed by the second decoding table, the selection unit selects an output of the first decoding table. A code encoded by an image encoding method using a combination of DCT (Discrete Cosine Transform) and a variable-length code, and assigning a variable-length bit codeword to consecutive zero coefficients of a sequence of DCT coefficients and subsequent non-zero coefficients. In a decoding method for decoding data,
A first decoding table that outputs decoding information when one codeword of all types of codewords appears, and a codeword in which a plurality of codewords assigned to information less than a predetermined amount of zero run are consecutive A second decoding table for outputting decoding information for a plurality of code words in response to a pattern input, and an output for selecting one of the output of the first decoding table and the output of the second decoding table. Using a decoding device comprising selection means,
Code data is supplied to both the first decoding table and the second decoding table to perform decoding in parallel, and when a plurality of codewords are simultaneously decoded by the second decoding table, the selection means Select the output of the second decoding table,
A decoding method characterized by selecting an output of the first decoding table by the selection means when the second decoding table cannot be decoded.

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