JP2710917B2 - Header detector and decoding device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a header detector for detecting the head of a predetermined code from a code string, and an improvement of a decoding device using the same.

[0002]

2. Description of the Related Art In recent years, with the digitization of transmission lines and storage media, encoders and decoders have been actively used. The header detector searches for the leading code (header code) included in the input code string in the variable-length decoder or the like, and detects the position of the leading code following the header code. Used to

[0003] A conventional header detector will be described below.
It is assumed that the header code is composed of n consecutive 0s followed by 1s.

The configuration of a conventional header detector is as follows. That is, first, a code string is input from the outside, the code string is output one bit at a time from the beginning, and the value of each output bit is compared by a comparator to determine whether it is 0 or 1 and is 0. In this case, the accumulator accumulates the consecutive numbers of 0 and compares the accumulation result with a set value (= n). By repeating the above operation n times, the value of each bit from the first bit to the n-th bit is all 0, that is, the output (accumulation result) of the accumulator is n
And the value of the next output bit is 1, it is determined to be a header code. Even if the value of the next output bit is not 1, it is determined that the value of the next output bit is 1 after the accumulation result of the accumulator is n + 1 or more, that is, after n + 1 or more 0s continue. If it is, it is determined as a header code.

On the other hand, if the output bit value is determined to be 1 by the comparator in a situation where the accumulation result of the accumulator is less than n, the accumulator is reset and the accumulated number of 0s is reset. Returns to 0. Therefore, even if the accumulation of the accumulator starts from the beginning and the subsequent n bits are sequentially output one by one, the header code is not determined. The output of the aforementioned bits is performed in synchronization with the clock signal.

[0006]

However, in the conventional header detector, the input code string is processed bit by bit from the beginning, so that the header code is detected by the number of bits of the header code. The same number of clocks as is required. Therefore, considering the operation speed of the shifters and accumulators constituting the header detector, the search speed of the header code is limited, and the search cannot be performed at a higher speed.

When a decoder is constructed using the conventional header detector, since the header detector can output only one bit at a time as described above, the decoded code is shifted out. Requires a number of clocks equal to the code length, and consequently, even when decoding is performed by a decoder, the decoding operation cannot be performed at high speed due to the operation speed of the header detector. Had problems.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to detect a header code at a high speed without requiring the components of a header detector to operate at a high speed. Another object of the present invention is to realize a decoder using the header detector and perform the decoding operation at a high speed.

[0009]

In order to achieve the above-mentioned object, according to the present invention, a plurality of bits are output from the beginning of a code string, and even if a header code straddles each of the plurality of output bits, the present invention is not limited thereto. A configuration capable of reliably detecting the header code is adopted to speed up the detection of the header code.

That is, the header detector according to the first aspect of the present invention includes a shift unit that receives a code string and sequentially outputs the input code string for each bit string of a plurality of bits.
A bit string output from the shift means is input, a signal indicating the number of consecutive 0s is output from the upper side of the bit string, and it is detected whether or not the input bit string has a 1 and a result signal is output. Detecting means, accumulating means for receiving a signal from the detecting means and accumulating the number of consecutive 0s from the upper side, inputting the accumulation result of the accumulating means, and detecting the accumulated result Comparison means for comparing a set value corresponding to a header code to be output and outputting a signal of the comparison result, and output means for outputting a header detection signal based on the comparison result signal of the comparison means and the detection result signal of the detection means And characterized in that:

According to a second aspect of the present invention, in the header detector according to the first aspect, +1 is added to the number of consecutive 0s from the upper side indicated by the signal from the detecting means.
An adder; and a shift amount setting unit that sets a shift amount of the shift unit. The shift amount setting unit sets the number of set bits as an increment of the shift amount when the detection result signal having no 1 is output from the detection unit. When the detection means outputs a detection result signal having "1", the addition result of the +1 adder is used as an increment of the shift amount.

According to a third aspect of the present invention, in the header detector according to the first aspect, the accumulating means includes a register for storing an initial value, and an initial value stored in the register. And an adder for adding the number of consecutive 0s from the upper side indicated by the signal.

[0013] In addition, in the header detector according to the present invention, a code string is input, and the input code string is sequentially output for each bit string of a plurality of bits.
The bit string output from the shift means is input, a signal indicating the number of consecutive 0's from the upper side of this bit string and a signal indicating the number of consecutive 0's from the lower side are output, and the input bit string has 1's. Detecting means for detecting whether or not the signal is present, outputting a result signal, accumulating means for receiving a signal from the detecting means and accumulating the number of consecutive 0's from the upper side, and an accumulating result of the accumulating means. And comparing the accumulation result with a set value corresponding to a header code to be detected and outputting a signal of the comparison result; a comparison result signal of the comparison means and a detection result of the detection means Output means for outputting a header detection signal based on the signal, wherein the accumulating means includes, as an initial value, the number of consecutive 0's from the upper side when receiving a detection result signal having no 1 in the bit string from the detecting means. Using the accumulated results, characterized by using a number of 0 is continuous from the lower side shown signal from the detection means when receiving the detection result signal is 1 from the detection means into a bit string.

According to a fifth aspect of the present invention, in the header detector according to the fourth aspect, a +1 adder for adding 1 to the number of consecutive 0s from the upper side indicated by the signal from the detecting means. A shift amount setting device for setting a shift amount of the shift means. The shift amount setting device sets the number of set bits as an increment of the shift amount when the header detection signal is not output from the output means, and detects the header from the output means. When outputting a signal, the addition result of the +1 adder is set as an increment of the shift amount.

According to a sixth aspect of the present invention, in the header detector according to the fourth aspect, the detecting means inputs the bit string output from the shifting means, and the number of consecutive 0s from the upper side of the bit string. And a priority encoder that outputs a signal indicating the number of bits, and a bit string output from the shift means, and outputs a signal indicating the number of consecutive 0s from the lower side of the bit string. And another priority encoder which outputs a signal as a result of the detection.

According to a seventh aspect of the present invention, in the header detector according to the fourth aspect, the accumulating means includes a register for storing an initial value, and an initial value stored in the register. An adder for adding the number of consecutive 0's from the upper side indicated by the signal, and a selector for selecting the number signal of consecutive 0's from the lower side from the output of the adder or the detecting means and inputting the signal to the register; and a control unit for controlling said selector, said control unit receives the detection result signal from the detection means, to select the output of the adder when there is no 1 bit string, detect came to have 1 bit string The selector is controlled so as to select a number signal having consecutive 0s from the lower side from the means.

In addition, in the invention according to claim 8, in the header detector according to claim 1 or 4, the comparing means corresponds to a header code to be detected in which the accumulation result of the accumulation means is to be detected. When the set value is equal to the set value, a coincidence signal is output as a signal of the comparison result.

In addition, in the invention according to claim 9, in the header detector according to claim 1 or 4,
The output means outputs a header detection signal when receiving a coincidence signal from the comparison means and a detection result signal from the detection means.

According to a tenth aspect of the present invention, in the header detector according to the third or seventh aspect, the adder of the accumulating means sets the addition result corresponding to the header code to be detected. A register for holding the carry signal of the adder, and a header detection signal when receiving a result signal from the output of the register and 1 from the detection means. It is characterized by having another output means for outputting.

Further, in the invention according to claim 11, in the header detector according to claim 2 or 5, the header detector decodes a code and outputs a code length signal of the decoded code. A selector which is connected to the decoder and configures the shift amount setting device, selects the code length signal from the decoder after starting the decoder.

In addition, according to the twelfth aspect of the present invention, in the header detector according to the first or fourth aspect, the code string includes a large number of codes coded based on the MPEG standard for image compression coding. Is a bit string including

In addition, a decoding device according to the invention of claim 13 includes the header detector according to claim 1 and a decoder , wherein the decoder is an output unit of the header detector. Activate the header detection signal from
Start decoding the code output from the shift means of the header detector, output a code length signal of the decoded code,
The shift means of the header detector sets a code length signal from the decoder as an increment of a shift amount.

According to a fourteenth aspect of the present invention, there is provided a decoding apparatus including the header detector according to the fourth aspect, and a decoder , wherein the decoder receives a signal from an output means of the header detector. Activate the header detection signal as a start signal, start decoding the code output from the shift means of the header detector, output a code length signal of the decoded code, the shift means of the header detector, The code length signal from the decoder is set as an increment of the shift amount.

[0024]

With the above construction, the header detector according to the first to third aspects of the present invention performs the following operation. That is, the code string is input to the shift means, and then output from the shift means for each of a plurality of bits. The detection means obtains the number of consecutive 0s from the upper side of each output bit string, and detects whether or not each bit string has 1s. The accumulating means accumulates the number of each 0 obtained by the detecting means, and the comparator calculates the accumulation result of the number of 0s as a set value (the number of 0s in the header code to be detected). Compare. Therefore, the output means can output the header detection signal based on the comparison result of the comparator and the detection result signal in which the detection means has 1 in the bit string.

Here, the code string is output from the shift means in units of a plurality of bits, and the number of 0s contained in the bit string of the plurality of bits is detected. The header code can be detected at high speed without operating the shift means and accumulation means at high speed.

In particular, in the header detector according to the second aspect of the invention, when there is no 1 in the bit string output from the shift means, the shift amount setting means sets the number of set bits as the shift amount. The bit string following the bit string is output. On the other hand, if there is 1 in the bit string output from the shift means, the shift amount setting means sets the output of the +1 adder, that is, the number of bits from the top of the output bit string to 1 as the shift amount. The following bit string is output. Therefore, it is possible to calculate the number of 0s following each 1 included in the code string.

Further, in the header detector according to the present invention, when the detecting means detects that there is 1 in the bit string output from the shifting means, the accumulating means starts from the lower side. The number of consecutive 0s, that is, the number of 0s following 1 in the bit string is set as an initial value. Thereafter, each time the detecting means detects that there is no 1 in the bit string sequentially output from the shifting means, the accumulating means adds the number of 0s from the upper side of the output bits to the initial value, The accumulation of the number of consecutive zeros is repeated, and each time the number of zeros is compared with the set value by the comparing means. Therefore, the output unit can output the header detection signal based on the comparison result of the comparison unit and the detection result signal having 1 from the detection unit.

In particular, in the header detector according to claim 5,
If the detecting means detects that there is 1 in the bit string output from the shifting means, the 1 already exists in the bit string.
Since the number of subsequent 0s after has been detected by the detecting means,
In the next time, it is not necessary to output a bit string with the first 0 following the 1 as a head, and therefore, if no header code is detected, the shift amount setting unit always sets the set bit number to the increment of the shift amount. When the header code is detected, the shift amount setting unit sets the output of the +1 adder as the increment of the shift amount, so that the shift means outputs a bit string (code) following the detected header code.

In addition, in the decoding apparatus according to the present invention, the bit string is inputted to the decoder from the shift means of the header detector, and the decoder outputs the bit string from the header detector. Since it is started only after receiving the header detection signal, the decoding operation of the bit string (code) output from the header detector is performed thereafter. The decoder outputs the code length of the decoded code, and since this code length is an increment of the shift amount of the shift means of the header detector, each time each code is decoded, the shift means outputs the decoded code. Is shifted out by one clock, and the code located next is output. Therefore, as compared with the case of shifting out the respective code for each bit as in the prior art, to obtain performs output of the code from the shift means at high speed, it can speed up as a result of the decoding operation of the decoder .

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a decoding apparatus according to a first embodiment of the present invention.

In FIG. 1, reference numeral 100 denotes a buffer for outputting a code string, and 101 denotes a header detector. The header detector 101 outputs a read signal requesting the buffer 100 to output a code string. Buffer 100
When a code string is output from the, the code string is input and a header code included in the code string is detected. The header detector 101 outputs a header detection signal when detecting a header code, and outputs a code following the header code. Reference numeral 102 denotes a decoder which starts upon receiving a header detection signal from the header detector 101, decodes a code from the header detector 101, and outputs decoded data.

As shown in FIG. 2, the buffer 100 has an address generator 105, a memory 106, and a register 107. In the memory 106, a code string is stored by being divided for each predetermined number of bits, and an address is assigned to each section. The address generator 105 is the header detector 1
In response to the read signal of 01, 1 is added to the current address to generate the next address. The memory 106 receives the address of the address generator 105 and outputs a bit string of a predetermined number of bits corresponding to the address. The register 107 stores the bit string output from the memory 106 and outputs the bit string to the header detector 101.

Here, the code string is the same as that of MPEG, which is an internationally standardized image compression coding standard, as shown in FIG.
As shown in (a), the whole is called a sequence,
A sequence is composed of units called a plurality of pictures. One picture is composed of units called a plurality of slices as shown in FIG. A slice is a minimum unit as shown in FIG. Said sequence,
Although not shown, a header code exists at the head of each picture and each slice.

In the following description, for the sake of simplicity, it is assumed that the code string starts with a header code and is followed by a plurality of variable length codes vlc1, vlc2, vlc3... As shown in FIG. The actual header code is defined as one type of code in which 23 or more consecutive 0s are followed by 1s in MPEG, which is an international standard for image compression encoding.

The decoder 102 shown in FIG. 1 comprises a look-up table 110 and a control unit 111 as shown in FIG. The table 110 has a plurality of lookup tables corresponding to the types of variable length codes, and each lookup table associates a number of variable length codes with decoded data and code length corresponding to each code. Remember. The control unit 111 starts upon receiving a header detection signal from the header detector 101, inputs a code from the header detector 101, and outputs a table selection signal corresponding to the type of the code. The table 110 receives the table selection signal, selects a lookup table corresponding to the table selection signal, inputs a code from the header detector 101, and decodes the decoded data corresponding to the input code from the selected lookup table. Output code length.

As shown in FIG. 1, the header detector 101 receives the code length from the decoder 102 and shifts out the bit string by the code length. Therefore, next time, the header detector 101 outputs the bit string following the decoded code.

Next, the configuration of the header detector 101 of FIG. 1 will be described with reference to FIG. In FIG. 1, reference numeral 1 denotes a shifter (shift means). The shifter 1 inputs a predetermined number of bits (for example, 8 bits) from the beginning of the code string from the buffer 100 and outputs a shift amount signal to be described later. Then, it shifts out the number of bits of the shift amount indicated by this signal, and outputs a bit string of a plurality of bits following this. The output of the shifter 1 is input to the decoder 102 as shown in FIG.

Reference numeral 2 denotes a priority encoder (detection means). The encoder 2 receives the bit string output from the shifter 1 and inputs the bit string from the upper side of the bit string as shown in the truth table of FIG. The number of 0s is obtained, the obtained number signal of 0s is output, and when 1 is present in the input bit string, a signal (1
Is output. In the truth table of FIG.
The symbol x indicates an arbitrary value (1 or 0) following 1.

Reference numeral 3 denotes an accumulator (accumulation means). The accumulator 3 operates in synchronization with the same clock signal as the clock signal input to the shifter 1, and has an m-bit adder. 4 and an m-bit register 6. The number m is an integer exceeding the logarithm of n with 2 as a base, where n is the number obtained by subtracting 1 from the code length of the header code to be detected (m>
log ₂ n), and when n = 7, for example, m = 3. The adder 4 adds the output of the priority encoder 2 (that is, the number signal of 0) and the output value of the register 6. The register 6 stores the zero count signal from the adder 4 as an initial value, and is reset by receiving a 1-containing signal from the priority encoder 2 as a reset signal. Therefore, the accumulator 3 accumulates the output of the priority encoder 2 (the number signal of 0). Adder 4
Is the setting value (7 in decimal notation (111 in binary notation))
When it exceeds, a carry signal (Carry) is output.

Reference numeral 10 denotes a 3-bit comparator (comparing means) for comparing the addition result of the adder 4 with a set value (= 7) and outputting a signal (0 satisfaction signal) when the addition result is the set value;
Is a 1-bit register for inputting and holding the carry signal of the adder 4.

Reference numeral 12 denotes a first AND circuit (output means), and reference numeral 13 denotes a second AND circuit (other output means). The first AND circuit 12 includes a zero satisfaction signal of the comparator 10 and a priority encoder. The header detection signal is output in response to the 2 containing signal. The second AND circuit 13 receives the carry signal of the register 11 and the 1-content signal of the priority encoder 2 and outputs a header detection signal.
The header detection signals from the AND circuits 12 and 13 are output to the outside via the OR circuit 14, respectively.

Reference numeral 17 denotes a +1 adder. The +1 adder 17 adds 1 to the number signal of 0 from the priority encoder 2 and outputs a signal indicating the addition result. Reference numeral 18 denotes a selector. The selector 18 receives the addition result signal of the +1 adder 17, a set bit number signal (for example, a 4-bit signal), and a code length signal from the decoder 102. Select and output one. Reference numeral 19 denotes an accumulator. The accumulator 19 receives the signal selected by the selector 18 and accumulates its value, and outputs the result of the accumulation to the shifter 1 as a shift amount signal.
The accumulator 19 generates a read signal when the accumulation result exceeds the number of bits output from the buffer 100 at one time. The selector and the accumulator 19 constitute shift amount setting means 21 for setting the shift amount of the shifter 1.

A control unit 20 controls the selector 18. The control unit 20 controls the header detection signal from the OR circuit 14 and the priority encoder 2.
Can be received, and if no header detection signal is received, the control is changed according to the presence or absence of the 1-content signal. If no 1-content signal is received, the set bit number signal (=
The selector 18 controls the selector 18 so as to select each of the addition results of the +1 adder 17 when the 1-containing signal is received, and outputs the addition result of the +1 adder 17 when the header detection signal is received. After receiving the detection signal (after activation of the decoder), the selector 18 is controlled so as to select the code length from the decoder 102, respectively.

Next, the operation of the above configuration will be described with reference to the timing chart of FIG. Note that the output of the code string from the buffer 100 is not a main part of the present invention, and a description thereof will be omitted. In the operation described here, it is assumed that the header code is a code in which 1 is located after seven consecutive 0s so that the contents of the invention can be easily understood.

If the code string is as shown in FIG.
At the third time, the shifter 1 outputs the bit string “0000”.
As a result, the priority encoder 2 outputs “4” as the number signal of 0, and does not output the 1-containing signal (1-containing signal = 0). At this first time, the register 6 is reset to an initial value (= 0).

At the second time, the selector 18 is controlled by the controller 20
Selects and outputs the set bit number signal (= 4-bit signal), so that the shifter 1 outputs the next bit string “1000”. The priority encoder 2 outputs “0” as a number signal of 0 and outputs a 1-containing signal (1-containing signal = 1). The register 6 stores the previous count signal “0” of the encoder 2, and the adder 4 adds the previous count signal “4” of the zero and the current count signal “0” of the zero to obtain 0. Is obtained. The comparator 10 compares the accumulated number signal “4” with the set value (= 7) to determine
The first AND circuit 12 does not output a sufficiency signal and therefore does not output a header detection signal.

In the third time, the selector 18 is controlled by the controller 20
, The output (= 1 bit signal) of the +1 adder 17 is selected and output, so that the shifter 1 outputs the bit string “0000”. The priority encoder 2 outputs “4” as the number signal of 0 and does not output the 1-containing signal. Since the register 6 has been reset to “0” by the previous 1-containing signal, the adder 4 obtains the number signal “4” of 0. The comparator 10 receives the count signal “4” and the set value (=
7), the first AND circuit 12 does not output the header detection signal because it does not output the 0 satisfaction signal.

At the fourth time, the selector 18 selects and outputs the set bit number signal (= 4 bit signal), so that the shifter 1 outputs the next bit string “0100”. The priority encoder 2 outputs a number signal “1” of 0 and a 1-containing signal. The register 6 is set to 0 of the previous encoder 2.
Since the number signal “4” is stored, the adder 4 adds the previous number signal “4” of 0 and the current number signal “1” of 0, and the accumulated number signal “5” of 0. Get. The comparator 10 compares the accumulated number signal “5” with the set value (= 7) and does not output a zero satisfaction signal, so the first AND circuit 12 does not output a header detection signal.

At the fifth time, the selector 18 selects and outputs the output (= 2 bit signal) of the +1 adder 17,
Shifter 1 outputs bit string “0000” (the first half of the header code). The priority encoder 2 outputs “4” as the number signal of 0 and does not output the 1-containing signal. Register 6 is set to "0" by the previous 1-containing signal
, The adder 4 obtains the number signal “4” of 0. Since the comparator 10 compares this number signal “4” with the set value (= 7) and does not output a zero satisfaction signal,
The first AND circuit 12 does not output a header detection signal.

At the sixth time, since the selector 18 selects and outputs the set bit number signal (= 4 bit signal), the shifter 1 outputs the next bit string “0001” (the latter half of the header code). The priority encoder 2 outputs “3” as a number signal of “0” and outputs a “1” containing signal. Since the register 6 stores the previous number signal “0” of the encoder 2, the adder 4 adds the previous number signal “4” of 0 and the current number signal “3” of 0,
An accumulated number signal "0" of 0 is obtained. Comparator 10 compares the accumulated number signal "7" with the set value (= 7) and outputs a zero satisfaction signal. Therefore, the first AND circuit 12 outputs the 0
Upon receiving the sufficiency signal and the 1-containing signal, it outputs a header detection signal. The decoder 102 is activated upon receiving the header detection signal.

After that, the selector 18 is controlled by the control unit 20 and the addition result of the +1 adder 17 (4-bit signal)
Select and output. As a result, the shifter 1 shifts out the latter half of the header code, so that the shifter 1 next outputs a 4-bit bit string following the header code. The decoder 102 decodes the bit string from the shifter 1 and outputs a code length signal of the decoded code. Since the selector 18 of the header detector 101 is controlled by the control unit 20 to select and output the code length signal from the decoder 102, the shifter 1 has four bits including the code located next to the decoded code. Is output.

Thus, in the present embodiment, the header code can be detected with 6 clocks for the code string shown in FIG. 19
It can only be detected after the clock. Therefore, in this embodiment, even if the operation speed of the shifter 1 and the accumulator 3 is the same as the conventional speed, the search speed of the header code can be increased.

Further, the shifter 1 converts the decoded code to 1
Conventionally, the decoded code is shifted out for the first time with the number of clocks equal to the code length (number of bits) of the decoded code, while shifting out with the clock.
Therefore, in the present embodiment, the period at which the code is output from the header detector 101 to the decoder 102 is increased, and as a result, the decoding operation by the decoder 102 can be performed at a high speed.

(Second Embodiment) FIG. 9 shows a second embodiment of the present invention. In the present embodiment, another priority encoder for obtaining the number of zeros from the lower side in the bit string output from the shifter 1 is provided, and the accumulator 3 of the first embodiment is improved to improve the header code. The detection can be performed even faster. That is, if the bit string output from the shifter contains 1s, the number of 0s lower than 1 in the bit string is used as the initial value of the accumulator, and the expected value is output next from the shifter. It accumulates the number of 0s from the upper side of the bit string.

In FIG. 9, reference numeral 23 denotes another priority encoder.
, And the number of 0s from the lower side is obtained from the input bit string as shown in the truth table of FIG. The output of the 1-containing signal is performed by another priority encoder 23 instead of the priority encoder 2 of the first embodiment. The two priority encoders 2 and 23 constitute detection means.

The accumulator (accumulation means) 3 'is a selector 2 in addition to the adder 4 and the 3-bit register 6 of the first embodiment.
4, and the control unit 20 'also constitutes a part of the accumulator 3'. The selector 24 is a two-input one-output type,
The two inputs are the output of the adder 4 and the output of the other priority encoder 23, and the output is input to the 3-bit register 6. The control unit 20 '
When no 1-containing signal is received, the output of the adder 4 is selected. When a 1-containing signal is received, the output of the other priority encoder 23, that is, the number signal of 0 from the lower side is selected. This number signal is stored in the register 6 and set as an initial value.

The control unit 20 'adds the set bit number signal (= 4 bit signal) when the header detection signal is not received regardless of whether or not the 1-containing signal is received, and adds +1 when the header detection signal is received. After receiving the header detection signal from the addition result of the decoder 17 (after activation of the decoder), the selector 18 is controlled so as to select the code length from the decoder 102, respectively. Since other configurations are the same as those of the first embodiment, the same portions are denoted by the same reference numerals and description thereof will be omitted.

Next, the operation of this embodiment will be described with reference to FIGS.
A description will be given based on the timing chart of FIG. FIG. 11 shows an operation example in which the comparator 10 outputs a 0 satisfaction signal to detect a header code, and FIG. 12 shows an operation example in which a carry occurs in the adder 4 and a header code is detected.

Referring to FIG. 11, a case where the code string is as shown in FIG. The selector 18 selects and outputs the set code length signal (4-bit signal) under the control of the control unit 20 'until the header detection signal is output.

In the first time, the shifter 1 outputs the bit string “000”
"0" is output. As a result, the two priority encoders 2 and 23 each output a count signal “4” of 0, and the encoder 23 does not output a 1-containing signal. At this first time, the register 6 is reset to an initial value (= 0).

At the second time, shifter 1 outputs the next bit string “1000”. Therefore, the priority encoder 2 outputs the number signal “0” of 0, and the other encoders 23 output the number signal “3” of 0 and also outputs the 1-containing signal. The selector 24 of the accumulator 3 'is set to 1
The output of the adder 4 (previous high-order 0 number signal "4") is selected by the non-output of the content signal (that is, 1 content signal = 0), and the register 6 stores the 0s from the high-order side. Since the number signal “4” is stored, the adder 4 accumulates the previous number signal “4” of 0 from the upper side and the current number signal “0” of 0 from the upper side, and accumulates 0. Is obtained. The comparator 10 outputs the accumulated number signal “4” and the set value (=
7), no 0 satisfaction signal is output, and therefore the first AND circuit 12 does not output the header detection signal.

At the third time, the shifter 1 outputs the next bit string “0010” (0 in the fourth bit is 0 located at the head of the header code). Accordingly, the priority encoder 2 outputs the number signal “2” of 0, and the other encoders 23 output the number signal “1” of 0 and also outputs the 1-containing signal. The selector 24 of the accumulator 3 'selects the output of the other encoder 23 (previous lower-order 0 number signal "3") by the output of the previous 1-containing signal, and the register 6 stores Since the number signal “3” is stored, the adder 4 stores the number signal “3” of 0 from the previous lower side and the number signal “2” of 0 from the upper side this time.
And an accumulated number signal “5” of 0 is obtained. Comparator 1
0 does not output the 0 satisfaction signal by comparing the accumulated number signal "5" with the set value (= 7).
Does not output a header detection signal.

At the fourth time, the shifter 1 outputs the next bit string “0000” (0 of the second to fifth bits of the header code). Both priority encoders 2, 2
3 both output the number signal “4” of 0, and the other encoders 23 do not output the 1-containing signal. The selector 24 of the accumulator 3 ′ selects the output of the other encoder 23 (the previous lower-number signal “1” of 0) from the output of the previous 1-containing signal, and the register 6 sets the number signal “1”. Since the "1" is stored, the adder 4 accumulates the previous number signal of "0" from the lower side and the current number signal of "4" from the upper side. An arithmetic signal "5" is obtained. The comparator 10 does not output the 0 satisfaction signal as in the fourth time, and the first AND circuit 12 does not output the header detection signal.

At the fifth time, the shifter 1 outputs the next bit string “0010” (0th bit of the sixth to eighth bits of the header code).
01 and subsequent 0) are output. Accordingly, the priority encoder 2 outputs the number signal “2” of 0, and the other encoders 23 output the number signal “1” of 0 and also outputs the 1-containing signal. The selector 24 of the accumulator 3 'selects the output of the adder 4 (accumulated number signal "0" of 0 on the high-order side) based on the previous non-output of the 1-containing signal (1-containing signal = 0). Since the register 6 stores the total number signal "5", the adder 4 outputs the accumulated number signal "5" of 0 from the previous upper side and the number signal "2" of 0 from the current upper side. Are added to obtain an accumulated number signal “0” of 0. The comparator 10 outputs the accumulated number signal “0” of “0” and the set value (=
7) and outputs a 0 satisfaction signal. The first AND circuit 12 receives the 0-satisfaction signal from the comparator 10 and the 1-containing signal from the other encoder 23, and outputs a header detection signal. Is output to

In FIG. 12, the operation of each component is shown in FIG.
1 (when the comparator 10 outputs a 0 satisfaction signal), except that the accumulated number signal of 0 is equal to the set value (=
7), the adder 4 generates a carry signal and the 1-bit register 11 holds the output of the carry signal.
The second AND circuit 13 outputs a header detection signal, and the detection signal is input to the decoder 102 via the OR circuit 14. Therefore, a detailed description of the operation in FIG. 12 is omitted.

Therefore, in the present embodiment, the header code can be detected five times (five clocks) as shown in FIGS. 11A and 12A, so that the header code is further reduced by one compared with the first embodiment. The header code can be detected faster with a clock, and the detection speed can be further improved.

In the first and second embodiments, the adder 4
Is provided, a 1-bit register 11 for holding the carry signal is provided. Instead, the adder 4 is configured to be capable of adding a sufficiently large value (for example, 15), and the result of the addition is The configuration may be such that the comparator 10 outputs a zero satisfaction signal when the result of addition is greater than or equal to the set value (= 7).

Further, in the first and second embodiments, all the components are constituted by hardware, but it is needless to say that a part or all of the components may be constituted by software.

In addition, it goes without saying that the header detector of the present invention is not limited to a decoder and may be used for other devices.

[0071]

As described above, according to the header detector of the first to third aspects of the present invention, the output of the code string by a plurality of bits is repeated, and the higher order of the output plurality of bits is repeated. Since the number of consecutive 0s is accumulated from the side and the following 1 is detected, the components of the header detector are faster than the conventional case where 0 or 1 is detected for each bit. It is possible to speed up the detection of the header code without requiring an operation.

Further, according to the header detector of the present invention, the output of the code string by a plurality of bits is repeated, and from the upper side and the lower side of the output plurality of bits. Since the number of consecutive 0s is accumulated and the following 1 is detected, the components of the header detector are faster than the conventional case where 0 or 1 is detected for each bit. It is possible to speed up the detection of the header code without requiring an operation. Also, since the number of consecutive 0s can be accumulated using the number of 0s following 1 as an initial value in the plurality of output bits, the number of consecutive 0s can be increased as compared with the header detector according to any one of claims 1 to 3. Further, the speed of header detection can be further increased.

Further, according to the decoding apparatus of the present invention, the code decoded by the decoder is shifted out by the header detector in one clock, so that the code is next written to the decoder. Input can be made with a clock, and as a result, the decoding operation of the decoder can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a decoding device according to a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a buffer according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram showing an outline of a code string in MPEG.

FIG. 4 is a configuration diagram showing an outline of a code string in the first embodiment of the present invention.

FIG. 5 is a schematic configuration diagram of a decoder according to the first embodiment of the present invention.

FIG. 6 is a configuration diagram of a header detector according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a truth table of the priority encoder according to the first embodiment of the present invention.

FIG. 8 is a time chart illustrating the operation of the header detector according to the first embodiment of the present invention.

FIG. 9 is a configuration diagram of a header detector according to a second embodiment of the present invention.

FIG. 10 is a diagram showing a truth table of another priority encoder according to the second embodiment of the present invention.

FIG. 11 is a time chart illustrating a header code detection operation based on an operation of a comparator of a header detector according to the second embodiment of the present invention.

FIG. 12 is a time chart illustrating a header code detecting operation based on the output of a carry signal of an adder of a header detector according to the second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Shifter (shift means) 2 Priority encoder (detection means) 3, 3 'Accumulator (accumulation means) 4 Adder 6 Register 10 Comparator (comparison means) 11 Register 12 First AND circuit (output means) 13 Second AND Circuit (Other Output Means) 14 OR Circuit 17 +1 Adder 18 Selector 20, 20 'Control Unit 21 Shift Amount Setting Means 23 Other Priority Encoder 24 Selector 101 Header Detector 102 Decoder

Claims (14)

(57) [Claims] Symbol 1. A shift means for inputting a code string and sequentially outputting the input code string for each bit string of a plurality of bits, a bit string output from the shift means being input, and Detecting means for outputting a signal indicating the number of consecutive 0's, detecting whether or not there is 1 in the input bit string, and outputting a signal as a result; An accumulating means for accumulating a continuous number, inputting the accumulating result of the accumulating means, comparing the accumulating result with a set value corresponding to a header code to be detected, and outputting a signal of the comparison result. A header detector comprising: comparing means for outputting; and outputting means for outputting a header detection signal based on a comparison result signal of the comparing means and a detection result signal of the detecting means. 2. A signal from a higher-order side indicated by a signal from a detecting means is 0.
And a shift amount setting means for setting a shift amount of the shift means, wherein the shift amount setting means outputs a detection result signal having no 1 from the detection means. 2. The header detector according to claim 1, wherein the set number of bits is an increment of the shift amount, and when the detection means outputs a detection result signal having one, the addition result of the +1 adder is an increment of the shift amount. . 3. The accumulating means comprises a register for storing an initial value, and an adder for adding the number of consecutive 0's from the upper side indicated by a signal from the detecting means to the initial value stored in the register. 2. The header detector according to claim 1, wherein: 4. A shift means for receiving a code string and sequentially outputting the input code string for each bit string having a plurality of bits, a bit string output from the shift means being input, and Detecting means for outputting a signal indicating the number of consecutive 0's and a signal indicating the number of consecutive 0's from the lower side, detecting whether or not there is 1 in the input bit string, and outputting a result signal; Accumulating means for receiving a signal from the means and accumulating the number of consecutive 0's from the upper side; inputting the accumulation result of the accumulating means, the accumulation result corresponding to a header code to be detected Comparing means for outputting a signal indicating the result of the comparison, and outputting means for outputting a header detection signal based on the comparison result signal of the comparison means and the detection result signal of the detection means. Means, as an initial value, from the upper side when receiving the detection result signal 1 is not in the bit sequence from said detection means 0
Characterized in that when the detection result signal having a bit string of 1 is received from the detection means, the number of consecutive 0s from the lower side indicated by the signal from the detection means is used. vessel. 5. A signal from a higher-order side indicated by a signal from the detecting means,
And a shift amount setting device for setting a shift amount of the shift means, wherein the shift amount setting device sets the number of set bits when the header detection signal from the output means is not output. 5. The header detector according to claim 4, wherein is the increment of the shift amount, and when the header detection signal is output from the output means, the addition result of the +1 adder is the increment of the shift amount. 6. A detecting means for receiving a bit string output from the shift means, a priority encoder for outputting a signal indicating the number of consecutive zeros from the upper side of the bit string, and a bit string output from the shift means. And outputs a signal indicating the number of consecutive 0's from the lower side of the bit string, and detects whether or not the input bit string has 1's, and outputs another signal to the priority encoder. The header detector according to claim 4, characterized in that: 7. An accumulating means, comprising: a register for storing an initial value; an adder for adding the number of consecutive zeros from the upper side indicated by a signal from the detecting means to the initial value stored in the register; 0 from the output of the adder or the lower side from the detection means
And a control unit for controlling the selector by selecting a number signal of successive numbers, and receiving the detection result signal from the detection unit, and adding the detection result signal when there is no 1 in the bit string. to select the output of the vessel, to select the number signal 0 is continuous from the lower side of the detecting means can there is a one in the bit string, the header of claim 4, wherein the controller controls the selector Detector. 8. The comparing means outputs a coincidence signal as a comparison result signal when an accumulation result of the accumulation means is equal to a set value corresponding to a header code to be detected. The header detector according to claim 1 or claim 4. 9. The output unit according to claim 1, wherein the output unit outputs a header detection signal when receiving a coincidence signal from the comparison unit and a detection result signal from the detection unit. Header detector. 10. The adder of the accumulating means outputs a carry signal when the addition result exceeds a set value corresponding to a header code to be detected, and holds the carry signal of the adder. 8. The header according to claim 3, further comprising: a register that outputs a header detection signal when an output of the register and one from the detection unit are received. Detector. 11. The header detector is connected to a decoder that decodes a code and outputs a code length signal of the decoded code, and a selector that constitutes a shift amount setting device is configured to operate after a start of the decoder. 6. The header detector according to claim 2, wherein a code length signal from the decoder is selected. 12. A code string is a standard MP of image compression coding.
5. The header detector according to claim 1, wherein the header is a bit string including a number of codes encoded based on the EG. 13. A header detector according to claim 1, and a decoder, the decoder activates the header detection signal from the output means of said header detector as an activation signal, wherein Start decoding the code output from the shift means of the header detector,
A decoding device for outputting a code length signal of the decoded code, wherein the shift means of the header detector sets the code length signal from the decoder as an increment of a shift amount. 14. A header detector according to claim 4, and a decoder, the decoder activates the header detection signal from the output means of said header detector as an activation signal, wherein Start decoding the code output from the shift means of the header detector,
A decoding device for outputting a code length signal of the decoded code, wherein the shift means of the header detector sets the code length signal from the decoder as an increment of a shift amount.