JPS60162391A - Sequence approximate vector quantizer - Google Patents

Abstract

PURPOSE:To obtain a sequence approximate vector quantizer which does not reproduce an unnatural picture when the picture changes rapidly by using tree search vector quantization for a vector quantization part and by controlling variably the number of steps. CONSTITUTION:By controlling variably the number of tree search vector quantization steps by a feedback control signal 45, a quantizer performs variable- length encoding. An encode controller 49 encodes codes corresponding to a zero vector, using a feedback control signal 45, zero vector detection signal 48, index i151, index i253 and index i355 as inputs when the input vectors are regarded as zero vectors. If the input vectors are not regarded as zero vectors, the encode controller 49 encodes any one of these i1, i2, and i3 as an output vector index basd on the control signal 45.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an interframe vector quantizer that performs highly efficient encoding of nine image signals by utilizing correlation in consecutive screens. .

[Prior art]

This type of interframe vector quantizer that has been proposed in the past has been constructed as shown in FIGS. 1, 2, 3, and 4. A specific example of the configuration of a conventional interframe encoding device will be described below with reference to FIG. FIG. 1 shows an encoder. In the figure, (1) is a digitized image signal, (
2) is a raster/block scan conversion unit that blocks the first image signal sequence (1) arranged in the raster scanning direction for each of a plurality of samples; (3) is a blocked image signal sequence;

(4) is a subtracter, (5) is a prediction error signal sequence of a blocked image signal, (6) is a motion estimation vector quantization encoder, (7) is a vector quantization encoding output, (8) is a vector quantization decoder, (9) is a vector quantization decoding output, that is, a reproduced prediction error signal sequence, and 0■ is an adder.

(11) is a block of the reproduced image signal sequence, +1
21 is a frame memory, a3) is a block of a reproduced image signal sequence delayed by one frame cycle, and a block of a predicted signal sequence for predicting block (3) of the 9 image signal sequence, (1a) is the transmission buffer, 061 is the feedback control signal, and 061 is the encoder output.
The figure shows in detail an example of the configuration of the vector quantization encoder (6). In the figure, (1η is an average value separation circuit,
(1~ is the amplitude normalization circuit, (Hj) is the inter-frame difference of the block of the image signal sequence normalized by the amplitude after separating the average value, (2G is the average calculated by the average value separation circuit aη) value, c!D is the amplitude calculated by the amplitude normalization circuit a81, @ is the average value (4) and the amplitude 1
A motion detection circuit that determines from 2D whether or not the blocked image signal sequence currently being processed has caused a significant change with respect to the block of the image signal sequence at the same position one frame period ago. , the threat is the determination result of the motion detection circuit, (24 is a code table address counter,
■ is the code table index, @ is the output vector code table memory, @ is the code table output vector.

(to) is a distortion calculation circuit, @ is a minimum distortion detection circuit, ■ is a signal indicating minimum distortion, and 61) is a transmission latch.

Further, FIG. 3 shows in detail an example of the configuration of the vector quantization decoder (8). In the figure, (3Z is the reception latch, 1331 is the amplitude reproduction circuit, +341 is the average value reproduction circuit. Also, Figure 4 is an example of the configuration of the decoder. A block/raster scan converter performs inverse processing of the meta/block scan converter (2), and @ is a reproduced image signal sequence.

Next, the operation will be explained. First, the general operation of the encoder will be explained along FIG. 1.

Basically, the concept of interframe DPCM method is used. The digitized image signal sequence (1) is as follows.

Although they are considered as a square grid of samples on the screen, the input is given in the order of the raster scanning direction. Raster/
The block scan converter (2) divides one image signal sequence (1) into blocks as shown in FIG. 5, and outputs the blocks as a unit. Now, in the f-th frame. A certain blocked image signal sequence (3) is expressed as a signal source vector
Let it be expressed as (81, 82, . . . -5k)f.

FIG. 5 shows an example where 2=4. Furthermore, the difference (5) between the signal source vector (3) calculated by the subtracter (4) and the block (131) of the predicted signal sequence is converted to εf, and the vector quantization encoder (6) and vector quantization decoding i(
, the block (11) of the reproduced image signal sequence is ΔSf, and the predicted signal sequence obtained as the output of the 7-frame memory is P.The rough operation of the encoder shown in FIG. 1 is as follows. It is expressed by the formula.

'f'5f-p.

However, Q represents a vector quantization error, and zf represents a delay of one frame period caused by zero frame memory. Therefore, Pf is an image at the same position of the signal source vector (3) and one frame period before, that is, the f-1th frame, the block of the image signal sequence> the reproduced signal sequence S of f-1,
be equivalent to. The vector quantization encoded output (7) obtained in the process is the difference between the signal source vector (3) and block a3 of the predicted signal sequence.

That is, the block εf(5) of the prediction error signal is data-compressed by the pectoquad encoder (6), and the output (7) is sent to the transmission buffer I, and the encoder output a
output to the transmission line as a uniform signal. Next, the operations of the vector quantization encoder (6) and vector quantization decoder (8) will be explained along FIGS. 2 and 3. Vector quantization considers a block composed of 2 samples (K: multiple) as an input vector in a 2-dimensional signal space, and calculates in advance that the distortion with the input vector is the minimum overall based on the probability distribution density of the input vector. From a set of output vectors prepared so that . On the decoding side, the output vector corresponding to the index may be read out from the set, which is also provided on the decoding side. Now, what is given as an input vector is a block of prediction error signal '(= ('x e '
21-*'k)f (6) ``6le.fmm diblock f (51 is the mean value division chick circuit (at 1η).

The average value μ(a) calculated by the following formula (% formula %) is subtracted, and the amplitude σc calculated by the linear formula (% formula %) in the amplitude normalization circuit positive! Normalized by D, mean-separated normalized input vector X=(X,,X2...,
Xk) (1!1 is formed, ie.

Xj ” (g j-μ)/a (j= 1.2...
. . , K) . . . Deflection (4) In addition to the above-mentioned method, other methods for calculating the amplitude can be considered. By performing the mean value separation normalization process, the input vectors can be randomly distributed within a certain limited range of the dimensional signal space, and the efficiency of vector quantization is improved.

When performing the same processing, a set of output vectors must also be prepared based on the distribution of the input vectors that have been subjected to mean value separation and normalization processing, and after reading the output vectors on the decoding side, the average It is necessary to perform inverse processing of value separation normalization. Of course, vector quantization without performing the same processing may also be used. In the code table memory (to), mean value separation normalization is prepared in advance based on the probability distribution density of the mean value separation normalization input vector so that the distortion with the mean value separation normalization input vector is minimized overall. Output vector is written. Now, given the mean-separated normalized input vector X+191.

The code table address kakunta (to) sequentially outputs the index of the vector stored in the code table memory □□□, that is, the code table address 4, and separates the average value from the code table memory and normalizes the output vector 1T.
= (Yil t)'T21...* 3'y, 0
(τ is the index) Read @. Distortion calculation circuit (to)
Now, the distortion between the mean value separated normalized input vector Let the strain be d(X, y,).

d (X, yr) = mBg Xj, rj When the minimum distortion detection circuit line sequentially calculated '(Xy yr) is smaller than the past minimum distortion, a strobe signal ■ is output. At the same time, latch cD captures the index. At the stage when the code table address counter (to) has output all the indexes once, the latch Gll stores the index i of the mean-separated normalized output vector that causes the minimum distortion for the mean-separated normalized input vector. has been done. The index, average value μ(a), and amplitude σf211 are vector quantized encoded outputs, and data compression is further performed using the correlation between consecutive screens. The input vector is a blocked prediction error signal.

The distribution will be centered around the zero vector. Therefore.

By setting a threshold value of 0, input vectors close to zero vectors are regarded as zero vectors, and the index, average value, and amplitude are not sent, the amount of data can be greatly reduced. In the motion detection circuit, the average value μ and the amplitude σ sequence are input.

It is determined whether a block of the prediction error signal sequence can be regarded as a zero vector, that is, whether a significant change (movement) has occurred in the block compared to one frame cycle ago. As a method, for example, if the threshold value is To, it is determined that there is no movement if μ≦Tθ and σ≦Tθ, and there is movement if μ>To or σ>To. Therefore, in the latch c111, the motion detection result (to) is "
If the result is a code of "no movement", only the signal indicating "no movement" is sent, and if the result is a code of "motion foot", it is added to the signal indicating "movement foot".

The average value (4)) and amplitude (21) of the index are respectively output as vector quantization encoded outputs (7). Transmission buffer (in other words, it monitors the amount of information to be transmitted).

The feedback control signal (151 sets the threshold value Tθ
This allows the amount of information to be transmitted to be controlled. In the vector quantization decoder (8), the latch (3) receives the vector-subset encoded output (7) and
When a signal of
11, and an average value ■ is added in the average value reproduction circuit 0a, and an output vector, that is, a reproduced prediction error signal sequence 1t(9) is output. Namely.

仝=σ・Yrj1μ(3=x、2．・・・、K)・
- (7) When a signal of "no movement" is received, the latch (3I) outputs 0 as the average value (4) and amplitude [21+, and at this time, the output vector becomes a zero vector. Next, the operation of the decoder will be explained with reference to FIG. The receiving buffer (341) receives the encoder output (161) and decodes the vector quantized encoded output signal (7).

The vector quantization decoder (8) decodes the output vector, that is, the prediction error signal sequence εf (9) as described above, and uses the adder (11, frame memory Qz to generate a block Sfaυ of the reproduced image signal sequence as shown in the following equation) Play.

8-, )-+81 where Q represents a vector quantization error and Z represents a delay of one frame period. The block/raster converter c16+ scan-converts the block-shaped reproduced image signal sequence 5f (1υ) in the raster scanning direction to obtain a reproduced image signal sequence node.

The conventionally proposed 7-frame vector quantizer is based on the above configuration, so when the 9 images change drastically, the threshold To is set to a large value in order to stabilize the amount of information to be transmitted. However, as a result, some blocks may remain in the same state as the previous screen, and the boundaries between blocks are conspicuous.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventionally proposed methods such as 9 and above, and uses tree search vector quantization in the vector quantization section.

In other words, by variably controlling the number of stages and controlling the amount of data to be transmitted by feedback, we have created a vector quantum that does not produce an unnatural reproduced image even when the image suddenly changes. The purpose is to provide a

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. First, consider the simple binary tree shown in FIG.

The root of the tree corresponds to a two-dimensional signal space Rk, and each node corresponds to a space obtained by dividing Hk in stages. A representative point is determined for each representative point, and the representative point becomes a dimensional output vector. The output vector of each stage is generated based on the distribution of input vectors so that the sum of distortions between input and output vectors is minimized. That is, the stepwise division described above is performed based on the distribution of input vectors in Rk.

When an input vector is given, 9 from the first stage to the final stage
By comparing the distortion with the output vector corresponding to the two branching nodes and selecting the branch with the smaller distortion, the output vector corresponding to the terminal node is selected. If the final stage is the n-th stage, there are 2n terminal nodes. In Figure 6, n =
Three examples are shown.

The above is tree search vector quantization (TSVQ: Tree 5
searchVector Quantization
). FIG. 7 shows an example of the configuration of an encoder according to the present invention. In the figure, (1) is a digitized image signal sequence, (2) is a raster/block scan conversion unit, (3) is a blocked image signal, (4) is a subtracter, and (5) is a prediction error. A block of signals, C (81 is a T8VQ encoder based on the above principle, @ is a TSVQ
Encoded output, (41 is TSVQ decoder, (411 is T8VQ decoded output, flol is adder, +42J is block of reproduced image signal, 07J is frame memory.

(431 is the frame memory (a block of predicted signals obtained as one output), (441 is a transmission buffer,
(451 is the feedback control signal, +46J is the encoder output.

In addition, FIG. 8 shows a detailed configuration example of the TSVQ encoder (381). In the figure, (4η measures the distance between the input vector and the origin, and If so, a limiter that quantizes to a zero vector.

(481 is the zero vector detection signal that is output when the input vector is quantized to a zero vector in the limiter (4η), +491 is the encoding control unit, B is the first stage of the TSVQ encoder, and 611 is the T8VQ encoder The output vector index, 6z, at the stage of searching up to the first stage ■ is T
The second stage of the SVQ encoder is the second stage of the TSVQ encoder.
Stage (output vector index up to the stage of searching up to 5z, (goods) is the third stage of the TSVQ encoder, +551 is the output vector index at the stage of searching up to the third stage 641 of the TSVQ encoder. FIG. 9 shows an example of the configuration of the second stage 4521 of the TSVW encoder in more detail. In the figure, @ indicates the second stage output vector code table memo!J, (571 indicates a parallel distortion calculation circuit).

Regarding the distortion comparator circuit 9, a signal representing the comparison result in the distortion comparator circuit (581), (601 is an index register), and FIG.
0) shows a configuration example. In the figure, @1) is the index latch, and the link is the output vector index.

The link is an output vector code table memory.

Further, FIG. 11 shows an example of the configuration of a decoder according to the present invention. In the figure, ((goods) is the reception buffer.

explain about.

The digitized image signal sequence (1) is samples given in order in the raster scanning direction. The raster/block scan converter (2) divides the image signal series into blocks (K is a plurality of blocks, and performs scan conversion in the order in which these blocks are units. Now, a certain block image signal in the f-th frame The sequence (3) is converted into a signal source vector Sr=
Let it be expressed as (81, 82,..., 5k)r.

Furthermore, the signal source vector (
3) and the predicted signal block size (5), e t
, TSVQ encoder (2) and TSVQ decoder C1
91, that is, a block of the reproduced prediction error signal (411 is εf), a block of the reproduced image signal (421 is Sf, the reproduced image signal delayed by one frame period by the frame memory α2) The block (43) of the predicted signal obtained as a block of P
Assuming that f is the basic operation of the encoder shown in FIG. 7, it is expressed by the following equation.

However, Q represents a vector quantization error, and 2-1 represents a delay of l frame period due to frame memory α. Basically, it is a DPCM method between frames.

The TSVQ encoded output (to) is sent to the transmitter port 7a.

The transmission buffer 441 monitors the amount of transmitted information and outputs the encoded output (461) to the transmission path.
control the amount of encoded data in (to). The control will be explained with reference to the TSVQ encoder and TSVQ decoder and decoder in FIGS. 8, 9, and 10. Now, the output vector Sera)Y has the binary book structure as shown in Figure 6.
It's a game. In Y, the vectors belonging to each stage are generated in advance based on the distribution of the input vectors so that the sum of distortions to the input vectors is minimized. Tree search vector quantization is a process of performing a distortion comparison between two output vectors and an input vector that are bare in each stage, and determining a bear to be compared in the ninth stage. The distortion comparison of the three stages of the tree shown in FIG.
'4 is associated with the third stage encoder (goods). What is now given as the input vector is block 'ff51 of the prediction error signal. The limiter (4η is the input vector (
5) and the origin (zero vector), and if it is less than a predetermined threshold, the input vector (5) is regarded as a zero vector, and a zero vector detection signal (481) is output. That is, If the distortion between the threshold value Tθ, the input vector εf, and the zero vector 0 is expressed by d(εf, o), then if d(2f, standing)<Tθ, then e(−仝・・・・・・・・・
. . . (lO) If the distortion is greater than the threshold, the input vector (5) is sent to the first TSvQ encoding encoder. Although various definitions of distortion can be considered, a few examples are shown below. Generally, the distortion of vector a and vector b is expressed as d(a, b
).

d(a, b)=mlx jaj−bjl etc. However, soil = (aI+82+”'+akL!j=(b1+b2
s''+blO Here, the input vector (5) that is not considered to be a zero vector is quantized as a tree search vector in the first to third stages of the T8VQ encoder. Calculate the distortion between the input vector and the output vector to determine the one with the smaller distortion, add that information to the comparison results up to the previous stage, and send it to the first stage.In the first stage, the output vector Since only one bear is off, the comparison results up to the previous stage are not necessary and do not exist.

If the distortion comparison result in the first stage is i, 51), @2
The stage calculates the distortion between the input vector and the output vector determined by 11, and adds the distortion comparison result to 11 to form 12. In the third stage, 12 and input vector ε
Given f, it outputs index i3. For example, if you select the technique on the left as shown in Figure 6, 0. Suppose that if you select the technique on the right side, 1 will be assigned.

ils '2+ +3 are 1-digit, 2-digit, and 3-digit 2, respectively.
The base number sequence corresponds to the index of the output vector. In the encoder according to the present invention, the number of stages of tree search vector quantization is variably controlled by the feedback control signal (phrase), and variable length encoding is performed.

That is, in the encoding control unit (4!1), when the feedback control signal, zero vector detection signal +481, index i, 611, and index t2at-index+3f are input, the input vector is considered to be a zero vector. encodes the code corresponding to the zero vector. If the input vector is not considered to be a zero vector, the feedback control signal (based on the phrase “1* '2e '3) is encoded as the output vector index. In other words, when there is sufficient feed path in each stage, the output of the final stage is encoded.

The closer to the first stage, the less information will be output.

As described above, the amount of information to be encoded can be controlled.

FIG. 9 shows a second example of the structure of the TSVQ encoding encoder. The second stage output vector code table memory mark stores output vectors corresponding to the second stage of the output vector cella)Y, and outputs a pair of output vectors specified by the index (5I) of the previous stage. The parallel distortion calculation circuit (5?l) performs distortion calculations between the input vector (5) and the bare output vector.

The distortion comparator circuit compares the two and outputs the comparison result as a signal (53).There are several distortion calculation methods as explained above in the limiter (47). index 61 of
), the second stage distortion comparison result is added to output the second stage index [stock]. The operations of the first and third stages are almost the same. The difference is that an output vector group corresponding to each stage is written in each output vector code table memory, and that the first stage does not have an index up to the previous stage. TSVQ decoder (40
Output vector code table memory included in 1
All output vectors and zero vectors belonging to the output vector cell (output vector cell) Y are stored. The index latch decodes the zero vector code or output vector index based on the T8VQ encoded output G9),
TSVQ from the output vector code table memory
Read the decoded output (41). Next, the operation of the decoder according to the present invention will be explained with reference to FIG. a receiving buffer receives the encoder output (461);
Decode the TSVQ encoded output □□□.

The TSVQ a encoder+41 generates the output vector as described above.

5(-Pf+ε(=8(+Q), where Q is the vector quantization error, 2-1 is the delay of one frame period caused by the frame memory (1), and εf is the delay of the reproduced prediction error signal obtained as the output vector. The block/raster converter (to) scan-converts the blocks S and f4 of the converted reproduced image signal in the 2-star scanning direction.

A reproduced image signal sequence (651 is obtained. In this explanation, three stages of main search vector quantization are taken as an example, but in reality, other stages (generally, it becomes multiple stages) may be used. Of course not.

〔Effect of the invention〕

As described above, this invention (according to the present invention) controls the amount of data by variable control of the number of stages of tree search vector quantization. A more natural reproduced image can be provided without increasing the portion that is left and giving an unnatural reproduced image.

The invention has a wide range of applications in television transmission, but particularly in interframe coding as a qualifier.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an encoder of a conventionally proposed interframe vector quantizer; Fig. 2 is a block diagram of a vector quantization encoder of a conventionally proposed interframe vector quantizer; Figure 3 is a block diagram of a vector quantization decoding unit of a conventionally proposed interframe vector quantizer, Figure 4 is a block diagram of a decoder of a conventionally proposed interframe vector quantizer, and Figure 5 is a block diagram of a decoder of a conventionally proposed interframe vector quantizer. FIG. 6 is an explanatory diagram explaining blocking of an image signal sequence, FIG. 6 is an explanatory diagram explaining tree search vector quantization, and FIG. 7 is an example of an encoder in a successive approximation vector quantizer according to the present invention. Configuration diagram, No. 8
The figure is a block diagram of an embodiment of the TSVQ encoder in the sequential approximation vector quantizer according to the present invention, and FIG. 9 is the TSVQ encoder in the sequential approximation vector quantizer according to the present invention.
FIG. 10 is a block diagram of an embodiment of the TSVQ decoder in the successive approximation vector quantizer by Akira Koko, and FIG. 11 is a block diagram of an embodiment of the second stage of the encoder. FIG. 2 is a configuration diagram of an embodiment of a decoder in a second-order approximate vector quantizer. In the figure, ll+31 is an image signal sequence, and (2) is a raster/
Block scan conversion unit, (4) is a subtracter, (5) is a prediction error signal sequence block, (6) is a motion estimation vector quantization encoder, (7) is a vector quantization encoding output, (8
) is a vector quantization decoder, (9) is a vector quantization encoded output, (1G is an adder, al) is a block of a reproduced image signal sequence, (1z frame memo! J, (+3
) is a block of the predicted signal sequence, a41 is a transmission buffer, (19 is a feeder, a block control signal, (161 is an encoder output signal, (171 is an average value separation circuit, a decoy is an amplitude normalization circuit, and Q!I is a Average value separation normalized input vector, ■ is the average value, t2n is the amplitude. The 9 examples of displacement motion detection section are the motion detection section output signal, f24+
is the code table address counter, +25) is the index, (4) is the average value separation normalized output vector code table memory, @ is the code table output vector, @
is a distortion calculation circuit, (2g1 is a minimum distortion detection circuit, (10) is a minimum distortion detection strobe signal, 1311 is a transmission latch,
C12+ is the reception latch, (3 moats are the amplitude reproduction circuits, (3
41 is an average value reproduction circuit, (G) is a reception buffer, Cl6
1 is block/raster scan conversion unit, @ is reproduced image signal sequence, 0 mark is TSVQ encoding i, C19) is 'rsVQ
Encoded output, (4I TsVQ decoder, (411
'rsVQ decoding output Decoding output is a block of the reproduced image signal sequence, formerly a block of the predicted signal sequence. (44 is the transmission buffer, the signal is the feedback control signal. (461 is the encoder output, (4η is the limiter, (the root is the zero vector detection signal, f4!l is the encoding control unit, i5I
is the first stage of the TSVQ encoder, (5u is the first stage output vector index, (521 is the second stage of the TSVQ encoder, te3+ is the second stage output vector index, and is the third stage of the TSVQ encoder. , saliva is the 3rd stage output vector index, 671 is the 2nd stage output vector code table memory, 671 is the parallel distortion calculation circuit, and 9 is the distortion comparison circuit.
The mark is the distortion comparison result signal, (601 is the index register, +611 is the index latch, (6 is the output vector index. The symbol is the output vector' code table memo! ji641 is the reception buffer, (651 is the reproduced image signal sequence). Identical or corresponding parts in Figure 9 are indicated with the same reference numerals.To agent Masuo Oiwa.

Claims (1)

[Scope of Claims] A 7-frame memory capable of storing past image signals for at least one frame, a predicted signal based on a block-formed previous image signal sequence read out from the frame memory one frame period before. As. The current image signal sequence is divided into blocks (K is the difference between the block of the image signal sequence that has been grouped together into blocks and the block of the predicted signal. 9. A subtractor for calculating the block of the prediction error signal, A limiter that takes a block of the prediction error signal of the subtracter as an input vector and outputs a zero vector detection signal by considering the input vector as the input vector if the distortion between the input vector and the zero vector is less than a predetermined threshold; Including, the dimensional signal space Rk is divided into two stages in a tree configuration
Reverse the division and in the nth stage (n is a positive integer) 2
An output vector code table memory that stores representative points of each division of one signal space Rk as a set of output vectors, two output vectors prepared by dividing each stage into two, and the above human vector)/L A parallel distortion calculation circuit that calculates the distortion between the two output vectors and the input vector, a distortion comparison circuit that compares the distortion between the two output vectors and the input vector, and determines which one gives the smaller distortion, and a comparison result of the distortion comparison circuit. An index register stores an index corresponding to an address for reading out an output vector step by step according to the method, and updates the index each time the distortion comparison result of each stage is given; An encoding control unit that controls the amount of data by controlling the number of α stages and performs variable length encoding of the zero vector detection signal and the index. a second code table memory having the same contents as the output vector code table memory; a second code table memory that receives the variable length coded encoder output, decodes the zero vector detection signal and the index; a decoder that reads an output vector from a code table memory and outputs the output vector or a zero vector; a block of a reproduced prediction error signal obtained as an output vector signaled by the decoder; and a block of the prediction signal; . The frame memory includes an adder that calculates a reproduced image signal to be used as a past image signal by delaying the frame memory by one frame period, and a transmission buffer that controls the number of final stages by feedback control.