JP2874003B2 - High efficiency coding apparatus and coding method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency coding apparatus and a coding method for compressing the amount of additional data generated in block coding.

[Summary of the Invention]

The present invention relates to a blocking circuit for blocking input digital image data, a block coding circuit for coding pixel data in a block in accordance with a dynamic range of each block, and a block used in the block coding circuit. A detection circuit for detecting the maximum value of each additional code over a predetermined number of blocks, a determination circuit for determining the number of bits to be allocated to the additional code in a period of the predetermined number of blocks based on an output of the detection circuit, and an output of the determination circuit A change circuit for changing the number of bits of the additional code based on the data of the additional code by transmitting the output of the block encoding circuit, the additional code from the change circuit, and the bit number identification code from the decision circuit. Can compress the quantity.

[Conventional technology]

The present applicant has proposed an adaptive dynamic range coding (ADRC) as an encoding method for compressing the transmission data amount of image data.
g) is proposed. ADRC calculates a dynamic range, which is the difference between the maximum value and the minimum value of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Laid-Open No. This is the encoding that performs the conversion. Further, as described in Japanese Patent Application Laid-Open No. 62-92620, an adaptive coding apparatus that performs coding adaptive to a dynamic range with respect to a three-dimensional block formed from pixels in an area included in each of a plurality of frames is proposed. Have been. Further, as described in Japanese Patent Application Laid-Open No. 62-128621, a variable length encoding method in which the number of bits changes according to a dynamic range so that the maximum distortion generated when quantization is performed is constant. Proposed.

In these ADRCs, an additional code having the dynamic range information of the block, for example, a minimum value MIN and a dynamic range DR are generated together with a code signal (quantized code) corresponding to each pixel included in the block. The code is transmitted. FIG. 6 shows the structure of transmission data. One block of data is composed of the additional codes DR and MIN and the code signal of each pixel in the block. The length of the code signal of one block is constant when the number of allocated bits for quantization is fixed, and not constant when this is variable.

Further, the applicant of the present application has proposed hybrid coding combining orthogonal transform coding such as cosine transform and the above-described ADRC (Japanese Patent Application Nos. 62-270564 and 63-2452).
No. 27). In this hybrid coding, ADRC is applied by blocking each of the DC component coefficient data obtained by the cosine transform and the AC component coefficient data of the same order. Therefore, an additional code of the dynamic range DR and the minimum value MIN is generated for each block including the coefficient data. It is also possible to make encoding different between coefficient data of a DC component and coefficient data of an AC component. That is, the coefficient data of the DC component is encoded in the same manner as in the ADRC, and the coefficient data of the AC component is determined in accordance with the dynamic range DR.
N is not regarded as 0 and is not transmitted, and a bit number data code signal indicating the number of allocated bits is transmitted.

[Problems to be solved by the invention]

Since the additional code is generated for each block, a relatively large load is imposed on data compression. As a method of compressing the additional code of ADRC, the applicant of the present invention has previously described the additional code, the maximum value MAX, the minimum value MIN, and the dynamic range DR.
Are encoded by ADRC in the same manner as pixel data (see Japanese Patent Application Nos. 61-303452 and 61-307184).

The present invention differs from the previously proposed one in that additional code is compressed using statistical data of the additional code. That is, the dynamic range DR in ADRC
And the minimum value MIN is transmitted in 8 bits each,
Due to the correlation of the images, the maximum value of the dynamic range DR may be 127 or less throughout one frame period, and the same may be applied to the minimum value MIN. If these maximum values are 127 or less, 8 bits
There is no problem even if shortened to a bit.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a high-efficiency encoding apparatus and an encoding method in which the compression efficiency is further improved by removing redundant portions of additional codes generated in block encoding.

[Means for solving the problem]

The present invention provides a blocking circuit (2) for blocking input digital image data, and a block coding circuit (3, 3) for coding pixel data in a block in accordance with a dynamic range of each block.
5, 6, 7) and a detection circuit (9) for detecting the maximum value of the additional code DR, MIN for each block used in the block coding circuit (3, 5, 6, 7) over a predetermined number of blocks. A decision circuit (10) for determining the number of bits to be allocated to the additional codes DR and MIN for a predetermined number of blocks based on the output of the detection circuit (9); and the additional code DR based on the output of the decision circuit (10). , MIN
A change circuit (11) for changing the number of bits of the output code DR, the output code DR of the block coding circuit (3, 5, 6, 7), the additional codes DR and MIN from the change circuit (11), and the decision circuit (1).
This is a high-efficiency encoding device that transmits the bit number identification codes DRn and MINn from 0). Further, the present invention is an encoding method for performing high-efficiency encoding as described above.

[Action]

Dynamic range DR of all blocks in one frame period
And the maximum value of the minimum value MIN is detected. From this maximum value D
Numbers n1 and n2 of bits allocated to R and MIN are determined. The dynamic range DR and the minimum value MIN are changed to the bit numbers n1 and n2. The additional codes DR and MIN with the changed number of bits, the code signal DT, and the identification codes DRn and MINn for identifying the number of bits are transmitted. The data amount of the additional code can be compressed, and the compression efficiency can be improved.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. In FIG. 1, the input terminal indicated by 1 is connected to 1
Digital video data in which the sample is digitized to 8 bits is supplied. The video data is converted by the blocking circuit 2 from a scan line order to a block order. A screen of one frame or one field is subdivided into blocks of a size such as (4 × 4 = 16 pixels) and (8 × 8 = 64 pixels).

The output signal of the blocking circuit 2 is supplied to the maximum and minimum value detection circuit 3 and the delay circuit 4. The detection circuit 3 detects the maximum value MAX and the minimum value MIN of the block. The delay circuit 4 delays data for a time for detecting the maximum value MAX and the minimum value MIN. The calculation of (MAX−MIN) is performed in the subtraction circuit 5, and the dynamic range DR is obtained from the subtraction circuit 5.
The subtraction circuit 6 subtracts the minimum value MIN from the video data from the delay circuit 4 and removes the minimum value from the subtraction circuit 6 to obtain normalized video data.

The output data of the subtraction circuit 6 and the dynamic range DR are supplied to the quantization circuit 7. From the quantization circuit 7, a code signal DT having a bit number smaller than the original bit number (8 bits), for example, 4 bits is obtained. The quantization circuit 7 performs quantization adapted to the dynamic range DR. That is, the quantization step Δ obtained by equally dividing the dynamic range DR into (2 ⁴ = 16)
Then, the video data from which the minimum value has been removed is divided, and the value obtained by rounding down the quotient to an integer is used as the code signal DT. The quantization circuit 7 can be constituted by a division circuit or a ROM.

Dynamic range DR and minimum value MI as additional codes
These are written to the memory 8 to compress N. The minimum value of each of the dynamic range DR and the minimum value MIN of all the blocks of one frame stored in the memory 8 is detected by the maximum value detection circuit 9. The detected maximum values are supplied to the bit number determination circuit 10, and the bit number n1 of the dynamic range DR and the bit number n2 of the minimum value MIN are each determined. For example, if the maximum value of the dynamic range DR of one frame is 127, it is set to (n1 = 7 bits). Regarding the minimum value MIN, the bit number n2 is similarly determined. Of course, when the maximum value is 128 or more, the bit number n1 or n2 is 8 bits equal to the original bit number.

An identification code corresponding to these bit numbers n1 and n2, respectively.
DRn and MINn are formed by the bit number determination circuit 10. An identification code DR for identifying 1 to 8 bits
n and MINn are 4-bit codes. When the bit numbers n1 and n2 are determined, in the bit processing circuit 11, the bit number of the dynamic range DR is changed from 8 bits to n1 bits, and the bit number of the minimum value MIN is changed from 8 bits to n2 bits. The number of bits can be changed by simple processing excluding the bit to be compressed (bit of “0”) from the most significant bit.

The code signal DT from the quantization circuit 7 is supplied to the framing circuit 13 via the delay circuit 12. The delay circuit 12 delays the code signal for one frame period required for determining the bit numbers n1 and n2. The dynamic range DR and the minimum value MIN from the bit processing circuit 11 and the identification codes DRn and MINn from the bit number determination circuit 10 are supplied to the framing circuit 13. Transmission data is extracted from an output terminal 14 of the framing circuit 13. The framing circuit 13 encodes an error correction code as needed.

In the transmission data, as shown in FIG. 2, the 4-bit identification codes DRn and MINn generated for each frame are located at the head of the transmission data for one frame, and thereafter the data of each block is located. The example of FIG. 2 shows the case of (n1 = 7 bits, N2 = 8 bits). When the total number of blocks in one frame is, for example, 5,000, the data amount of (5,000 × 1− (4 × 2) = 4,992 bits) can be reduced in the example of FIG.

When the dynamic range DR or the minimum value MIN can be expressed by 4 bits or less, it is considered that the number is extremely small.
You may make it identify from bit to 8 bits.
Further, the compression processing of the dynamic range DR and the minimum value MIN may be performed for each area obtained by dividing the screen of one frame into several parts.

Next, another embodiment in which the present invention is applied to hybrid coding that combines cosine transform and ADRC, which is one of orthogonal transform coding, will be described.

In FIG. 3, a digital video signal from an input terminal indicated by 21 is supplied to a blocking circuit 22, and the order of the input digital video signal is changed to a block mechanism for cosine conversion. For example, an image of one frame is (4 ×
It is divided into 4) small blocks.

The output signal of the blocking circuit 22 is supplied to a cosine transform circuit 23, which performs two-dimensional cosine transform. From the cosine transform circuit 23, a (4 × 4) coefficient table corresponding to the block size of the cosine transform is obtained. Of course, the size of the cosine transform block is not limited to this. FIG. 4A shows a (4 × 4) coefficient table obtained from the cosine transform circuit 23. In FIG. 4, DC indicates a DC component, and AC1, AC2,
... AC15 indicates an AC component. The coefficient table is transmitted in a sequence in which each coefficient data is arranged in a zigzag scanning order starting from a DC component.

In the two-dimensional cosine transform, a sampled discrete image signal f (j, k) is subjected to processing represented by the following equation by a cosine transform circuit 23. However, as for the original data, one block has two-dimensional data f (j, k) (j, k = 0,
1, ..., N-1).

The coefficient data from the cosine conversion circuit 23 is supplied to the distribution circuit 24. The distribution circuit 24 separates and outputs a total of 16 pieces of coefficient data of a DC component DC and an AC component of the same order (same order). For each frame, each coefficient data from the distribution circuit 24 is supplied to each of the reblocking circuits 25A to 25P. FIG. 3 shows a configuration relating to the coefficient data DC of the DC component and a configuration relating to the coefficient data AC15 of the AC component. The configuration of the AC coefficient data AC1 to AC14 of the other AC components is the same as that of the AC coefficient data AC15.

As shown in FIG. 4B, the re-blocking circuits 25A to 25P have the coefficient table shown in FIG. 4A (4 × 4 = 16, 16 ×
(16 = 256 data) A block composed of the same coefficient data included in the collected enlarged block is formed. In FIG. 4B, a, b, c,... P indicate spatially close coefficient tables, respectively. For example, the reblocking circuit 25A, as shown in FIG. 4C, stores the DC component coefficient data DC included in each of the 16 coefficient tables a to p.
Form data of a block structure consisting of a to DCp.

The output data of the reblocking circuit 25A is ADRC encoder 2.
Supplied to 6A. The ADRC encoder 26A detects the maximum value MAX and the maximum value MIN of the coefficient data in the block, obtains a dynamic range DR, which is a difference between them, and adapts the coefficient The data DCa to DCp are quantized.

The dynamic range DR and the minimum value MIN output from the ADRC encoder 26A are written to the memory 27A. memory
The maximum values of DR and MIN for one frame stored in 27A are supplied to a maximum value detection circuit 28A. As in the above-described embodiment, the bit number determination circuit 29A is determined based on the detected maximum value.
The bit numbers n1 and n2 are determined, and the bit processing circuit 30A
Changes the number of bits. For the framing circuit 32, the dynamic range DR from the bit processing circuit 30A
And the minimum value MIN, and the code signal DT passed through the delay circuit 31A.
And bit number identification codes DRn and MINn are supplied,
Transmission data is obtained at the output terminal 33 of the framing circuit 32.

AC component coefficient data AC1 from the reblocking circuit 25P
5 is supplied to the ADRC encoder 26P. The ADRC encoder 26P determines the number n0 of bits to be allocated for quantization by the bit number determination circuit 34P from the detected dynamic range DR, and does not transmit the maximum value MIN as 0. A for coefficient data AC1 to AC14 of other AC components
The same applies to the DRC encoder. With this encoding, the amount of transmission data relating to AC component coefficients and data can be compressed. Therefore, the additional code is bit number data indicating the bit number n0 of quantization. The AC component coefficient data AC1 to AC15 are
Normally, since the data is quantized to 7 bits or less, the bit number data is a 3-bit code that can identify 1 to 7 bits.

If the bit number data, which is the additional code, is not compressed, one block of data is constituted by the 3-bit bit number data and the code signal of each block, as shown in FIG. Since there are 15 AC component coefficient data, the bit number data per block is (3 × 15 = 45 bits), and the load of the additional code is still heavy.

Therefore, in another embodiment, a memory 27P, a maximum value detection circuit 28P, a bit number determination circuit 29P, and a bit processing circuit 30P are provided to compress the bit number data. Memory 27
The maximum value of the bit number data for one frame stored in P is detected by the maximum value detection circuit 28P, and the bit number n3 according to the maximum value is determined by the bit number determination circuit 29P. In the bit processing circuit 30P, the bit number data is
Is changed to Since the number of bits n3 can be 1 bit, 2 bits or 3 bits, the identification code Bn for identifying this is 2 bits.

As an example, when the coefficient data AC15 is quantized with the maximum distortion 8, the maximum value of the coefficient data AC15 in one frame period is
If it is 30.72, the maximum value of the bit number data is also 1 bit. Therefore, the length of the bit number data is 3 bits to 1
And the identification code Bn for each frame is 1
Bit. Therefore, in this case, the transmission data shown in FIG. 5 is obtained.

As described above, in the other embodiments, the additional codes DR and MIN can be compressed for the DC component coefficient data, and the additional code (bit number data) can be compressed for the AC component coefficient data. It can be performed.

As in the embodiment, the compression processing of the additional code may be performed for each area obtained by dividing the screen of one frame into several parts. Also. Orthogonal transform codes other than cosine transform may be used. Further, block coding other than ADRC may be used.

〔The invention's effect〕

According to the present invention, redundant portions of additional codes generated in block coding can be reduced, and the amount of transmission data can be reduced as a whole. Further, the present invention has an advantage that the image quality of the restored image is not deteriorated because the redundant portion of the additional code is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a schematic diagram showing an example of transmission data of this embodiment, FIG. 3 is a block diagram of another embodiment of the present invention, FIG. FIGS. 5 and 5 are schematic diagrams used to explain another embodiment, and FIGS. 6 and 7 are schematic diagrams used to explain a conventional high-efficiency encoding apparatus. Description of main symbols in the drawings 2: block circuit, 3: maximum value, minimum value detection circuit, 7: quantization circuit, 9: maximum value detection circuit, 10: bit number determination circuit, 11: bit processing circuit.

Claims (2)

(57) [Claims] 1. A block coding circuit that blocks input digital image data, a block coding circuit that codes pixel data in the block according to a dynamic range of each block, and a block coding circuit that is used in the block coding circuit. A detection circuit for detecting the maximum value of the additional code for each block over a predetermined number of blocks, and determining the number of bits to be allocated to the additional code for the period of the predetermined number of blocks based on an output of the detection circuit. And a change circuit for changing the number of bits of the additional code based on the output of the decision circuit. The output of the block encoding circuit, the additional code from the change circuit, and the number of bits from the decision circuit. A high-efficiency encoding device that transmits an identification code. 2. The method according to claim 1, wherein the input digital image data is divided into blocks; a block encoding step of encoding pixel data in the block in accordance with a dynamic range of each block; and a block encoding step. Detecting the maximum value of the additional code for each of the blocks over a predetermined number of the blocks; and determining the number of bits to be allocated to the additional code for the period of the predetermined number of blocks based on the detection result. Changing the number of bits of the additional code based on the determined number of bits, the output generated by the block encoding step, the changed number of bits corresponding to the changed additional code, and the determined number of bits. High efficiency coding method for transmitting a bit number identification code to be transmitted.