JP2793402B2 - Image coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image encoding apparatus suitable for compression encoding of still images and moving images, such as a videophone, an image transmission device, or an electronic still camera.

[0002]

2. Description of the Related Art In recent years, with the spread of videophones, electronic still cameras, and the like, digital processing of images, particularly, high-efficiency coding techniques for compressing image data have been remarkably advanced. FIG. 7 is a block diagram showing an electronic still camera that encodes and records image information.

The CCD 1 receives light from an object, photoelectrically converts the light, and supplies the photoelectric conversion circuit 2 with the light. The signal from the CCD 1 is converted into, for example, a luminance signal and a color difference signal by the imaging circuit 2 and the signal processing circuit 3. The video signal from the signal processing circuit 3 is applied to a frame memory 4 for recording, and then read out sequentially and applied to a compression encoding circuit 5. Compression encoding circuit 5
Compresses the read data by encoding, transmits the data through, for example, a telephone line 7, and records the data on a recording medium such as a memory card 6.

[0004] By the way, when an image is compression-encoded, the code amount generally tends to increase for a fine picture and to decrease for a smooth image. For this reason, the amount of transmission code changes for each image, and there is a disadvantage that the capacity of the recording medium for recording the image may be insufficient.

In view of this, there is a type in which a buffer memory is provided in the output unit so that the amount of code for each image is constant regardless of the picture. FIG. 8 is a block diagram showing such a conventional image encoding device.

The image data read from the frame memory 4 is supplied to a quantization circuit 11 for quantization. The quantized image data is differentially encoded in the DPCM circuit 12, and further, for example, Huffman encoded in the variable length encoding circuit 13. With Huffman coding, the bit rate is further reduced. The output of the variable length coding circuit 13 is
Output via. The output of the buffer memory 14 is also provided to the quantization circuit 11. The quantization circuit 11 is a buffer memory 14
The quantization is controlled depending on the usage state of, and the quantization characteristic is changed so that the average value of the output rate becomes constant.

FIG. 9 is a block diagram showing another conventional example.

The image data read from the frame memory 4 is applied to a DCT (discrete cosine transform) circuit 15 for DCT processing. The DCT coefficient from the DCT circuit 15 is
To quantize. Further, the quantized output is subjected to, for example, Huffman coding in the variable length coding circuit 17. The Huffman code from the variable length coding circuit 17 is output via the buffer memory 18. Depending on the use state of this buffer memory 18,
The quantization circuit 16 changes the quantization characteristic and controls the output rate to be constant.

However, in these methods, since the encoding characteristics are sequentially changed according to the use state of the buffer memory, it is not possible to make an optimal adjustment over the entire screen. For example, when image data of a fine pattern is input in the upper half of the screen and fine in the lower half, unnecessary bits are assigned to encoding of the image data of the upper half of the screen, and the lower half of the image data of the image data is input. Sufficient bits cannot be allocated for encoding, and image quality deteriorates.

In some cases, the encoding is repeated a plurality of times until a desired data amount is obtained. In such a conventional image encoding apparatus, when the output data amount is larger than the target value, the quantization value is changed and the encoding is performed again to reduce the data amount. Conversely, when the output data amount is smaller than the target value, the quantization value is changed and the encoding is performed again to increase the data amount. By repeating this encoding, the output data amount finally converges to the target value.

However, this method has a disadvantage that the time required for the encoding process is enormous.

[0012]

As described above, in the conventional image coding apparatus described above, the output rate is kept constant by sequentially changing the coding characteristics in accordance with the amount of output buffer used, and the entire picture is displayed. There is a problem that the optimum encoding cannot be performed over the entire system, and the image quality deteriorates. In addition, when a method of repeating coding to keep the output rate constant is employed, there is a problem that high-speed processing cannot be performed.

The present invention provides an image coding apparatus which enables high-speed processing and enables optimum coding over the entire screen by previously obtaining code amounts corresponding to a plurality of coding characteristics. The purpose is to do.

[0014]

An image encoding apparatus according to the present invention orthogonally transforms block data obtained by dividing a digital image signal into a plurality of pixels to obtain transform coefficients, and quantizes the transform coefficients. An image coding apparatus for performing variable-length coding by using a quantization circuit that receives the transform coefficient and quantizes the transform coefficient with a predetermined quantization characteristic and outputs the quantized circuit; And image dividing means for obtaining a transform coefficient for the quantization circuit and estimating the total code amount from the code amount of the variable-length encoded output when estimating the code amount, and determining the estimated code amount and the target code amount. A quantization characteristic changing unit that changes the quantization characteristic to perform a predetermined number of encodings, and estimates a total code amount from a code amount of an encoded output obtained by the predetermined number of encodings when estimating the code amount. Together, is characterized in that it has and a quantization characteristic determining means for determining an optimum quantization characteristic and a code amount to be estimated code amount and the target.

[0015]

In the present invention, the encoding means performs encoding with predetermined encoding characteristics prior to the original encoding. In this case, only a part of the image signal of the image is encoded by the image dividing means, and the time required for the encoding is short. The encoding characteristic changing means changes the encoding characteristic of the encoding means. Thus, the code amount of the coded output at the time of a plurality of coding characteristics can be obtained in a relatively short time. The coding characteristic determining means obtains a coding characteristic for obtaining a target total code amount from coded outputs in a plurality of times of coding. The encoding means encodes the image signals of all the images with the encoding characteristics.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of an image encoding device according to the present invention.

The luminance signal and the color difference signal are stored in a frame memory 21.
To enter. The writing and reading of the frame memory 21 are controlled by the address control circuit 22, and the input signal is framed and supplied to the block dividing circuit 23. FIG. 2 is an explanatory diagram for explaining image data from the block dividing circuit 23. The block division circuit 23 divides the input signal into a total of 64 pixels of 8 horizontal pixels and 8 vertical pixels as shown in FIG.
The data is divided into pixels and supplied to the DCT circuit 24. The address control circuit 22 controls the address of the frame memory 21 so that predetermined block data in the screen is output from the block dividing circuit 23. Thus, for example, every other block data in the horizontal direction is divided into block division circuits only from odd block lines in blocks in each row of the screen (hereinafter, referred to as block lines).
It is also possible to output sequentially from 23. The DCT circuit 24 performs a DCT process on the input image data to convert it into frequency components, and outputs 64 DCT coefficients for each block.

FIG. 3 is an explanatory diagram for explaining the DCT coefficient from the DCT circuit 24.

As shown in FIG. 3, the DCT coefficients are arranged in order from the low-frequency component in the horizontal and vertical directions to the high-frequency component. As shown by the numbers in FIG. 3, the DCT circuit 24 scans the DCT coefficients in a zigzag manner from the low-frequency component to the high-frequency component in the horizontal and vertical directions, and outputs the DCT coefficients in this order. Note that the number 0 part in FIG. 3 indicates a DC term, and the value is an average value of all pixels. The other part is the AC term.

The DC term from the DCT circuit 24 is applied to a quantization circuit 25
To the quantization circuit 26. Quantization circuit 2
Numerals 5 and 26 quantize a DC term or an AC term, respectively, and output a quantized output to a DPCM circuit 28 or a zigzag scan circuit 29, respectively. DPCM circuit
28 calculates the difference of the DC term between the input adjacent blocks and supplies it to the encoding circuit 30. The encoding circuit 30 uses the Huffman table 32 to Huffman-encode the difference value from the DPCM circuit 28 and outputs the result to the multiplexing circuit 34. On the other hand, the zigzag scan circuit 29 reads the AC terms from the quantization circuit 26 in a zigzag scan order and supplies the read AC terms to the encoding circuit 31. The encoding circuit 31 creates a combination of the number of consecutive zeros of the quantized output (0 run) and the number of bits of the DCT coefficient immediately after the combination, and uses the Huffman table 33 to generate a Huffman table for this combination. The data is encoded and output to the multiplexing circuit 34. The multiplexing circuit 34 is configured to time-division multiplex the Huffman-encoded DC term and AC term and output them.

Table 1 below shows examples of Huffman codes. For example, when “1” is input after two consecutive “0” as the quantized output, as shown in Table 1, the encoding circuits 30 and 31 output a Huffman code of “11011”. ing.

[0022]

[Table 1] As described above, the code length of one block and the code length of one screen change by Huffman coding. On the other hand, the code length also changes due to quantization. The quantization circuit 26 performs quantization based on the quantization value from the multiplier 27. For example, when the quantization value is increased, the probability that 0 appears as a quantization output increases, and the code length (total number of bits) ) Becomes shorter. In a general image, when the quantization value is increased, the code length (the number of bits) is rapidly reduced. The multiplier 27 converts the basic quantization value stored in the basic quantization table
By multiplying the quantization table scale factor α from the calculation circuit 37, the quantization value given to the quantization circuit 26 is changed.

However, the total number of bits when the quantization value is changed differs for each image, and the total number of bits is not determined until after the coding is completed. Therefore, in the present embodiment, prior to encoding, the quantization table scale factor α is appropriately changed and encoding is performed on predetermined block data to obtain an optimal quantization value.

That is, the α calculating circuit 37 sets the scale factor α as 1, 0.5, 0.25,
A value such as 0.1 is output. The output of the multiplexing circuit 34 is also supplied to a code amount calculation circuit 36. The code amount calculation circuit 36 obtains the code amount of the encoded output to obtain an α calculation circuit 37.
Output to The α calculation circuit 37 calculates an optimum scale factor αT from the obtained code amount. That is, the .alpha. Calculation circuit 37 determines the optimum scale factor .alpha.T from the two upper and lower total bits near the total bit number NT of the target encoded output in the input code amount data. For example, if the code amounts when the scale factors are α3 and α4 are N3 and N4, respectively, and N4>NT> N3, the α calculation circuit 37 performs the operation shown in the following equation (1).
An optimum scale factor αT for obtaining a target total number of bits is obtained.

[0025] Next, the operation of the embodiment configured as described above will be described with reference to FIG.
This will be described with reference to FIG. FIG. 4 is an explanatory diagram for explaining block data to be encoded at the time of estimating the code amount for obtaining the optimum scale factor αT, and FIG. 5 is an explanatory diagram showing the quantization values.

The luminance signal and the color difference signal are stored in the frame memory 21.
And memorize it. The image data read from the frame memory 21 is divided into blocks by a block dividing circuit 23 and supplied to a DCT circuit 24. Here, the address control circuit 22 controls reading of the frame memory 21, and first,
As shown by the hatched portion in FIG. 4, only every other block data of the odd-numbered block line is sequentially applied to the DCT circuit 24.

The DCT circuit 24 performs DCT processing on block data in units of 8 × 8 pixels, and quantizes DCT coefficients into quantization circuits 25 and 26.
Give to. The quantization circuit 25 quantizes the DC term of the DCT coefficient and outputs it to the DPCM circuit 28. The DPCM circuit obtains a difference between a DC term of the quantized output and an adjacent block and outputs a difference value to the encoding circuit 30. The encoding circuit 30 uses the Huffman table 32 to Huffman-encode the difference value from the DPCM circuit 28 and outputs the result to the multiplexing circuit 34.

On the other hand, the quantization circuit 26 performs quantization on the AC term of the DCT coefficient based on the scale factor α. For example, the α calculating circuit 37 first sets the scale factor α to 1
Is output. In this case, the basic quantization value of the basic quantization table 35 is directly supplied from the multiplier 27 to the quantization circuit 26. The output of the quantization circuit 26 is given to the encoding circuit 31,
The encoding circuit 31 performs Huffman encoding on a set of 0 run and the number of bits of the quantized coefficient for the AC term of the quantized output. The multiplexing circuit 34 multiplexes the coded outputs from the coding circuits 30 and 31 and supplies the multiplexed output to the code amount calculation circuit 36.

The code amount calculation circuit 36 accumulates the code amount of each block, obtains the code amount at the time of completion of the encoding of a quarter block of the entire screen, and quadruples the scale factor α =
In the case of 1, the total code amount N1 of the entire screen is calculated. As a result, the total code amount can be obtained in about one-fourth of the time required to read all block data. In a natural image, the correlation between pixels is high, and the error is small even when the code amount is estimated using a partial image as in the present embodiment. According to the results of investigation on many images, the code amount obtained when all blocks are coded and the code amount obtained by quadrupling the code amount obtained when １ ／ of the entire block is coded are as follows. Although it varies slightly depending on the sampling position, it falls within an error within a few percent. Now, it is assumed that the code amount N1 thus obtained is smaller than the target code amount NT. Then, the α calculation circuit 37 next sets 0.1 as the scale factor α.

The address control circuit 22 controls the frame memory 21 to read out data of a quarter of all blocks again. In this case, data of the same block as the previous time may be read, or block data different from the previous time may be read. The DCT circuit 24 performs a DCT process on the read block data, and supplies the block data to the quantization circuits 25 and 26. The multiplier 27 obtains a quantization value by multiplying the basic quantization value of the basic quantization table 35 by a scale factor α = 0.1 and supplies the quantization value to the quantization circuit 26. The quantization circuit 26 quantizes the AC term based on the quantization value from the multiplier 27 and outputs the result. The coding circuit 31 performs Huffman coding on the quantized output of the AC term and outputs the result to a multiplexing circuit 34.
The output of 31 is multiplexed and output to the code amount calculation circuit 36.

As in the previous case, the code amount calculation circuit 36 accumulates the code amount of each block, and quadruples the code amount to estimate the code amount of all blocks. Now, it is assumed that the code amount N2 thus obtained is larger than the target code amount NT. Then, α
Next, the calculation circuit 37 outputs 0.5 as the scale factor α. Similarly, the DCT circuit 24 outputs 1 /
The DCT process is performed on the block No. 4 and the quantization circuit 26 performs quantization based on the quantization value from the multiplier 27. Thus, the code amount calculation circuit 36 obtains the code amount when the scale factor α = 0.5.

Assuming that the code amount N3 in this case is smaller than the target code amount NT, the α calculating circuit 37 then outputs 0.25 as the scale factor α. Multiplier 27
Multiplies the basic quantized value by a scale factor α = 0.25 and supplies the result to the quantizing circuit 26. Quantization and encoding are performed for a quarter of the block as in the previous case,
Estimate the code amount. Assuming that the code amount N4 in this case is larger than the target code amount NT and that N4>NT> N3, the α calculating circuit 37 performs the operation of the above equation (1) to determine the optimum scale factor αT. calculate. In this case, the optimum scale factor αT can be calculated in the same time as when all the blocks are coded once.

Next, encoding is performed using the optimum scale factor αT. The address control circuit 22 is a frame memory 21
And sequentially supplies data of all blocks to the block dividing circuit 23. The DCT circuit 24 subjects the block data from the block dividing circuit 23 to DCT processing and performs quantization processing.
Give 25, 26. The quantization circuit 25 quantizes the DC term,
The PCM circuit 28 obtains a difference value between adjacent blocks, and the coding circuit 30 performs Huffman coding on the difference value and performs a multiplexing circuit 34.
Output to

On the other hand, the multiplier 27 has an optimum scale factor α
By multiplying T by the basic quantization value, for example, a quantization value shown in FIG. 5 is created. Each quantization value in FIG. 5 corresponds to each frequency component of the quantization output shown in FIG. This quantization value is given to the quantization circuit 26. The quantization circuit 26
For example, the quantization is performed by dividing the DCT coefficient by the quantization value, and the quantization output is output to the encoding circuit 31 via the zigzag scan circuit 29. The encoding circuit 31 performs Huffman encoding on a set of 0 run and the number of bits of the quantization coefficient.
The multiplexing circuit 34 multiplexes and outputs the Huffman codes from the encoding circuits 30 and 31.

As described above, in this embodiment, when estimating the code amount, encoding is performed a plurality of times by changing the scale factor α for each ブ ロ ッ ク block data of the entire screen, and the code of the encoded output is obtained. Since the total code amount is estimated by quadrupling the amount, the time required for calculating the optimal scale factor αT can be reduced. Encoding is performed using the optimal scale factor αT, and optimal encoding can be performed over the entire screen.

In this embodiment, 1/4 of the whole
Although the total code amount is estimated by reading the block data of, arbitrary block data such as 又 は or ８ of the whole may be read. Also, for example, at the first code amount estimation, 1/8 of the entire block may be read, and at the second code amount estimation, 1/4 of the entire block may be read to perform the code amount estimation. That is, at first, a large sampling error is allowed by coarse sampling, and sampling is performed gradually and finely, thereby enabling quick and accurate code amount estimation. In addition, the sampling positions may be regularly determined as shown in FIG. 4, may be shifted while being shifted, or may be randomly determined. Further, in the present embodiment, encoding is performed four times in order to estimate the code amount. However, the number of times of encoding can be set arbitrarily. Until the allowable error | NT−Nn | with the code amount Nn at the time of encoding becomes smaller than the predetermined value nb, the encoding may be repeated while changing the scale factor α to calculate the optimal scale factor αT.

The above equation (1) is based on the assumption that the relationship between the code amount and the scale factor α is linear. However, in practice, the relationship between them is not linear. FIG. 6 is a graph showing the relationship between the code amount and the scale factor α by taking the logarithm of the scale factor α on the horizontal axis and the logarithm of the total code amount N on the vertical axis.

For example, when the relationship between the logarithm of the scale factor α and the logarithm of the total code amount N is determined for predetermined images A and B, both become linear as shown in FIG. According to the evaluation results of many images, the logarithm of the scale factor α and the total code amount N has the relationship shown in FIG. That is, the following equation (2) holds.

Log N = K 1 log α + K 2 (2) where K 1 and K 2 are constants.

The α-calculating circuit 37 may calculate the optimum scale factor αT from the calculation of the above equation (2).
That is, the α calculating circuit 37 calculates the above N3, N4, α3
, Α4, and K1 and K2 are determined, and the optimum scale factor αT is determined from the target code amount NT. When equation (2) is adopted, the calculation becomes complicated, but a more accurate scale factor αT can be obtained.

In this case, it is assumed that the scale factor α at the time of estimating the code amount corresponds to a logarithmic value. That is, in the embodiment, the scale factor α
Was changed to 1,0.1,0.5,0.25, but log
Since N and log α are proportional, the scale factor α is set to 1, 0.126, 0.31 so that the logarithmic value becomes 1/2.
It is better to change to 6,0.178.

[0042]

As described above, according to the present invention, since the encoding is performed by obtaining the optimum encoding characteristics for the entire screen, high-speed processing can be performed and the image quality can be improved. It has the effect of.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image encoding device according to the present invention.

FIG. 2 is an explanatory diagram illustrating an embodiment.

FIG. 3 is an explanatory diagram for explaining the embodiment.

FIG. 4 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 5 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 6 is a graph for explaining a modification of the embodiment.

FIG. 7 is a block diagram showing an electronic still camera.

FIG. 8 is a block diagram showing a conventional image encoding device.

FIG. 9 is a block diagram showing a conventional image encoding device.

[Explanation of symbols]

21: frame memory, 22: address control circuit, 23: block division circuit, 24: DCT circuit, 25, 26: quantization circuit,
27: Multiplier, 30, 31: Encoding circuit, 36: Code amount calculation circuit, 37: α calculation circuit

Claims (3)

(57) [Claims] 1. An image coding apparatus for orthogonally transforming block data obtained by blocking a digital image signal for each of a plurality of pixels to obtain a transform coefficient, quantizing the transform coefficient, and performing variable length coding, the image coding apparatus comprising: A quantization circuit that receives a coefficient and quantizes the data with a predetermined quantization characteristic and outputs the result; and an image division unit that obtains a transform coefficient for some block data of the block data when estimating a code amount and provides the transform coefficient to the quantization circuit. Means for estimating the total code amount from the code amount of the variable-length encoded output at the time of estimating the code amount, and changing the quantization characteristic from the estimated code amount and the target code amount to perform encoding a predetermined number of times. Means for changing the quantization characteristic to be performed, and estimating the total code amount from the code amount of the coded output obtained by performing the predetermined number of times of encoding when estimating the code amount, and also estimates the estimated code amount and the target code amount. Image encoding apparatus characterized by comprising a quantization characteristic determining means for determining an optimum quantization characteristic from. 2. An image coding apparatus for orthogonally transforming block data obtained by blocking a digital image signal for each of a plurality of pixels to obtain a transform coefficient, quantizing the transform coefficient, and performing variable length coding, the image coding apparatus comprising: A quantization circuit that receives a coefficient and quantizes the data with a predetermined quantization characteristic and outputs the result; and an image division unit that obtains a transform coefficient for some block data of the block data when estimating a code amount and provides the transform coefficient to the quantization circuit. Means for estimating the total code amount from the code amount of the variable-length encoded output at the time of estimating the code amount, and changing the quantization characteristic until the difference between the estimated code amount and the target code amount is within an allowable value. Quantization characteristic changing means for performing coding multiple times, and estimating the total code amount from the code amount of the coded output obtained by performing the coding multiple times when estimating the code amount. Image encoding apparatus characterized by comprising a quantization characteristic determining means for determining an optimum quantization characteristic and a code amount that the amount and the target. Wherein said image splitting means image coding according to any one of claims 1 or 2, characterized in that to increase the portion to be used for estimating the code amount for each coding when the estimated amount of codes apparatus.