JPH0487460A - Picture processor - Google Patents

Abstract

PURPOSE:To improve the reproducibility of a character and an intermediate tone picture respectively by selecting a quantization table in response to a picture data and coding a block-processed picture data subjected to a block processing based on a selected quantization table. CONSTITUTION:An inputted PDL picture element data is converted into a raster image data by an interpreter 2 and whether the picture data is a line picture such as a character or graphics or an intermediate picture such as a photograph is identified. A signal changeover switch 7 is thrown to connect a terminal (a) (or b) of a relevant Q table 6 to a common terminal (c) according to an identification signal from the interpreter 2. Through the connection, the data is subjected to linear quantization with a conversion coefficient according to quantization step information fed from either a character table 6a or a picture table 6b of the table 6 by a quantizer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and more particularly to an image processing device that stores halftone image information such as a photograph having gradations (colors).

[Prior Art] When storing halftone images such as photographs (hereinafter referred to as "images") in memory, the required memory capacity is (number of pixels) x (number of gradation bits), and high-quality color Storing images required a huge amount of memory capacity. For this reason, various compression methods have been proposed to compress the amount of information.
Memory capacity is reduced by storing compressed information in memory.

Figure 4 shows JPEG (Joint Photographic
Ba proposed by Experts Group)
Coding method of 5eline System (basic method) (Yasuda: [International standardization of color still image coding] 1 Journal of the Institute of Image Electronics Engineers, Vol. 18.

No. 6, pp, 398-409.1989> is a block configuration diagram.

The image pixel data input from the input terminal 1 is cut out into blocks of 8x8 pixels by the blocking circuit 3, cosine transformed by the H-loss cosine transform (DCT) circuit 17, and the transform coefficients are sent to the quantizer (Q). ) 40. This quantizer 40 performs linear quantization of the transform coefficients according to quantization step information applied by a quantization table 41. Among the quantized transform coefficients, the DC coefficients are converted into DC coefficients of the previous block by a predictive coding circuit (DPCM) 42.
A difference (prediction error) with the component is taken and supplied to the Huffman encoding circuit 43.

FIG. 5 is a detailed block diagram of the predictive encoding circuit 42 shown in FIG. 4.

The DC coefficients quantized by the quantizer 40 are sent to the delay circuit 53.
and is applied to the subtractor 54. This delay circuit 53 is a circuit in which the discrete cosine transform circuit is delayed by the time required to calculate one block, that is, 8x8 pixels. Therefore, the DC coefficient of the previous block is sent from the delay circuit 53 to the subtracter 54. Supplied. Therefore, the subtracter 54 outputs the difference (prediction error) in the DC coefficient from the previous block. The circuit 42 is composed of the delay circuit 53 as described above).

Next, the one-dimensional Huffman encoding circuit 43 shown in FIG.
The prediction error signal supplied from the prediction encoding circuit 42 is
The data is variable-length encoded according to the Huffman code table 44, and is supplied as a DC Huffman code to a multiplexing circuit 51, which will be described later.

On the other hand, the AC coefficients (coefficients other than the DC coefficients) quantized by the quantizer 40 are zigzag-scanned by the scan conversion circuit 45 in order from the low-order coefficients as shown in FIG. 6 to detect significant coefficients. The signal is supplied to circuit 46. This significant coefficient detection circuit 46 determines whether the quantized AC coefficient is "0" or not. If it is "0", it supplies a count up signal to the run length counter 47 and increases the counter value by "+1". increase. However, in the case of a coefficient other than "0", a reset signal is supplied to the run length counter 475, the counter value is reset, and the coefficients are sent to the grouping circuit 48 as shown in FIG. and additional bits, and supply the group number 5SSS to the Huffman encoding circuit 49 and the additional bits to the multiplexing circuit 51, respectively.

The run length counter 47 described above is a circuit that counts the run length of "0", and the number N of "OH" between significant coefficients other than "0".
NNN is supplied to a two-dimensional Huffman encoding circuit 49. This Huffman encoding circuit 49 performs variable length encoding on the supplied MO'' run length NNNN and significant coefficient group number 5sss according to the AC Huffman code table 50.
A multiplexing circuit 51 is provided with an AC Huffman code.

In the multiplexing circuit 51, one block (8x8 input pixels)
The DCC eight-man code, AC Huffman code, and additional bits are multiplexed, and compressed image data is output from the output terminal 52.

Therefore, the memory capacity can be reduced by storing the compressed image data outputted from the output terminal 52 in a memory and decompressing it by a reverse operation when reading.

[Problems to be Solved by the Invention] However, in the conventional example described above, the quantization unit 40 has only one quantization table 41, so that line drawings such as character graphics and halftone images such as photographs are In both cases, it was difficult to improve reproducibility. In other words, it was necessary to increase the resolution for characters (line drawings) and the gradation for halftone images.

The present invention was made to solve the above problems, and
It is an object of the present invention to provide an image processing device capable of improving the reproducibility of each of characters and halftone images, and achieving high image quality.

[Means for Solving the Problems] In order to achieve the above object, an image processing apparatus of the present invention has the following configuration. That is, the image processing apparatus has different quantization tables and compresses and stores block image data, and includes a selection means for selecting a quantization table according to the image data, and a quantization table selected by the selection means. The selection means includes an encoding means for encoding image data divided into blocks based on a quantization table, and a storage means for storing the image data encoded by the encoding means, and the selection means includes a page description. A language interpreter identifies the image data and selects a quantization table depending on the result.

Preferably, one aspect of the selection means is to select a quantization table based on a difference between a maximum value and a minimum value of image data in the block.

Preferably, one aspect of the selection means is to select the quantization table based on the maximum value of the difference between adjacent pixels of the image data in the block.

[For use] In the above configuration, by selecting a quantization table according to the image data and encoding the block image data based on the selected quantization table, characters and halftone images can be created. In addition to improving the reproducibility of each, it is possible to achieve high image quality.

[Embodiment] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram showing the configuration of an image processing apparatus in this embodiment. In the figure, a page description language (PDL), such as Adobe's Bost Script (PS), is input from an input terminal l.

Image data expressed in Canon's CaPSL or the like is input. The PDL pixel data input here is converted into rask image data by the next interpreter 2, and at the same time, it is determined whether the image data is a line drawing such as text or graphics, or a halftone image such as a photograph. Then, an identification signal that is the identification result is output to a signal changeover switch 7 and an index memory 10, which will be described later.

The rask image data converted by the interpreter 2 is processed in the blocking circuit 3, for example, 8x8
It is cut out into blocks of pixels and subjected to discrete cosine transformation (DC
T) A cosine transform is performed in the circuit 4, and the transform coefficients are sent to the quantizer (Q) 5.

Next, the signal changeover switch 7 selects terminal a (or b) of the corresponding Q table 6 according to the identification signal from the interpreter 2.
) to common terminal C. With this connection, the quantizer 5 linearly quantizes the transform coefficients according to the quantization step information applied from either the character table 6a or the image table 6b.

The linearly quantized transform coefficients are processed by the following variable length coding circuit (
VLC) 8 is used to perform variable length encoding, and one block of data is stored in a frame memory 9. At this time, the above-mentioned identification signal (index) is stored in the index memory IO.

In this embodiment, since there are two types of Q tables 6a and 6b, the index is 1 bit for each block.

By repeating the above operations, data for one frame is accumulated in the frame memory 9.

The configuration of the variable length coding circuit (VLC) 8 is similar to that shown in FIGS. 42 to 52, but other variable length coding methods (eg, arithmetic coding) may be used.

FIGS. 2(a) and 2(b) are diagrams showing the details of the character table 6a and the image table 6b, respectively.As is clear from the figures, the character table (a) improves resolution, and the image table (b) ) stores step information for increasing gradation.

[Other Embodiments] Next, other embodiments according to the present invention will be described below with reference to the related drawings.

FIG. 3 is a schematic block diagram showing the configuration of the image processing apparatus in this embodiment.

It should be noted that blocks having the same functions as the blocks shown in FIG. 1 are given the same numbers and will not be described here.

As shown in FIG. 3, in this embodiment, a normal image area M (edge detection circuit 33) is used as means for identifying character data or image data.

In the figure, when bitmap image data is input from the input terminal 31, the next blocking circuit
For example, it is cut out into blocks of 8x8 pixels and sent to the edge detection circuit 34. In this edge detection circuit 34, when the difference between the maximum value and the minimum value for each block or the maximum value of the difference between adjacent pixels exceeds a certain value, the common terminal C of the signal changeover switch 7 is connected to the Q table 6. character table 6a
Connect to terminal a on the side. Furthermore, if the maximum value of the difference between the maximum value and the minimum value or the maximum value of the difference between adjacent pixels is less than a certain value, the common terminal C of the signal changeover switch 7 is connected to the terminal of the Q table 6 on the image table 6b side. Connect to.

On the other hand, the image data that has passed through the edge detection circuit 34 is subjected to cosine transformation in the discrete cosine transform (DCT) circuit 4, and the transformation coefficients are applied by the quantization table 6 of either the character table 6a or the image table 6b. Linear quantization is performed according to the quantization step information.

Note that, similarly to the embodiments described above, the linearly quantized transform coefficients are variable-length coded by a variable-length coding circuit (VLC) 8, and one block of data is stored in a frame memory 9. At this time, similarly, index memory 1
The index is stored in 0. In this embodiment as well, there are two types of Q-tables, so the index is one bit for each block.

By repeating the above operations, data for one frame is accumulated in the frame memory 9. Then, the character table 6a and the image table 6b are used as the second table as in the previous embodiment.
Figures (a) and (b) are used, with the character table (a) providing step information for increasing the resolution, and the image table (b) for increasing the gradation.

In the above two embodiments, the configurations shown in FIGS. 2(a) and 2(b) are used as the coefficients of the character table and image table, but the present invention is not limited to this. It is also possible to subdivide or use coefficients more optimized for the characteristics of the output device.

Furthermore, it is also possible to use not only one character table and one image table each (or a plurality of each depending on the ratio of character data/image data, the size of edges, etc.). A similar effect can also be obtained with a configuration in which an edge detection circuit is placed after the DCT circuit 4 and edge detection is performed in frequency space.

According to the embodiment described above, it is possible to improve the reproducibility and achieve high image quality for both text and halftone images such as photographs. It has become possible to improve gradation in the image area.

[Effects of the Invention] As described above, according to the present invention, it is possible to improve the reproducibility of each of characters and halftone images, and to achieve high image quality.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing the configuration of the image processing device in this embodiment. FIGS. 2(a) and (b) are diagrams showing the contents of an image table and a character table, respectively. FIG. 3 is another embodiment. 4 is a block diagram illustrating the configuration of a conventional encoding system; FIG. 5 is a detailed block diagram illustrating the configuration of the predictive encoding circuit shown in FIG. 4; FIG. 6 is a diagram showing the scan order of DCT coefficients, and FIG. 7 is a diagram showing group numbers and additional bits of AC coefficients. In the figure, 2... Interpreter, 3... Blocking circuit, 4... DCT circuit, 5... Quantizer, 6... Quantization table, 6a... Image table, 6b Character table , 7... signal changeover switch, 8... variable length encoding circuit, 9... frame memory, 10... index memory, 33... edge pressure detection circuit. (a) (b) 2nd figure AC i111 and [sss figure 7

Claims (3)

[Claims] (1) An image processing device that has different quantization tables and encodes and stores blocked image data, comprising a selection means for selecting a quantization table according to the image data; and a selection means for selecting a quantization table according to the image data. The selection means comprises: an encoding means for encoding the image data divided into blocks based on the quantization table, and a storage means for storing the image data encoded by the encoding means; An image processing device characterized in that a page description language interpreter identifies image data and selects a quantization table based on the result. (2) The image processing apparatus according to claim 1, wherein the selection means selects a quantization table based on a difference between a maximum value and a minimum value of image data in a block. (3) The image processing apparatus according to claim 1, wherein the selection means selects a quantization table based on a maximum value of a difference between adjacent pixels of image data in a block.