JP2668904B2 - High efficiency coding device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency coding apparatus applied to compress a transmission information amount when transmitting a digital image signal such as a digital video signal. SUMMARY OF THE INVENTION In the present invention, a digital image signal is divided into blocks, a maximum value and a minimum value of the block are detected, and a dynamic range which is a difference between the maximum value and the minimum value is detected, and the dynamic range is adapted. In a high-efficiency encoding device that quantizes each pixel data of a digital image signal with a smaller number of bits than the original number of quantization bits, the frequency in the level direction of the data quantized in block units is detected, According to the frequency information of the detection output, re-quantization is performed by assigning a smaller number of bits than the number of bits to the data of the higher frequency level, and the frequency information and the maximum value,
By transmitting at least two of the minimum value and the dynamic range, a high compression ratio of the amount of transmitted information can be realized. 2. Description of the Related Art There is known a high-efficiency coding apparatus that reduces the average number of bits per sample in order to compress the amount of transmitted information of a digital image signal such as a digital television signal. The applicant of the present application obtains a dynamic range, which is a difference between the maximum value and the minimum value of a plurality of strokes included in a two-dimensional block, as described in Japanese Patent Application No. 59-266407, and calculates the dynamic range. We have proposed a high-efficiency coder that performs adaptive coding. Also, Japanese Patent Application No. 60-23
As described in the specification of Japanese Patent No. 2789, there has been proposed a high-efficiency coding apparatus that performs coding suitable for a dynamic range with respect to a three-dimensional block formed from pixels in an area included in each of a plurality of frames. [Problems to be Solved by the Invention] In many actual image signals, the signal level rises from a minimum value to a maximum value or vice versa in one block. When coding (ADRC) adaptive to the dynamic range is performed on such a signal, the frequency distribution of the obtained code signal becomes non-uniform. That is, the number of pixels of the code signal corresponding to the maximum value or the minimum value is large, and the number of pixels of the code signal corresponding to the intermediate level is small. The present invention focuses on the fact that there are actually many non-uniform frequency distributions, and performs more efficient encoding. That is, an object of the present invention is to provide a high-efficiency coding apparatus that can improve the above-mentioned ADRC and further reduce the amount of transmission information. [Means for Solving the Problems] In the present invention, a digital image signal is divided into blocks, and a maximum value and a minimum value of the block are detected, and a dynamic range that is a difference between the maximum value and the minimum value is detected. In a high-efficiency encoding device adapted to quantize each pixel data of a digital image signal with a bit number smaller than the original quantization bit number in accordance with a dynamic range, a level direction of data quantized in block units is used. The frequency is detected, and according to the frequency information of the detection output, re-quantization is performed by allocating a smaller number of bits than the number of bits to the data of the higher frequency level, and the frequency information and the maximum value
At least two of the minimum value and the dynamic range are transmitted. [Operation] The digital image signal is quantized by ADRC encoding with a bit number smaller than the original bit number, for example, 8 bits, for example, 3 bits. 1 of the code signal obtained by this quantization
The frequency distribution in the block is detected. Frequency data is obtained according to the frequency distribution. Requantization is performed on the code signal having a high frequency. Since there is a code signal that does not occur in one block, requantization can be performed with a smaller number of bits than the number of bits allocated by ADRC. Although it is necessary to transmit frequency data, the number of bits per pixel can be reduced, so that the amount of information required to be transmitted per block can be reduced. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, a digital video signal having one sample of 8 bits is supplied to an input terminal indicated by 1.
This digital video signal is supplied to the blocking circuit 2. The blocking circuit 2 converts an input signal in the order of television scanning into the order of blocks. For example, as shown in FIG. 2, a screen of one frame is converted into a block structure of (4 lines × 4 pixels). The size of this block is an example, and may be converted into a three-dimensional block. An output signal of the blocking circuit 2 is supplied to a maximum value detection circuit 3, a minimum value detection circuit 4, and a delay circuit 5. Maximum value MA in the video signal of one block by the maximum value detection circuit 3
X is detected. The maximum value MAX is supplied to the subtraction circuit 6. The minimum value detection circuit 4 supplies the minimum value in one block.
MIN is detected. This minimum value MIN is supplied to the subtraction circuit 6. The dynamic range DR of the block represented by (MAX−MIN) is obtained by the subtraction circuit 6. The delay circuit 5 delays an input signal for a time necessary to detect the maximum value MAX and the minimum value MIN. An output signal of the delay circuit 5 is supplied to a subtraction circuit 7. The minimum value MIN is subtracted from the input signal by the subtraction circuit 7, and data PDI after the minimum value is removed is formed. The data PDI after the removal of the minimum value is supplied to the quantization circuit 8. The quantization circuit 8 is supplied with the dynamic range DR from the subtraction circuit 7 and is quantized in accordance with the dynamic range DR. As the quantization bit number, a bit number smaller than the original bit number (8 bits), for example, 3 bits is used. That is, as shown in FIG. 4, the maximum value MA
A level range in which the dynamic range DR between X and the minimum value MIN is equally divided into 8 is set, and a 3-bit code signal (000) to 3 bits depends on which level range the input data belongs to.
(111) is assigned. Specifically, the quantization circuit 8 is configured by a division circuit that divides the data PDI after the removal of the minimum value by the quantization width, or a ROM to which the dynamic range DR and the data PDI after the removal of the minimum value are supplied. The code signal DT obtained at the output of the quantization circuit 8 is supplied to the frequency detection circuit 9 and the delay circuit 10. Frequency detection circuit 9
Detects the presence / absence of each of the code signals DT in the block, and generates 8-bit frequency data DF according to the presence / absence. This frequency data DF is taken out to the output terminal 16.
The delay circuit 10 is provided in order to delay the code signal DT for the time when the frequency detection circuit 9 detects the frequency. The code signal DT passed through the delay circuit 10 is requantized by the requantization circuit 11.
Supplied to The frequency data DF from the frequency detection circuit 9 is supplied to the requantization circuit 11. The requantization circuit 11 is a circuit that further compresses the code signal DT using the frequency data DF. The 2-bit code signal DTR obtained from the requantization circuit 11 is taken out to the output terminal 17. An 8-bit dynamic range DR via a delay circuit 12 is extracted from an output terminal 14, and an 8-bit minimum value MIN via a delay circuit 13 is extracted from an output terminal 15. These delay circuits 12 and 13 are provided to delay the data for the time when the frequency data DF and the code signal DTR are obtained. The data obtained at the output terminals 14, 15, 16 and 17 are supplied to a framing circuit, not shown,
It is converted into transmission data of a frame structure. In this framing circuit, error correction coding processing is performed as necessary. Unlike this embodiment, dynamic range DR
And the maximum value MAX may be transmitted, or the maximum value MAX and the minimum value MIN may be transmitted. The above frequency detection and requantization will be further described.
As an example, consider the case where the signal in one block rises from the minimum value MIN to the maximum value MAX, as shown in FIG. For simplicity, FIG. 3 shows the case where the block is a one-dimensional block only in the time direction. Such non-uniform changes in signal level occur at the contours of the object and are quite common. In the example of FIG. 3, when 16 pixels are included in one block, the frequency distribution of the code signal DT from the quantization circuit 8 is the fourth.
It is shown in the figure. In the example shown in Fig. 4, (000)
(That is, MIN) is 12 pixels, (100) is 1 pixel, (111)
(That is, MAX) has a frequency of 3 pixels. The frequency detection circuit 9 generates frequency data DF represented by (10010001) by a bit that becomes “1” when there is a frequency and “0” when there is no frequency. From the frequency data DF, a code that actually has a frequency, that is, a used code can be expressed by 2 bits. The requantization circuit 11 allocates (000) to (00), (100) to (01), and (111) to (1) from the frequency data DF.
Perform requantization assigned to 0). In this way, in the quantization circuit 8, the code signal DTR compressed to 2 bits is formed in the requantization circuit 11 despite the allocation of 3 bits. In the block structure shown in FIG. 2, in the case of ADRC forming a 3-bit code signal, the data amount of one block is (8 + 8 + 3 × 16 = 64 bits). On the other hand, in this embodiment, (8 + 8 + 8 + 2 × 16 = 54 bits) is set, and the amount of transmission data can be further reduced. On the receiving side, contrary to the transmitting side described above, the code signal DT is obtained from the frequency data DF and the code signal DTR, and the ADRC code is decoded from the code signal DT, the dynamic range DR and the minimum value MIN, and the original level is obtained. Is restored. When the number of pixels in a block increases, a case where the code signal having a frequency of completely zero is less than half of the total number of levels is likely to occur, and the compression effect may be reduced. Therefore, the number of bits of the code signal DTR actually output may be determined as shown in the following table with respect to the bit allocation for quantization of ADRC. For example, in the case of 4-bit allocation, a code signal DTR of 3-bit code is generated. That is, the upper eight levels of the frequency are indicated by the bit pattern “1” of the frequency data DF. The lower 8 frequency levels are indicated by "0" in the bit pattern of the frequency data DF, and if the frequency is not 0,
Replace with the nearest top eight levels. In the block shown in FIG. 2, one row of frequency, frequency data DTR, and code signal DTR with fixed-length 3-bit allocation is shown below. In the example where bits are newly assigned in descending order of frequency as in the above-described example, the code signals DT ((001) and (1) whose bits are not newly allocated due to low frequency are assigned.
00)) is also assigned the nearest code signal DTR. In order to perform this processing, it is necessary to calculate the distance of the code and assign the code signal DTR of the shorter distance, and a microcomputer capable of high-speed processing is used. The above-described ADRC encoding circuit converts pixel data of a two-dimensional block into a fixed-length code signal. However, it may be converted to a three-dimensional block structure. Further, it may be possible to switch between performing only ADRC encoding or performing both ADRC encoding and requantization according to the result of frequency detection. In this case, it is necessary to transmit an additional bit for instructing one of the above two encodings. According to the present invention, a frequency distribution in a block of a code signal DT obtained by ADRC encoding is detected, and a code signal having a high frequency is requantized. Can be further reduced and the compression rate of the amount of transmitted information can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a schematic diagram of an example of a block, FIG. 3 is a schematic diagram of an example of a signal, and FIG. It is an approximate line figure used for description of quantization and frequency detection. Explanation of main symbols in the drawings 1: input terminal, 2: blocking circuit, 3: maximum value detection circuit, 4: minimum value detection circuit, 8: quantization circuit, 9: frequency detection circuit, 11: requantization circuit .

Claims (1)

(57) [Claims] The digital image signal is divided into blocks, the maximum value and the minimum value of the block are detected, the dynamic range that is the difference between the maximum value and the minimum value is detected, and the original quantization is performed in accordance with the dynamic range. A high-efficiency encoding apparatus that quantizes each pixel data of the digital image signal with a smaller number of bits than the number of bits, comprising: detecting a level-direction frequency of the quantized data in the block unit; Depending on the output frequency information,
Re-quantization is performed by allocating a smaller number of bits than the number of bits to data having a higher frequency, and transmitting at least two of the frequency information, the maximum value, the minimum value, and the dynamic range. A high-efficiency coding device characterized by the above.