JP3046116B2 - Discrete cosine transformer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a discrete cosine transform (D
More specifically, the present invention relates to a discrete cosine transformer that performs a two-dimensional discrete cosine transform operation.

[0002] DCT is known as a conversion method suitable for compressing image data. There are a forward DCT for converting image data into frequency components and a reverse DCT (IDCT) for performing inverse transform to restore image data. In this specification, both are called DCT, and when only one is indicated, These will be referred to as forward (forward) DCT and reverse (reverse) DCT.

[0003]

2. Description of the Related Art In recent years, DCT, which is one method of orthogonal transformation, has been widely adopted as a data compression method.

FIG. 3 shows an image data compression technique using DCT. As shown in FIG. 3A, the target screen 5
0 is divided into small subsections 51. The small section 51 has a size of, for example, 8 pixels × 8 pixels. That is, the small section 51 forms an 8 × 8 square matrix including 64 elements. The image information on the screen 50 is processed for each small section 51.

As shown in FIG. 3B, image data 52 of a small section 51 is processed by a forward DCT processor 53 to obtain a DCT coefficient (F) 54. This DCT coefficient 54
Is obtained by frequency-analyzing image information in a row direction and a column direction. The DCT coefficient 54 is processed by the threshold processing device 55, and data below a certain value is discarded. Next, in order to reduce the non-zero data length, the data is divided by a constant value by the normalization processing device 56 to obtain shortened data 57.

The image data 57 thus obtained is
Is non-zero and zero, but the high frequency component is almost zero. For non-zero data, Huffman coding is performed, and the data is further compressed. For zero data, run-length encoding is performed, a block of zeros is treated as one data, and Huffman encoding is performed.

When the original image is reproduced from the compressed data obtained in this way, the image data 57 is first reproduced by decoding Huffman coding and the like, and then the reverse processing of the normalization processing is performed. Image information is reproduced by performing a reverse DCT process which is a reverse process of the directional DCT process.

FIG. 3 (C) shows the forward direction D shown in FIG. 3 (B).
The content of the CT processing is shown. The DCT coefficient F is obtained by sandwiching the image data f between the transposed cosine coefficient matrix ^Dt and the cosine coefficient matrix D and performing a matrix operation.

[0009] Incidentally, when the forward DCT process further deployment, expressed as ^{F = D t fD = {(} fD) t D} t. That is, the image data f is multiplied by the cosine coefficient matrix D from the right side, frequency analysis in the row direction is performed, the obtained matrix is transposed to convert the row direction and the column direction, and the cosine coefficient matrix D is again multiplied. By performing the frequency analysis in the column direction and transposing, the row direction and the column direction are returned to the original state, and the DCT coefficient F obtained by frequency-analyzing the image information in the row direction and the column direction can be obtained. To perform such an operation, it is necessary to repeat the matrix multiplication twice.

FIG. 4 shows a transform coefficient matrix used for forward DCT and inverse DCT when the block size is 8 × 8. Figure 4 shows a cosine coefficient matrix D and transposed cosine coefficient matrix D ^t to (A).

When the forward DCT is performed according to the above equation, a cosine coefficient matrix D is stored in a memory,
The multiplication (product-sum operation) of the input signal and the cosine coefficient matrix D may be performed.

The inverse DCT transform is an operation for reproducing the image information f from the DCT coefficient F, and is expressed as f = DFD ^t = (F ^t D ^t ) ^t D ^t = ｛(FD ^t ) ^t D ^t ｝ ^t. You.

Therefore, to perform the inverse DCT transform,
The DCT coefficient F is multiplied by the transposed cosine coefficient matrix D ^t from the right, the obtained result is transposed to exchange rows and columns, the transposed cosine coefficient matrix D ^t is multiplied again from the right, and the obtained result is transposed. Then you can return the rows and columns to their original state.

When both the image data f and the cosine coefficient matrix D are 8 × 8 matrices, the multiplication is an 8 × 8 matrix multiplication. In order to perform such forward DCT or inverse DCT processing, eight multipliers will be used.

Observe the cosine coefficient matrix D
And in each column, the first to fourth rows and the fifth to eighth rows
It turns out that it has a symmetrical configuration separately. sand
That is, the element of a certain column of the cosine coefficient matrix D is represented by D₀~ D₇
Then D₀= ± D₇, D ₁= ± D₆, D_Two= ±
D_Five, D_Three= ± D_FourThere is a relationship. This code is
Plus in odd columns and my in even columns
It becomes eggplant.

Therefore, multiplications having the same coefficients can be put together, and one multiply-add operation can be executed by four multiplications. Utilizing such a symmetry of the transformation matrix, DCT transformation using a high-speed algorithm has also been proposed.

Incidentally, the coefficient of the product-sum operation in the DCT transform is determined by the block size and is fixed. Therefore, the DCT operation can be performed by storing the operation result in the ROM and using the result as a look-up table.

As one method of matrix multiplication, DA (Dist
A known Arithmetic algorithm is known. Consider a matrix multiplication of Y = A · X. X is m bits. The matrix operation for one column is expressed as follows.

[0019]

(Equation 1)

[0020] In this ^{case, X = -x (m-1} ) · 2 m-1 + Σ M x
^(M) · ^2M . Therefore, the equation (i) is expressed as follows: Y _i = Σ _j A _ij X _j = Σ _j (−A _ij x _j ^(m−1) · 2 ^(m−1) + Σ _M A _ij x _j ^(M) · 2 ^M …… (ii). Here, x ^(M) represents the M-th bit of X, and its value is “0” or “1”.

Equation (ii) is further expressed as Y _i = − (Σ _j A _ij x _j ^(m−1) ) · 2 ^m−1 + Σ _M (Σ _j A _ij x _j ^(M) ) · 2 ^M Is done. The first term on the right side indicates the sign bit, and the second term indicates the multiplication for each bit of X. Where x _j ^(M)
Is “0” or “1”, and if A is a matrix of n rows and n columns, the addition of j = 0 to (n−1) of A _ij is performed.

Therefore, if the parentheses are configured with a look-up table based on x _j, it is possible to calculate Y _i of matrix multiplication by shifting and addition / subtraction depending on the bit position.
In the case where the DCT operation is configured by hardware, if the speed is to be increased by using a multiplier, the hardware becomes large, so that the multiplier is not desired to be used as much as possible. The DA algorithm is appropriate as a technique for performing multiplication without using a multiplier.

FIG. 5 shows an example of a two-dimensional DCT operation circuit using such a DA algorithm. FIG.
FIG. 5B schematically shows the configuration of the one-dimensional processing unit, and FIG.
3 shows a configuration of a DA product-sum operation block in a dimensional processing unit.

In FIG. 5A, input data is input to a one-dimensional DCT processing unit 61, subjected to DCT conversion using a look-up table, and an output is supplied to a shift / round circuit 62. The shift / round circuit 62 is D
The signal whose number of bits has been increased by the CT processing is again adjusted to the desired number of bits, and rounding processing is performed.

The output of the shift / round circuit 62 is supplied to a transposition RAM 63, and the rows and columns are exchanged. The transposed signal is supplied to another one-dimensional DCT processing unit 64, subjected to frequency analysis in other directions, and shifted / shifted.
It is supplied to the round circuit 65. The shift / round circuit 65 adjusts the number of bits again, performs rounding processing, and forms output data.

FIG. 5B shows the one-dimensional D shown in FIG.
The configuration of each of the CT processing units 61 and 64 is schematically shown. That is, in the one-dimensional DCT processing unit,
The input data is provided to a pre-processing circuit 66 to form an appropriate combination of input signals. The input signal converted in this manner is input to DA product-sum operation blocks 67 and 68 which are divided into two sets.

For example, when an image signal is an 8 × 8 block, eight input signals are supplied as input data, and four sets of signals supplied by a preprocessing circuit 66 are supplied to a DA product-sum operation block 67. Is the DA product-sum operation block 6
8 is supplied.

As described above, dividing the DA product-sum operation block into two is preferable because the size of the look-up table is not excessively large and the symmetry of the DCT transform matrix is used. The output signals of the DA product-sum operation blocks 67 and 68 are supplied to a post-processing circuit 69, where the number of bits is reduced and rounding is performed. In this way, output data is generated from the post-processing circuit 69.

FIG. 6 shows such a look-up table.
1 shows a basic configuration of a DCT operation processing circuit using. n
The input signal stores a DCT transform lookup table
Supplied to the coefficient ROM 81 as an address,
The sum-of-products operation is performed by the table. Looka
The output signal of the table 81 is input x_jIs a sign bit
In the case of the adder 8, after the sign is inverted by the signal Ts,
3 through the output signal Y _iTo form

The output signal Y _i is _supplied to a coefficient circuit 84.
Is returned to the adder 83. Next, the input signal on one bit is stored in the look-up table 81.
, And the same operation is performed, and an output signal is supplied to the adder 83. The output signal is supplied to a coefficient circuit 84.
Through the digit alignment has been previously calculated results are summed, a new output signal Y _i are formed. At this time, a coefficient circuit 84 is used to align the bit positions.

Assuming that each input signal has 15 bits, the operation usually requires 15 cycles. However, in order to process an 8 × 8 block in real time, the calculation must be completed within eight cycles even if a pipeline is used. Therefore, by taking out the input signal two bits at a time and doubling the look-up table, the arithmetic processing can be completed in eight cycles.

By the way, as is apparent from the conversion matrix of FIG. 4A, the cosine coefficient matrix D has a symmetrical structure in which 1 to 4 rows and 5 to 8 rows of each column are symmetric. Therefore, the same lookup table can be used for rows 1 to 4 and rows 5 to 8 of the transformation matrix. Therefore, enter 8
It is effective to divide these signals into groups of four and use a look-up table for each group.

FIG. 7 shows that input signals are divided into groups of four in the DCT transform having the 8 × 8 configuration, and each signal is divided into two groups.
3 shows a configuration of a DCT operation circuit that supplies bit by bit. The coefficient ROM 81a and the coefficient ROM 81b have the same look-up table, and input a set of upper bits and a set of lower bits of four input signals. The output signal of the look-up table 81b for inputting the lower bit is multiplied by １ ／ by the coefficient circuit 86, and is added to the output signal of the upper bit look-up table 81a in the adder.

When the input is a sign bit, the signal T
The sign is inverted by s and added to form an output signal Y _i via an adder 83. The output signal Y
_i is fed back to the adder 83 via the coefficient circuit 87.
The coefficient circuit 87 multiplies the output signal Y _i by １ ／ to adder 83
Return to. This is to adjust that the same numerical value becomes four times larger in the subsequent operation because the operation is performed every two bits.

FIG. 5C shows the one-dimensional DCT of FIG.
2 shows a configuration of a DA product-sum operation block used in the processing unit. Each DA product-sum operation block inputs four sets of input signals two bits at a time.

The four sets of input signals for each two bits are:
The upper bits are divided into upper bits and lower bits. The lower bits are supplied to a lower bit look-up table 71a or 72a, and the upper bits are supplied to an upper bit look-up table 71b or 72b.

That is, the lower bit look-up tables 71a and 72a and the upper bit look-up tables 71b and 72b have different bit positions, but receive the same combination of input signals and perform the same conversion.

Lower bit look-up table 71
a and 72a are supplied to a coefficient circuit 73,
/ 2 times and supplied to the adder 74. The output signals of the upper bit look-up tables 71b and 72b are directly supplied to the adder 74.

The number of digits of the upper bit and the lower bit is made uniform by the coefficient circuit 73, and the addition is performed in the adder 74. The output signal of the adder 74 is supplied to an accumulator 75 to form a cumulative sum. The accumulator 75 includes an adder 74, a register 78, a shifter 7,
9 and the previous output signal is bit-shifted by the shifter 79 and fed back to the adder 77.

In this way, the adder 77 adds the previous output signal and the current output signal and stores the result in the register 78. For example, to calculate in order from the least significant bit,
The shifter 79 multiplies the output by 1/4 and performs digit alignment with the next calculation. When the calculation is performed from the upper bits, shifter 79 multiplies the output signal by four times and performs digit alignment with the next calculation.

In this way, the DCT operation is performed using the DA product-sum operation block shown in FIG. In the case of inverse DCT operation, transformation matrix is transposed matrix D ^t shown in FIG. 4 (A). D ^t does not have the symmetry like the transformation matrix D, but considering odd rows and even rows separately, the first column and the eighth column, the second column and the seventh column, the third column and the Six rows, the fourth row, and the fifth row each have a symmetric configuration.

Therefore, in the case of the inverse DCT operation, by dividing the transformation matrix into odd rows and even rows, the forward DCT
Look-up table reduction similar to conversion can be performed.
Table 1 shows the contents of the lookup table in the case of using the configuration in FIG.

[0043]

[Table 1]

[0044]

[Table 2]

[0045]

[Table 3]

[0046]

[Table 4]

[0047]

[Table 5]

[0048]

[Table 6]

[0049]

[Table 7]

[0050]

[Table 8]

The forward DCT look-up tables in Tables 1 to 8 correspond to the first to eighth columns of the transformation matrix, and the input signals x1 to x4 correspond to the first to eighth rows of the transformation matrix.
Corresponds to the fourth row.

The look-up table for inverse DCT is shown in Table 1.
No. 0 in Table 2 and No. 1 in Table 2 correspond to the first and eighth columns, No. 0 corresponds to an odd-numbered row, and No. 1 corresponds to an even-numbered row. Similarly, the look-up table for inverse DCT is shown in Table 3
No. 2 in Table 4 and No. 3 in Table 4 correspond to the second and seventh rows, No. 4 in Table 5 and No. 5 in Table 6 correspond to the third and sixth columns,
No. 6 in Table 7 and No. 7 in Table 8 correspond to the fourth and fifth columns.

Looking at the numerical values of the lookup tables shown in Tables 1 to 8, for No. 1, No. 3, No. 5, and No. 7, the forward DCT look-up table and the inverse DCT look-up table are shown. Are the same. Therefore, they can share a look-up table.

Basically, as shown in FIG. 5C, each of the eight DA product-sum operation blocks in FIG.
One lookup table is required, and one-dimensional DCT is performed using 4 × 8 = 32 lookup tables. To perform a two-dimensional DCT transform, 32 × 2
= 64 lookup tables are required.

However, as shown in Tables 1 to 8,
There are portions where the look-up tables can be shared for the forward DCT operation and the inverse DCT operation, and when these are shared, the number of necessary lookup tables is 48.

Further, the look-up tables shown in Table 1 have higher symmetry, and the configuration can be further simplified by using them. FIG.
An example in which the configuration of a DCT conversion circuit is further simplified by using the symmetry of a look-up table will be described. As shown in FIG. 8A, for example, look-up table No.
In the case of 0, when 8192 is equally subtracted from the numerical value of the content, the upper half and the lower half of the table have a symmetrical configuration.

That is, if the other bits are exclusively ORed with bit x4 and the sign is inverted, the contents of the look-up table can be halved. FIG. 8B shows a configuration of a DA product-sum operation block using such symmetry. The look-up tables 88a and 88b have half the contents of the look-up tables 81a and 81b shown in FIG. 7, and receive three types of input signals formed by the exclusive OR circuit.

The signal x4 is further supplied to a sign inverter via an exclusive OR circuit. Other configurations are the same as those in FIG. As described above, in order to simplify the configuration of the DCT operation processing device, it is necessary to simplify the operation using the symmetry of the cosine coefficient matrix or the transposed cosine coefficient matrix.

Therefore, it is necessary to group input signals using the same transform coefficient. In order to form a plurality of desired combinations of input signals from a plurality of input signals, a butterfly circuit, which is a combination of addition and subtraction circuits, is used.

FIG. 2 shows an example of the configuration of a two-dimensional DCT operation processing device in which the operation results of the DCT operation are stored in a table in a ROM. The input signal is input to the shift register 121 and supplied to the butterfly circuit 122 and the switching unit 123 in parallel. The butterfly circuit 122 forms a desired combination of input signals from a plurality of input signals, and supplies an output to the switching unit 123.

Switching section 123 determines which input signal is to be selected by a forward / reverse switching signal indicating whether the DCT processing unit performs forward DCT operation or inverse DCT operation. The input signal selected by the switching unit 123 is supplied to the operation ROM unit 124 and subjected to a matrix operation.

The output signal of the operation ROM section 124 is supplied to the switching section 126 and the butterfly circuit 125 in parallel. The butterfly circuit 125 creates a desired combination of a plurality of input signals from the plurality of input signals, and supplies the output signal to the switching unit 126.

Switching section 126 determines which input signal is to be selected according to a forward / reverse switching signal indicating whether to perform forward DCT operation or inverse DCT operation. The signal selected by the switching unit 126 is stored in the accumulator 1
The calculation result for each bit which is supplied to 27 and sequentially supplied is added.

The output signal of accumulator 127 is supplied to transposition circuit 130 via shift register 128,
Transpose rows and columns. The signal transposed by the transposition circuit 130 has another one-dimensional DCT having the same configuration as that described above.
The processing unit is supplied.

That is, the other DCT operation processing units include a shift register 131, a butterfly circuit 132, a switching unit 133, an operation ROM 134, and a butterfly circuit 13
5, including a switching unit 136, an accumulator 137, and a shift register 138.
The same operation as described above is performed, and the operation result is supplied as an output signal.

[0066]

As described above,
When using the cosine coefficient matrix for performing the DCT operation or the symmetry of the transposed cosine coefficient matrix, a two-dimensional D
To perform a CT operation, four butterfly circuits are required.

An object of the present invention is to provide a discrete cosine transformer having a simple configuration.

[0068]

SUMMARY OF THE INVENTION A discrete cosine transformer according to the present invention includes a first one-dimensional discrete cosine transform circuit, a transpose circuit, and a second one-dimensional discrete cosine transform circuit.
Dimensional discrete cosine transformer, wherein said first and second
Has a one-dimensional discrete cosine processing circuit, a pre-processing circuit and a post-processing circuit connected to an input side and an output side thereof, respectively, and the first one-dimensional discrete cosine processing circuit And a post-processing circuit of the second one-dimensional discrete cosine processing circuit include a common first butterfly circuit, and a post-processing circuit of the first one-dimensional discrete cosine processing circuit and the second one-dimensional discrete cosine processing circuit. The processing circuit in which the one-dimensional discrete cosine processing circuit performs includes a common second butterfly circuit.

[0069]

When a forward DCT operation is performed, a desired combination of input signals input to the DCT operation circuit must be formed by a butterfly circuit. However, an output signal of the DCT operation circuit does not need to pass through the butterfly circuit. What is necessary is just to supply directly. Conversely, when performing the inverse DCT operation,
The input signal of the DCT operation circuit does not need to pass through the butterfly circuit, and the output signal needs to be supplied to the butterfly circuit.

When performing a two-dimensional DCT operation, two of the four butterfly circuits are used, but the remaining two are not used. Therefore, when performing a two-dimensional DCT operation, it is sufficient that two one-dimensional DCT operation circuits and two butterfly circuits can be used.

As described above, when the two-dimensional discrete cosine transform is performed, the butterfly circuit is shared,
Two butterfly circuits can be omitted.

[0072]

FIG. 1 shows the configuration of a two-dimensional DCT processing unit according to an embodiment of the present invention. The plurality of input signals are supplied to the input buffer 101 and sent from the input buffer 101 to the selector 102.

The selector 102 supplies the input signal directly to the one-dimensional DCT operation circuit 105 or
03 to be supplied. The output signal of the butterfly circuit 103 is supplied to a one-dimensional DCT circuit 105. That is, the input signal is one-dimensional DC by the selector 102.
The signal can be directly input to the T operation circuit 105 or can be input via the butterfly circuit 103.

The output signal of the one-dimensional DCT operation circuit 105 is supplied to the selector 106. The selector 106 is
Whether the input signal is directly supplied to the output buffer 108 or the butterfly circuit 107 is selected. The output signal of the buffer circuit 107 is supplied to an output buffer 108.

The output buffer 108 supplies the transposed circuit 110 with the signal subjected to the one-dimensional DCT operation processing. The transposition circuit 110 transposes the input signal and converts rows and columns of the matrix. The row and column converted matrix signal is applied to a transposition circuit 110
Is supplied to the selector 112 via the input buffer 111.

The selector 112 supplies the input signal directly to the one-dimensional DCT operation circuit 115 or the butterfly circuit 1
07 to be supplied. The output signal of the butterfly circuit 107 is supplied to a one-dimensional DCT operation circuit 115.

The output signal of the one-dimensional DCT operation circuit 115 is supplied to the selector 116. The selector 116 is
Whether the input signal is supplied directly to the output buffer 117 or the butterfly circuit 103 is selected. The output signal of the butterfly circuit 103 is supplied to an output buffer 117. The output buffer 117 supplies the output signal that has been subjected to the two-dimensional DCT operation processing.

In the case of the forward DCT operation, the selector 102 supplies the input signal to the butterfly circuit 103 and the selector 1
06 supplies the input signal directly to the output buffer 108.
On the other hand, the selector 112 outputs the input signal to the butterfly circuit 10.
7, and the selector 116 supplies the input signal directly to the output buffer 117.

As described above, the butterfly circuit 103 forms an input signal of the first one-dimensional DCT operation circuit 105, and the butterfly circuit 107 forms an input signal of the second one-dimensional DCT operation circuit 115.

In the inverse DCT operation, the selector 102
Supplies the input signal directly to the one-dimensional DCT operation circuit 105, and the selector 106 supplies the input signal to the butterfly circuit 107.
To supply. The selector 112 directly inputs the input signal to 1
The selector 116 supplies the input signal to the butterfly circuit 103.

As described above, the butterfly circuit 107 has the first
Is added or subtracted from the output signal of the one-dimensional DCT operation circuit 105,
The butterfly circuit 103 is a second one-dimensional DCT operation circuit 1
15 output signals are added or subtracted.

As described above, the two butterfly circuits 1
03 and 107 can constitute a two-dimensional DCT arithmetic processing device. The one-dimensional DCT operation circuits 105 and 11
5 may be a matrix multiplication or a ROM table.

FIG. 9 shows a configuration of a two-dimensional DCT operation processing device having a DCT operation result as a table in a ROM. The input signal is supplied to the parallel / serial conversion circuit 14 directly via the input buffer 11 or via the butterfly circuit 103, and supplied as a serial signal to the ROM accumulator 15a.

The ROM accumulator 15a performs a product-sum operation from a combination of input signals and outputs a result. The output signal of the ROM accumulator 15a is output directly or by the butterfly circuit 1.
07, is supplied to the output buffer 18, and from the output buffer 18 to the transposition RAM 20.

The transposing RAM 20 transposes the rows and columns of the input matrix signal and outputs a transposed matrix. The transposed output is supplied from the input buffer 21 via the butterfly circuit 107 or directly to the parallel / serial conversion circuit 24.

The signal converted to a serial signal is stored in a ROM
The DCT is supplied to the accumulator 15b. R
The OM accumulator 6b outputs the result of performing the product-sum operation from the input signal, similarly to the ROM accumulator 15a.

The output signal of the ROM accumulator 15b is sent to the output buffer 28 directly or via the butterfly circuit 103 to form an output signal. In the figure, in the case of the forward DCT transform, the butterfly circuit 103 is used in the first one-dimensional DCT transform, and the butterfly circuit 107 is used in the second one-dimensional DCT transform, as shown by the forward and reverse characters. used. A selector for distributing signals is not shown.

In the inverse DCT, the butterfly circuit 103 is used in the second one-dimensional DCT, and the butterfly circuit 107 is used in the first one-dimensional DCT.
In this way, a two-dimensional DCT operation processing device can be configured using two butterfly circuits.

The configuration of each unit for further simplifying the configuration of the two-dimensional DCT processing unit will be described below.
FIG. 10 schematically shows the configuration of the ROM accumulator 15. In this configuration, a plurality of input signals are grouped in pairs, and a look-up table is created for each pair. Look-up tables 1a and 1b store input signals I
1, 2 and I3, I4 are input in units of 2 bits, and the corresponding outputs are supplied to the adder 2.

Since the look-up tables 1a and 1b operate on input signals at the same bit position, their output bit positions are equal and simply added by the adder 2. The output of the adder 2 is supplied to an accumulator 6, where a cumulative sum is calculated. The accumulator 6 has an adder 3, a register 4,
The input signal is stored in the register 4 via the adder 3, and the output of the register 4 is fed back to the adder 3 via the shifter 5.

Therefore, the previous value stored in the register 4 is supplied to the adder 3 via the shifter 5 and added to a new signal. In this way, the cumulative sum is calculated.

The look-up tables 1c and 1b receive two signals, I5, I6 and I7 and I8, respectively, as in the case of the look-up tables 1a and 1b, and supply corresponding output signals.

As described above, by constructing a look-up table for inputting each input signal two bits at a time and selecting a combination of signals, the same look-up table can be commonly used for the forward DCT transform and the inverse DCT transform. The possibilities increase.

Hereinafter, the case where the block size is 8 × 8 will be described. When the block size is 8 × 8, the transformation matrix is as shown in FIG. It should be noted that the numerical values in this table give values shifted by 3 bits when the two-dimensional DCT transform is performed.

As described above, the transform matrix D used for the forward DCT transform has a configuration in which the upper half and the lower half are symmetrical in each column. Therefore, if four input signals are prepared for each column, a DCT transform operation can be performed.

[0096] Incidentally, the transform matrix D ^t used for the inverse DCT transform, since the matrix and the transformation matrix D is inverted, symmetry, such as D has been lost. However, the first of D ^t
Focusing on the column, the even-numbered rows are 5681, 4816, 3218, 1130 as shown in the left column of FIG.
Which is the same as the upper half of the second column of the transformation matrix D used for the forward DCT transformation. The numerical values of the even-numbered rows of the eighth column of D ^t, as shown in FIG. 4 (A), -5681, -481
6, -3218 and -1130, which are different in sign from the even-numbered row in the first column, but have the same absolute value.

[0097] Therefore, as shown in FIG. 4 (A), 2 column of the upper and lower transformation matrices D used in order DCT transform has a symmetrical structure, their conversion matrix D ^t used for the inverse DCT transform, respectively The even-numbered rows in the first and eighth columns also have a symmetric configuration. By using this symmetry, the look-up table can be shared.

[0098] The first column of the transformation matrix D ^t for the second column and the inverse DCT of the transform matrix D used in order DCT transformation,
Having described the eighth row of symmetry, the third column of the same symmetry second row and the seventh row in the fourth column and the D ^t of D, the sixth column of D and D ^t And the sixth column, the eighth column of D and D ^t
Of the fourth and fifth columns. These relationships are shown in FIG.

[0099] Furthermore, for the odd rows D ^t, it can be found the intersection between D. For example, the first of D ^t
When the odd-numbered rows are extracted for the column, they become 4096, 5352, 4096, and 2217 as shown in FIG. 4C. Of these, two 4096s are the first row of the first column of D,
Equivalent to the third row.

[0100] Also, the second row odd row of D ^t, as shown in FIG. 4 (C), the third row, the seventh row D
Is the same as the second and fourth rows in the third column. Thus, D ^t
When only the odd rows of are extracted and compared with the elements of D, half of them have commonality.

As is clear from FIGS. 4B and 4C,
The transform matrix D ^t used for the inverse DCT transform, divided into odd and even rows, when newly applying the number of rows for each of commonality with the transformation matrix used in order DCT transformation is evident.

Therefore, for the transform matrix D of the forward DCT transform, a set of the first and third rows of each column is formed, and a set of the second and fourth rows is formed. Of 1
The combination of the row and the third row, the combination of the second and the fourth rows, and the combination of the first and third rows of the even rows may be the combination of the input signals. . Tables 9 to 16 show conversion tables for each combination of two bits.

[0103]

[Table 9]

[0104]

[Table 10]

[0105]

[Table 11]

[0106]

[Table 12]

[0107]

[Table 13]

[0108]

[Table 14]

[0109]

[Table 15]

[0110]

[Table 16]

In Tables 9 to 16, Nos. 0 to 7 in the forward DCT look-up table correspond to the first to eighth columns of the transformation matrix D. Also, the look-up table for reverse DCT, No. 0 and No. 1 corresponds to the first row odd and even rows of D ^t, similarly, No. 2 and No. 3 is the second column of D ^t Nos. 4 and 5 correspond to the odd and even rows of the eye,
No. 6 and No. 6 correspond to the odd and even rows in the third column of ^t .
7 corresponds to the odd and even rows of the fourth column of D ^t.

In Tables 9 to 16, rows 2 and 4 of No. 0,
1, 2 and 3 lines of No. 2, 2 and 4 lines of No. 4, 1 and 3 lines of No. 6
Only the transform look-up table for forward DCT and inverse DCT
Is a different part in the conversion look-up table. Therefore, to construct these look-up tables, the number of ROMs may be 2 × 8 + 4 = 20. 2D DC
To configure the T arithmetic unit, 20 × 2 = 40 ROMs
Will suffice.

By observing the contents of the look-up table, half of the portion surrounded by the solid frame, that is, N of the look-up table for forward DCT,
o. No. 4 and No. 4 and No. 2 and No. 6 of the inverse DCT look-up table are formed by forming the sum or difference of the input signals of 2 bits each and performing a bit shift of 12 bits. can do. That is,
These operations can be performed without using a lookup table by using an addition / subtraction circuit and a bit shifter.

With such a configuration, 20 ROMs
Required ROM can be further omitted
Becomes 16. In order to realize a two-dimensional DCT operation device, 16 × 2 = 32 ROMs are sufficient.

With such a configuration, 20 ROMs
Required ROM can be further omitted
Becomes 16. In order to realize a two-dimensional DCT operation device, 16 × 2 = 32 ROMs are sufficient.

FIG. 11 shows a portion of the ROM accumulator of the DCT arithmetic unit using the above-mentioned table. Coefficient ROM 1a,
1b has a look-up table, and uses two types of inputs x1, x3 and x2, x4 of 2 bits each as input signals. Since the combination of input signals is 4 bits, the content of the coefficient ROM is 16 words.

In addition, an adder 7, a coefficient circuit 8 by bit shift, and a selector 9 are further connected to one coefficient ROM, the coefficient ROM 1b in the case shown. The circuit by the elements 7, 8, 9 is for forming an output signal from the sum or difference of the input signals when the look-up tables for the forward DCT transform and the inverse DCT transform are different. It is omitted when the lookup tables are the same.

Also, a case has been shown in which an arithmetic circuit by bit shifting is added to the coefficient ROM 1b, but this arithmetic circuit is connected to the coefficient ROM 1a depending on the block. The selector 9 is for selecting either the output of the coefficient ROM 1b or the output by bit shift.

The output signal of the coefficient ROM 1a and the output signal of the selector 9 are added by the adder 2 and output via the adder 3. The output signal is fed back to the adder 3 via the coefficient circuit 5 by bit shift.

That is, since the bit position changes successively in the subsequent operation, alignment is performed to form a cumulative sum. When the input is a sign bit, the signal Ts
Sign is inverted.

FIG. 12 shows the configuration of a one-dimensional DCT processing system. The input signal is input to the input buffer 11 and supplied from the input buffer to the parallel / serial conversion circuit 14 via the butterfly circuit 12 or the bypass 13.

In the case of the forward DCT, the input signal is supplied from the input buffer 11 to the butterfly circuit 12, and the sum or difference of two types of input signals, ie, f0 + f7, f1 + f6, f
2 + f5, f3 + f4, f0-f7, f1-f6, f2
-F5 and f3-f4 are formed. These signals are supplied to the parallel / serial conversion circuit 14, where two bits are output.

In the case of the inverse DCT, the output of the input buffer 11 is supplied directly to the parallel / serial conversion circuit 14 via the bypass 13. In the parallel / serial conversion circuit, the odd-numbered input signals f0 + f2, f4,
f6 and the even-numbered input signals f1, f3, f5, and f7 are separately accommodated.

The outputs of the parallel / serial conversion circuit 14 are respectively grouped into four to form two 8-bit signals. This signal is supplied to a ROM accumulator 10 having a plurality of configurations as shown in FIG. 11, and a lookup table is selected according to a calculation position, and an output signal is formed. The output signal of the ROM accumulator 10 is
6 or supplied to an output buffer 18 via a bypass 17. Thus, the output signal is supplied from the output buffer 18.

In the forward DCT, the output signal of the ROM accumulator 10 passes through the bypass 17, and in the inverse DCT, the output signal of the ROM accumulator 10 is
6 to an output buffer 18. Thus, a one-dimensional DCT operation is performed.

FIG. 13 shows an equivalent circuit in the case of a two-dimensional DCT operation. In FIG. 13, an input buffer 11, a butterfly circuit 12, a bypass 13, a parallel / serial conversion circuit 14, a ROM accumulator 10a, a butterfly circuit 1
6, bypass 17, and output buffer 18 are equivalent to the corresponding parts shown in FIG.

That is, the one-dimensional D
CT conversion is performed. The one-dimensional DCT-converted signal is converted into rows and columns by the transposition ROM 20 and supplied to the input buffer 21. An input buffer 21, a butterfly circuit 22, a bypass 23, a parallel / serial conversion circuit 24, a ROM accumulator 10b, a butterfly circuit 26,
The bypass 27 and the output buffer 28 are connected to another one-dimensional DCT.
An arithmetic circuit is configured to execute a second-dimensional DCT operation.
In this way, an output signal subjected to DCT processing in the two-dimensional direction is formed.

The values of the look-up tables shown in Tables 9 to 16 can be halved by taking the exclusive OR with the most significant bit b2 in the tables. For example, look-up table N for forward DCT
Regarding o.0, subtracting the average value 12288 from the values in the table results in a symmetrical configuration in the upper half and the lower half. According to such a configuration, the capacity of the look-up table can be reduced to half.

FIG. 14 shows a configuration of a ROM accumulator using such a configuration. 4-bit input signals b2, b1, a
Exclusive OR of b2 and the remaining three b1, a2, and a1 is obtained for b2 and a1, and three signals are input to coefficient ROMs 31a and 31b. Coefficient ROM3
1a and 31b receive an input signal of 3 bits and have an 8-word configuration. The other points are the same as those of the circuit of FIG.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0131]

As described above, according to the present invention,
The butterfly circuit of the two-dimensional discrete cosine transformer can be reduced.

The chip size and power consumption of a semiconductor device for realizing a discrete cosine converter can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional technique.

FIG. 3 is a schematic diagram illustrating an image data compression technique using DCT according to a conventional technique.

FIG. 4 is a schematic diagram for explaining a DCT transform matrix.

FIG. 5 is a block diagram illustrating a configuration of a conventional DCT operation device.

FIG. 6 is a block diagram showing a main part of a DCT operation device according to a conventional technique.

FIG. 7 is a block diagram illustrating a main part of a DCT operation device according to a conventional technique.

FIG. 8 is a table and a block diagram showing a main part of a DCT operation device according to a conventional technique.

FIG. 9 is a block diagram illustrating a main part of a DCT operation device according to an embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a ROM accumulator of the DCT operation device.

FIG. 11 is a block diagram showing another configuration of the ROM accumulator of the DCT operation device.

FIG. 12 is a block diagram showing a one-dimensional operation part of the DCT operation device.

FIG. 13 is a block diagram showing an equivalent circuit of the two-dimensional DCT operation device.

FIG. 14 is a block diagram showing another configuration of the ROM accumulator of the DCT operation device.

[Explanation of symbols]

 Reference Signs List 1 lookup table 2, 3 adder 4 register 5 shifter 6 accumulator 7 adder 8 coefficient circuit (shifter) 9 selector 10 ROM accumulator 11 input buffer 12 butterfly circuit 13 bypass 15 ROM accumulator 14 parallel / serial conversion circuit 16 butterfly circuit 17 bypass 18 output buffer 20 transpose RAM 21 input buffer 22 butterfly circuit 23 bypass 24 parallel / serial conversion circuit 26 butterfly circuit 27 bypass 28 output buffer 101 input buffer 102 selector 103 butterfly circuit 105 one-dimensional DCT 106 selector 107 butterfly circuit 108 output buffer 110 Transpose circuit 111 Input buffer 112 Selector 115 One-dimensional DCT 116 Selector 117 Output buffer

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H04N 7/30 H04N 7/133 Z (56) References JP-A-3-95670 (JP, A) ) Proceeding of the SPIE-The International Society for Optical Engineering Vol. 1244 1990 pp.234-239 (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/14 G06T 9/00 H03M 7/30 H04N 1/41 H04N 1/415 H04N 7/30 INSPEC (DIALOG) JICST File (JOIS) WPI (DIALOG)

Claims (1)

(57) [Claims] A first one-dimensional discrete cosine transform circuit;
A two-dimensional discrete cosine transformer having a transpose circuit and a second one-dimensional discrete cosine transform circuit, wherein the first and second one-dimensional discrete cosine transform circuits are each a one-dimensional discrete cosine processing circuit (105, 115)
And a pre-processing circuit and a post-processing circuit connected to the input side and the output side thereof. The pre-processing circuit of the first one-dimensional discrete cosine processing circuit and the second one-dimensional discrete cosine processing circuit The post-processing circuit includes a common first butterfly circuit (103), and the post-processing circuit of the first one-dimensional discrete cosine processing circuit and the pre-processing circuit of the second one-dimensional discrete cosine processing circuit are common. Of the second butterfly circuit (1
07).