JP3396818B2 - DCT operation circuit and IDCT operation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to DCT (Discrete Cosine Transform) used in image coding and IDCT (Inverse Discrete Cosine Transform) which is the inverse transform thereof.
) Is related to the arithmetic circuit.

[0002]

[Prior art]

(1) DCT / IDCT operation X _i (i = 0,1,2,3,4,5,6,7) is used as an original signal, and Y _j (j = 0,
If 1,2,3,4,5,6,7) is the DCT transform coefficient, the 8-point one-dimensional DCT using the high-speed calculation algorithm is
Expression (2) is expressed. _{a 0 0 ~a 3 3, b} 0 0 ~b 3 3 are coefficients.

[0003]

[0004]

An 8-point one-dimensional IDCT using the high speed calculation algorithm is represented by the following equations (3) and (4). _{c 0 0 ~c 3 3, d} 0 0 ~d 3 3 are coefficients.

[0006]

[0007]

(2) First Example of Prior Art FIG. 8 is a block diagram showing the configuration of an 8-point one-dimensional DCT arithmetic circuit of the first example of the prior art. In this circuit, first, the calculation of the equation (1) is performed in 4 parallels in 4 clocks, and the calculation of the following equation (2) is performed in 4 parallels in 4 clocks.

The original signal X _i is stored in the data memory 2 which is addressed by the address generation circuit 1 in which the address is incremented by +1 and the original signals read from the original signal X _i are X ₀ , X ₁ , X _2. , X ₃ , X ₄ , X ₅ , X ₆ , X ₇
The register 4 of the shift register 3 is moved for each clock in this order.

The selector 5 selects the original signal from the shift register 3 in the order of X ₇ , X ₆ , X ₅ , X ₄ , X ₇ , X ₆ , X ₅ , X ₄ , and the selector 6 selects X ₀ , X ₁ , X ₂ , X ₃ , X
Select ₀ , X ₁ , X ₂ , X ₃ .

The adder / subtractor 7 receives the result, and X ₀ + X
₇ , X ₁ + X ₆ , X ₂ + X ₅ , X ₃ + X ₄ , X ₀ -X
_{7, X 1 -X 6, X} 2 -X 5, calculated in the order of X ₃ -X _4, the result is sent to the four multiplier-adder 9A-9D.

The coefficient memory 8 is an 8 W memory capable of storing four coefficients at one address, and the coefficient matrix of the above equation (1) is arranged in the first, second, and third columns in order from address 0. The 4th column is also the 1st column of the coefficient matrix of equation (2), 2
The third, fourth and fourth columns are stored.

Therefore, when the address is read from address 0 while incrementing the address by 1, the four coefficients in each column in the coefficient matrix of equation (1) are read out first, and then the coefficient matrix of equation (2). The four coefficients of each column are read.

The read coefficient is sent to four summing arithmetic units 9A to 9D which are composed of a multiplier 10, an adder 11, an output register 12 and a register 13.

From the above, the DCT conversion coefficients Y ₀ , Y ₂ , Y ₄ and Y ₆ can be obtained in the output register 12 and Y ₁ , Y ₃ , Y ₅ and Y ₇ can be obtained 4 clocks later. .

These DCT transform coefficients are fetched from the selector 14, and Y ₀ , Y ₂ , Y ₄ , Y ₆ , Y ₁ , Y ₃ ,
While moving the register 4 of the shift register 15 in the order of Y ₅ and Y ₇ , the selector 16 causes Y ₀ , Y ₁ , Y ₂ and Y
₃ , Y ₄ , Y ₅ , Y ₆ , Y ₇ are selected in this order and written in the data memory 17.

Regarding the technology relating to such a DCT arithmetic circuit, for example, Miyazaki, Nishitani, Edahiro, Kohinata, Mitsuhashi,
Iwata, "DCT LSI for HDTV", 1991,
It is described in SC-8-4, IEICE Spring National Convention.

(3) Second Example of Prior Art FIG. 9 is a block diagram showing the configuration of an 8-point one-dimensional IDCT arithmetic circuit of a second example of the prior art. Similar to the example shown in FIG. 8, in this circuit, the calculation of the formula (3) is first performed in 4 parallels in 4 clocks, and then the calculation of the formula (4) is performed in 4 parallels in 4 clocks. In FIG. 9, components having the same functions as those shown in FIG. 8 are designated by the same reference numerals.

The data memory 2 stores the DCT transform coefficient, and the DCT transform coefficient Y _j read from the DCT transform coefficient is stored in the data memory 2.
Shifts the shift register 18 for each clock in the order of Y ₀ , Y ₁ , Y ₂ , Y ₃ , Y ₄ , Y ₅ , Y ₆ , and Y ₇ .

Selector 19 shifts from shift register 18 to D
The CT conversion coefficients are Y ₀ , Y ₂ , Y ₄ , Y ₆ , Y ₁ , Y ₃ ,
Y ₅ and Y ₇ are selected in this order, and four product-sum arithmetic operators 9A to 9 are selected.
Send to D.

In the coefficient memory 8, the first column, the second column, the third column, and the fourth column of the coefficient matrix of the above equation (3) and the coefficient matrix 1 of the equation (4) are sequentially arranged from address 0. The second, third, fourth and fourth columns are stored. Among them, first, four coefficients of each column in the coefficient matrix of Expression (3) are read out, and then four coefficients of each column in the coefficient matrix of Expression (4) are read out. The read coefficient is sent to the four product-sum calculation operators 9D to 9D.

Therefore, the output register 12 first stores (X ₀ + X ₇ ) / 2, (X ₁ + X ₆ ) / 2, (X ₂ + X).
_{5) / 2, (X 3} + X 4) / 2 to obtain, after the four _{clocks, (X 0 -X 7) /} 2, (X 1 -X 6) / 2, (X 2
-X ₅₎ / 2, can be obtained _{(X 3 -X 4) / 2} .

While these original signals are moving in the shift register 20, the selector 21 is (X ₀ + X ₇ ) / 2.
(X ₁ + X ₆ ) / 2, (X ₂ + X ₅ ) / 2, (X ₃ + X
_{4) / 2, (X 3} + X 4) / 2, (X 2 + X 5) / 2,
(X ₁ + X ₆ ) / 2, (X ₀ + X ₇ ) / 2 in that order, and the selector 22 has (X ₀ −X ₇ ) / 2, (X ₁ −X ₆ ) /
_{2, (X 2 -X 5)} / 2, (X 3 -X 4) / 2, (X 3
_{-X 4) / 2, (X} 2 -X 5) / 2, (X 1 -X 6) /
2, select the data in the order of _{(X 0 -X 7) / 2} , and sends the adder-subtracter 23.

The adder / subtractor 23 first adds four times and then subtracts four times to obtain X ₀ , X ₁ , X ₂ , X ₃ , X ₄ , X.
_The original signal is written in the data memory 17 in the order of ₅ , X ₆ , X ₇ .

Regarding the technology relating to such an IDCT arithmetic circuit, similar to the first example of the prior art, for example, Miyazaki, Nishitani, Edahiro, Kohinata, Mitsuhashi and Iwata, "DCT LSI for HDTV", 1991, It is described in SC-8-4, IEICE Spring National Convention.

(4) Third Example of Prior Art FIG. 10 is a block diagram showing the configuration of an 8-point one-dimensional DCT arithmetic circuit of a third example of the prior art. In this circuit, unlike the first example of the prior art, the calculation of the equations (1) and (2) is alternately performed for each clock. In this FIG.
Components having the same functions as those shown in FIG. 8 are designated by the same reference numerals.

From the data memory 2 to X ₀ , X ₁ , X ₂ , X
_The original signals read out in the order of ₃ , X ₄ , X ₅ , X ₆ , X ₇ are set as 2 data 1 set in the data combiner 24.
(X ₀ , X ₇ ), (X ₁ , X ₆ ), (X ₂ , X ₅ ),
Input to the adder / subtractor 7 in the order of (X ₃ , X ₄ ).

In the adder / subtractor 7, X ₀ + X ₇ , X ₀ -X
_{7, X 1 + X 6,} X 1 -X 6, X 2 + X 5, X 2 -X
_5, X ₃ + X _4, are calculated in the order of X ₃ -X _4, the result is sent to the four multiplier-adder 25A to 25D.

In the coefficient memory 8, the first column of the coefficient matrix of the above formula (1) and the 1 of the coefficient matrix of the above formula (2) are sequentially arranged from address 0.
The second column of the formula (1), the second column of the formula (2), the third column of the formula (1), the third column of the formula (2), the fourth column of the formula (1),
The fourth column of equation (2) is stored.

Therefore, when the address is read from address 0 while incrementing the address by 1, the four coefficients of each column in the coefficient matrix of equation (1) and the four coefficients of each column in the coefficient matrix of equation (2) are read. The coefficients are alternately read. The read coefficient is sent to the four product-sum calculators 25A to 25D.

In the product-sum calculators 25A to 25D, accumulators 26 and 27 connected in series are used,
Equations (1) and (2) are calculated alternately, DCT conversion coefficients Y ₀ , Y ₂ , Y ₄ and Y ₆ are stored in the output register 28, and Y ₁ , Y ₃ , Y ₅ and are stored in the output register 29. Y ₇ is obtained.

These DCT transform coefficients are Y ₀ , Y ₁ , Y ₂ , Y ₃ , Y ₄ , Y ₅ , Y ₆ , Y ₇ by the selector 30.
Are selected in this order and written in the data memory 17.

The technique relating to the above DCT arithmetic circuit is described in, for example, Japanese Patent Application No. 4-307662 "Discrete Cosine Transform Device and Inverse Discrete Cosine Transform Device".

(5) Fourth Example of Prior Art FIG. 11 is a block diagram showing the configuration of an 8-point one-dimensional IDCT arithmetic circuit of a fourth example of the prior art. Similar to the third example of the prior art, this circuit differs from the first example of the prior art described above in that the calculations of the equations (1) and (2) are alternately performed for each clock. In FIG. 11, elements having the same functions as those shown in FIGS. 8 and 10 are designated by the same reference numerals.

The data memory 2 stores the DCT transform coefficient, and the DCT transform coefficient read from it is
_{Y 0, Y 1, Y 2} , Y 3, Y 4, Y 5, Y 6, is sent in the order of Y ₇ the four product-sum operation unit 25A to 25D.

Here, in the coefficient memory 8, the first column of the coefficient matrix of the equation (3), the first column of the coefficient matrix of the equation (4), and the second column of the equation (3) in order from the address 0. , The second column of equation (4),
The third column of equation (3), the third column of equation (4), the fourth column of equation (3), and the fourth column of equation (4) are stored.

Therefore, when the address is read from address 0 while incrementing by one, the four coefficients of each column in the coefficient matrix of equation (3) and the four coefficients of each column in the coefficient matrix of equation (4). The coefficients are alternately read. Then, the read coefficient is sent to the four product-sum calculators 25A to 25D.

In the product-sum calculators 25A to 25D, accumulators 26 and 27 connected in series are used.
Equations (3) and (4) are alternately calculated, and (X ₀ + X ₇ ) / 2, (X ₁ + X ₆ ) / are stored in the respective output registers 28.
2, (X ₂ + X ₅ ) / 2, (X ₃ + X ₄ ) / 2 are stored in the respective output registers 29 as (X ₀ −X ₇ ) / 2, (X ₁ −
_{X 6) / 2, (X} 2 -X 5) / 2, (X 3 -X 4) / 2
Can be obtained.

The selector 31 has (X ₀ + X ₇ ) / 2.
(X ₁ + X ₆ ) / 2, (X ₂ + X ₅ ) / 2, (X ₃ + X
_{4) / 2, (X 3} + X 4) / 2, (X 2 + X 5) / 2,
(X ₁ + X ₆ ) / 2, (X ₀ + X ₇ ) / 2 in that order, and the selector 32 selects (X ₀ −X ₇ ) / 2, (X ₁ −X ₆ ) /
_{2, (X 2 -X 5)} / 2, (X 3 -X 4) / 2, (X 3
_{-X 4) / 2, (X} 2 -X 5) / 2, (X 1 -X 6) /
2, select the data in the order of _{(X 0 -X 7) / 2} , and sends the adder-subtracter 23.

In the adder / subtractor 23, first four times are added and then four times are subtracted to obtain X ₀ , X ₁ , X ₂ , X ₃ ,
The original signal is stored in the data memory 1 in the order of X ₄ , X ₅ , X ₆ , X _7.
Write to 7.

The technology relating to such an IDCT conversion circuit is described in, for example, Japanese Patent Application No. 4-307662 "Discrete Cosine Transform Device and Inverse Discrete Cosine Transform Device", as in the third example of the prior art. .

[0042]

[0043]

[0044]

However, in the DCT arithmetic circuits shown in the above-mentioned first and third examples of the prior art, the data memory is connected to X ₀ , X ₁ , X ₂ , X ₃ , X ₃ .
_It is necessary to rearrange the original signals read in the order of ₄ , X ₅ , X ₆ , and X ₇ to form a pair.

That is, in the DCT arithmetic circuit, X ₀ , X ₁ , X ₂ , ...
_The original signals read out in the order of _{n - 2} and Xn _{- 1} are used as Xn _{- 1} and _Xn-
2 , X _{n- 3} , ..., X _{n / 2} , X _{n- 1} , X _{n- 2} ,
X _{n- 3} , ..., X _{n / 2} and X ₀ , X ₁ , X ₂ ,
_{·····, X n / 2- 1,} X 0, X 1, X 2, ···, X
_{n / 2-1} of must be sorted into two sets of sequences, there is a problem that because the circuit becomes complicated.

Further, in the DCT arithmetic circuits shown in the first and third examples of the prior art, a circuit for sending the output of the product-sum arithmetic unit to the data memory and the second and fourth examples of the prior art are shown. In the IDCT arithmetic circuit, (X ₀ + X ₇ ) / 2, (X ₁ + X ₆ ) / 2, (X <sub>2
+ X 5) / 2, (</sub> X 3 + X 4) / 2, (X 0 -X 7) /
_{2, (X 1 -X 6)} / 2, (X 2 -X 5) / 2, (X 3
Since the configuration of the circuit that rearranges −X ₄ ) / 2 and sends it to the adder / subtractor is different, when configuring a circuit that can execute both the CDT operation and the IDCT operation, the configuration for the DCT operation and the IDC operation
There is a problem that a separate structure for T calculation must be provided.

That is, when n / 2 product-sum calculators are used, a circuit for sending the output of the product-sum calculator to the data memory in the DCT calculator and an output from the product-sum calculator in the IDCT calculator are provided. There has been a problem that the circuit configuration sent to the adder / subtractor is different.

[0048]

[0049]

The present invention has been made to solve such a problem, and a first object thereof is a DCT operation with a small amount of hardware for reading an original signal from a data memory and sending it to an adder / subtractor. Is to provide a vessel.

A second object is to provide a circuit for sending the output of the product-sum operation unit of the DCT operation circuit to the data memory and a circuit for rearranging the data output from the product-sum operation unit of the IDCT operation circuit and sending it to the adder-subtractor. It is possible to make the configurations the same.

[0052]

[0053]

Means for Solving the Problems] DCT calculation circuit of the first aspect of the invention for this is, X ₀ the original signal from the lower side of the address to the upper _{side, X 1, X 2, ···} , X n-2 , X _n-1 [n =
2 ^k (k = 1, 2, 3, ...)]
From the first data memory and X ₀ ,
X _n-1 , X ₁ , X _n-2 , X ₂ , X _n-3 , ..., X
_{n / 2-1,} the intermediate register for storing a first address generation circuit for generating an address for reading out sequentially with the original signal X n _{/ 2,} the data read out from the first data memory,
The data stored in the intermediate register is input, addition and subtraction are repeated, and X ₀ + X _n-1 , X ₀ -X _n-1 , X ₁ + X
_{n-2, X 1 -X n} -2, X 2 + X n-3, X 2 -X n-3, ··
........, X _{n / 2-1} + X _{n / 2} , X _{n / 2-1} −X _{n / 2} are calculated in this order, and the output of the adder / subtractor is X ₀ + X
_{It corresponds} to a shift register that shifts in sequence from _n-1 for each clock, and n / 2 registers at every other stage among a plurality of registers that form the shift register.
The data stored in the corresponding register ,
When X ₀ + X _n-1 is stored in the first register, the first multiply-accumulate operator starts the multiply-accumulate operation, and then, every two clocks, the successive multiply-accumulate operator starts the arithmetic operation n / 2 And the n / 2 product-sum calculators for DCT calculation
A coefficient memory for sending / 2 coefficients individually at a time,
DCT coefficients Y ₀ , Y ₁ ,
Y ₂ , ..., Y _n-2 , Y _n-1 are taken out in this order, and the DCT coefficients are read from the lower address side to the higher address side of Y ₀ , Y ₁ , Y ₂ ,. A second data memory that stores Y _n-2 and Y _n-1 in this order, and the DCT coefficients Y ₀ and Y
The second in the order of ₁ , Y ₂ , ..., Y _n-2 , Y _n-1 .
Second to give the address to write to the data memory of
And an address generation circuit of.

The IDCT arithmetic circuit of the second invention is a DCT.
Coefficients from the lower address side to the higher address side of Y ₀ , Y ₁ ,
Y ₂ , ..., Y _n-2 , Y _n-1 [n = 2 ^k (k = 1,
2, 3, ...)] stored in the order of the first data memory and Y ₀ , Y ₁ , Y ₂ ,
..., a first address generating circuit for providing the address for reading the DCT coefficients in the order of _{Y n-2, Y n-} 1, the data read out from said first data memory from Y ₀ It corresponds to a shift register that shifts in sequence for each clock, and n / 2 registers at every other stage among a plurality of registers that constitute the shift register .
When the data stored in the register is fetched and the DCT coefficient Y ₀ is stored in the first register, the first product-sum operation unit starts the product-sum operation, and thereafter, every two clocks Of n / 2 product-sum calculators that start calculation and n / n for IDCT calculation in the n / 2 product-sum calculators.
(X ₀ + X _n-1 ) / 2 obtained from the coefficient memory for sending two coefficients individually at one time and the above n / 2 product-sum calculators
_{(X 0 -X n-1)} / 2, (X 1 + X n-2) / 2, (X 1 -
_{X n-2) / 2,} (X 2 + X n-3) / 2, (X 2 -X n-3) / 2,
・ ・ ・ ・ ・ ・ ・ ・, (X _{n / 2-1} + X _{n / 2} ) / 2, (X _{n / 2-1}
-X _{n / 2} ) / 2, and the data stored in the intermediate register are input and addition and subtraction are repeated to obtain X ₀ , X _n-1 , X ₁ , X _n-2 , X. ₂ , X _n-3 , ...
_{·····, X n / 2-1, X} 0 and adder-subtracter which calculates the order of X n _{/ 2} to obtain an original signal, the original signal from the lower side of the address to the upper side, X _1, X _2, ... A second data memory that stores X _n-2 and X _n-1 in this order, and an original signal that is output from the adder / subtractor to the second data memory, X ₀ ,
X _n-1 , X ₁ , X _n-2 , X ₂ , X _n-3 , ..., X
_Second to generate addresses to be written in the order of _{n / 2-1} and X _{n /} 2
And an address generation circuit of.

[0055]

[0056]

[0057]

[0058]

[0059]

In the present invention, first, in the DCT arithmetic circuit,
From the first data memory, X ₀ , X _{n- 1} , X ₁ , X _{n- 2} ,
_{X 2, X n- 3, ·······} , since reading the _{X n / 2- 1, X n} / 2 of the original signal in order, circuit rearranging the original signal is not required.

Further, the circuit of sending the output of the product-sum operator to the data memory in the DCT operation circuit and the circuit of sending the data output from the product-sum operator to the adder / subtractor in the IDCT operation circuit have the same configuration. Therefore, this circuit can be shared by the DCT operation circuit and the IDCT operation circuit.

Further, a DCT is performed by using a product-sum operator composed of n / 2 multipliers and an adder for adding their outputs.
When configuring the arithmetic unit or the IDCT arithmetic unit, the original signal or the DCT coefficient given to the DCT arithmetic unit or the IDCT arithmetic unit is read from the data memory one by one.

[0062]

EXAMPLES Examples of the present invention will be described below.

(1) First Embodiment FIG. 1 is a block diagram showing the configuration of an 8-point one-dimensional DCT arithmetic circuit of the first embodiment. In this circuit, the calculation of the formulas (1) and (2) is alternately performed for each clock, and the start of the calculation in the product-sum calculators 44A to 44D is delayed by two clocks to shift the shift register 43 to the original signal. Matrix operation is performed as it is done. As a result, DC
T calculation coefficient Y ₀ , Y ₁ , Y ₂ , Y ₃ , Y ₄ , Y ₅ , Y
₆ and Y ₇ are obtained every clock.

The address generation circuit 39, which will be described later, has 0, 7,
It is possible to generate addresses in the order of ₁ , ₆ , ₂ , ₅ , ₃ , 4, and the original signals are X ₀ , X ₇ , X ₁ , X ₆ , X ₂ , X from the data memory 2 for each clock. ₅ , X ₃ , X ₄
Are read in this order.

X ₀ , X ₁ , X ₂ and X ₃ are sent to the register 40 and further transferred to the register 41 in synchronization with the next rising edge of the clock. X ₇ , X ₆ , X ₅ , and X ₄ are sent to the resist 42. These registers 40 to 42 form an intermediate register.

Therefore, the adder / subtractor 7 uses X ₀ + X ₇ , X _0.
-X ₇ , X ₁ + X ₆ , X ₁ -X ₆ , X ₂ + X ₅ , X _2-
X ₅ , X ₃ + X ₄ , X ₃ −X ₄ are calculated in this order, and the result is sequentially sent to the shift register 43.

The shift register 43 has X ₀ + X ₇ , X _0.
-X ₇ , X ₁ + X ₆ , X ₁ -X ₆ , X ₂ + X ₅ , X _2-
X ₅ , X ₃ + X ₄ , and X ₃ -X ₄ are delayed by 2 clocks each and sent to the four product-sum calculators 44A to 44D.

The fact that the coefficient matrix of the equation (1) is stored in the even addresses of the coefficient memory 8 and the coefficient matrix of the equation (2) is stored in the odd addresses is the same as in the case of the prior art example 3 described above. The coefficient of each column in the matrix is shifted by 2 addresses as shown by the broken line with an arrow.

Therefore, when the address is read from the address 0 while incrementing the address by one, X ₀ + X ₇ , X ₀ -X ₇ , X ₁
+ X ₆ , X ₁ -X ₆ , X ₂ + X ₅ , X ₂ -X ₅ , X ₃ +
At the timing when X ₄ and X ₃ -X ₄ are sent to each of the product-sum calculators 44A to 44D, the above-mentioned formula (1) from the coefficient memory 8
Coefficients required to alternately calculate the equation (2) are sent to the product-sum calculators 44A to 44D.

Therefore, if the accumulation of the equation (1) is performed in the registers 45a to 45d of each of the product-sum calculators 44A to 44D and the accumulation of the equation (2) is performed in the registers 46a to 46d, one clock is delayed. The register 45a with Y ₀ and the register 46 with
Y _{1 for} a, Y _{2 for} register 45b, Y for register 46b
_3, it is possible to obtain a _{····, Y 0, Y 1,} Y
Data can be written in the data memory 17 in the order of ₂ , Y ₃ , Y ₄ , Y ₅ , Y ₆ , and Y ₇ . Incidentally, 47 to 49 are selectors.

FIG. 2 is a block diagram showing the structure of the address generating circuit 39 described above. 50 is an adder, 51 is an address pointer, and 52 is an ex-OR gate. This e
Due to the function of the x-OR gate 52, when the LSB of the 4-bit address pointer 51 is 0, the MSB 3 bits are directly output as an address, and when the LSB is 1, they are inverted and output.

Therefore, when the initial value is 0000, the address changes as follows. 000 → inversion 000 → 001 → inversion 001 → 010 → inversion 010 → 011 → inversion 011 000 → 111 → 001 → 110 → 010 → 101 → 0
11 → 100 That is, when the above is expressed in decimal, it becomes as follows. 0 → 7 → 1 → 6 → 2 → 5 → 3 → 4

Although only the case of generating an address from address 0 has been described above, this method is applied to eight consecutive addresses whose initial value is an address in which the lower 3 bits of the address of the data memory are 0. When the address is generated, the original signal can be placed at consecutive 8 addresses starting from the address in which the lower 3 bits in the data memory are 0.

As described above, in the address generation circuit of the first embodiment, the bit length of the address pointer is set to 1 in the lower order.
Bit expansion is performed to exclude the LSB from the 1st bit to the kth bit (k = 1, 2, 3, ...), that is, the lower k bits of the address to be given to the data memory. Of 2 bits, and the other input is given to the data memory through k 2-input ex-OR gates having the LSB of the address pointer.

This address generation circuit increments the value of the address pointer by +1 from the address A in which the lower k bits of the address given to the data memory, in other words, the lower k + 1 bits of the address pointer are all 0, thereby increasing A + 0, A +. (N-1), A +
1, A + (n-2), A + 2, A + (n-3), ...
.., A + (n / 2−1), A + (n / 2) in that order (n =
2 ^k ) to generate an address.

(2) Second Embodiment FIG. 3 is a block diagram showing the configuration of an 8-point one-dimensional IDCT arithmetic circuit according to the second embodiment of the present invention. In this circuit,
Equations (3) and (4) are calculated alternately for each clock. In addition, the start of calculation in the product-sum calculators 44A to 44D is delayed by 2 clocks, and the shift register 43 is set to DC
By performing the sum of products operation as the T transform coefficient is being shifted, X ₀ , X ₇ , X ₁ , X ₆ , X ₂ , X
The original signals of ₅ , X ₃ , X ₄ are obtained with a delay of one clock.

The DCT transform coefficients read from the data memory 2 are Y ₀ , Y ₁ , Y ₂ , Y ₃ , Y ₄ , Y ₅ , Y ₆ ,
The shift register 43 is moved for each clock in the order of Y ₇ , and the DCT transform coefficient is sent to the product-sum calculators 44A to 44D while being delayed by 2 clocks.

The coefficient memory 8 stores the coefficient matrix of equation (3) at even addresses and the coefficient matrix of equation (4) at odd addresses, as in the case of the prior art example 4. The coefficient in each column is shifted by 2 addresses as indicated by the broken line with an arrow.

Therefore, if the address is read from address 0 while incrementing by one, Y ₀ , Y ₁ , Y ₂ , Y ₃ , Y
₄ , Y ₅ , Y ₆ , and Y ₇ are sent from the coefficient memory 7 to the above equation (3) at the timing when they are sent to the respective product-sum calculators 44A to 44D.
Coefficients required to alternately calculate the equation (4) are sent to the product-sum calculators 44A to 44D.

Therefore, if the accumulation of the formula (3) is performed in the registers 45a to 45d and the accumulation of the formula (4) is performed in the registers 46a to 46d, the register 45a is delayed by one clock.
To (X ₀ + X ₇ ) / 2, and to the register 46 a (X ₀ −X 7
₇₎ / 2, in register _{45b (X 1 + X 6)} / 2, in register _{46b (X 1 -X 6) /} 2, can be obtained .......

Next, (X ₀ + X ₇ ) / 2, (X ₁ +
X ₆ ) / 2, (X ₂ + X ₅ ) / 2, (X ₃ + X ₄ ) / 2
To the register 53, shift to the register 54 in synchronization with the next rising edge of the clock, and (X ₀ -X
_{7) / 2, (X 1} -X 6) / 2, (X 2 -X 5) / 2,
When (X ₃ −X ₄ ) / 2 is sent to the register 55, the adder / subtractor 23 alternately repeats addition and subtraction to obtain X
_The original signal can be calculated in the order of ₀ , X ₇ , X ₁ , X ₆ , X ₂ , X ₅ , X ₃ , X ₄ . Registers 53 to 5 above
5 constitutes an intermediate register.

The address generation circuit 39 uses 0, 7, 1,
Addresses can be generated in the order of ₆ , ₂ , ₅ , ₃ , 4, and the original signals are stored in the data memory 16 every clock as X ₀ , X ₇ , X ₁ , X ₆ , X ₂ , X. ₅ , X ₃ , X
_It is written in the order of ₄ .

(3) No.Reference example of 1 FIG. 4 shows the present inventionFirst reference example related to8 points 1-dimensional DC
It is a block diagram which shows the structure of T arithmetic circuit. In this circuit
Are the third example of the prior art and the first example.
Similarly, calculation of equations (1) and (2) is performed for each clock.
Also, as in the first and third examples of the prior art described above, the sum of products
The arithmetic operations are simultaneously started in the arithmetic units 44A to 44D.

In the adder / subtractor 7, the original signals are X ₀ + X ₇ , X _0.
-X ₇ , X ₁ + X ₆ , X ₁ -X ₆ , X ₂ + X ₅ , X _2-
The calculation in the order of X ₅ , X ₃ + X ₄ , X ₃ −X ₄ is the same as in the first embodiment, but the result is 4
It is sent to each of the product-sum calculators 44A to 44D.

The arrangement of coefficients in the coefficient memory 8 is the same as in the third example of the prior art described above, and (1) is assigned to even addresses.
The coefficient matrix of the expression, and the coefficient matrix of the expression (2) is stored in the odd address.

The order of calculation is also the same as that of the third example of the prior art, and by performing the accumulation of the equation (1) in the registers 45a to 45d and the accumulation of the equation (2) in the registers 46a to 46d, First, the registers 45a to 45d are provided with Y ₀ , Y ₂ , and Y.
₄ , Y ₆ and Y ₁ , Y ₃ , Y ₅ , and Y ₇ can be obtained in the registers 46a to 46d at the next clock.

The shift register 56 shifts data every clock, transfers the DCT transform coefficients to the shift register 56 at the next clock when Y ₀ , Y ₂ , Y ₄ and Y ₆ are obtained, and continues. If you transfer _{Y 1, Y 3, Y 5} , Y 7 _{Te, Y 0, Y 1, Y} 2, Y 3, Y 4, Y 5, Y
Data can be written in the data memory 17 in the order of ₆ and Y ₇ .

In the present embodiment, the product-sum calculation unit 4
Instead of 4A to 44D, the product-sum calculators 25A to 25D shown in the third and fourth examples of the related art can be used.

(3) No.Reference example of 2 FIG. 5 shows the present inventionSecond reference example related to8 points 1-dimensional ID
It is a block diagram showing a configuration of a CT arithmetic circuit. This circuit
Then, with the fourth example and the second example of the prior art described above,
Similarly, the calculation of equations (3) and (4) is exchanged for each clock.
Mutually performed and similar to the second and fourth examples of the prior art described above.
Simultaneously start calculation in the product-sum calculators 44A to 44D
To do.

From data memory 2 to Y ₀ , Y ₁ , Y ₂ , Y
DCT read in the order of ₃ , Y ₄ , Y ₅ , Y ₆ , and Y _7.
The conversion coefficient is sent to the four product-sum calculators 44a to 44D, as in the fourth example of the related art.

The arrangement of the coefficients in the coefficient memory 8 is also the same as in the fourth example of the prior art. As in the case of FIG. 11, the coefficient matrix of equation (3) is used for even addresses and (4) for odd addresses. The coefficient matrix of the equation is stored.

Furthermore, the order of calculation is the same as that of the fourth example of the prior art. First, by performing the accumulation of equation (3) in registers 45a to 45d and the equation (4) in registers 46a to 46d, In the registers 45a to 45d, (X ₀ + X ₇ ) /
2, (X ₁ + X ₆ ) / 2, (X ₂ + X ₅ ) / 2, (X ₃
+ X ₄ ) / 2 is obtained, and at the next clock, the register 46a-
To _{46d (X 0 -X 7) /} 2, (X 1 -X 6) / 2,
_{(X 2 -X 5) / 2} , can be obtained _{(X 3 -X 4) / 2} .

Next, (X ₀ + X ₇ ) / 2, (X ₁ + X)
₆ ) / 2, (X ₂ + X ₅ ) / 2, (X ₃ + X ₄ ) / 2 are obtained, they are transferred to the shift register 56 at the next clock, followed by (X ₀ −X ₇ ) / 2. , (X ₁ -X ₆₎ /
_{2, (X 2 -X 5)} / 2, (X 3 -X 4) / 2 is transferred.

The functions of the registers 53 to 55 and the adder / subtractor 23 are the same as those in the second embodiment, and X ₀ , X ₇ , X ₁ , X.
_The original signal is obtained in the order of ₆ , X ₂ , X ₅ , X ₃ , X ₄ .

Also in the fourth embodiment, the product-sum calculators 25A to 25D shown in the third and fourth examples of the prior art can be used instead of the product-sum calculators 44A to 44D. .

(3) No.Reference example of 3 FIG. 6 shows the present inventionThird reference example related to8 points 1-dimensional DC
It is a block diagram which shows the structure of T arithmetic circuit. In this circuit
Is beforeNote: The power required to calculate equations (1) and (2)
An operation that sums the calculation results is executed at once.

In the adder / subtractor 7, the original signal is X ₀ + X ₇ , X _0.
-X ₇ , X ₁ + X ₆ , X ₁ -X ₆ , X ₂ + X ₅ , X _2-
The calculation in the order of X ₅ , X ₃ + X ₄ , X ₃ −X ₄ is the same as in the first and third embodiments, but the result is moved in the shift register 57 for each clock. Then
The final X ₃ −X ₄ is calculated, and at the next clock latched in the shift register 57, X ₀ + X ₇ , X ₁ + X ₆ ,
X ₂ + X ₅ and X ₃ + X ₄ are stored in the register 59 and X ₀ −.
X ₇ , X ₁ -X ₆ , X ₂ -X ₅ , and X ₃ -X ₄ are transferred to the register 58.

The selector 60 first selects the register 58 and the register 59 alternately, starting from the register 59.

The coefficient memory 8 stores the coefficient matrix of equation (1) at even addresses and the coefficient matrix of equation (2) at odd addresses, but not at each column in the coefficient matrix at the same address. , The coefficient of each row is placed.

Therefore, when the address is read while incrementing the address by one, the above equations (1) and (2) are alternately calculated, and the DCT transform coefficients Y ₀ , Y ₁ , Y ₂ , Y ₃ ,
It can be obtained in the order of Y ₄ , Y ₅ , Y ₆ , and Y ₇ .

(3) No.Reference example of 4 FIG. 7 shows the present inventionFourth reference example related to8 points 1-dimensional ID
It is a block diagram showing a configuration of a CT arithmetic circuit. This circuit
soIs the third reference exampleIn the same way as the above, the formulas (3) and (4) are calculated.
An operation that takes the sum of the four multiplication results required to calculate
Is executed once.

From the data memory 2 to Y ₀ , Y ₁ , Y ₂ , Y
DCT read in the order of ₃ , Y ₄ , Y ₅ , Y ₆ , and Y _7.
The conversion coefficient moves in the shift register 57 every clock, and the last Y ₇ is the next clock latched in the shift register 57, and Y ₀ , Y ₂ , Y ₄ , and Y ₆ are stored in the register 59. Y ₁ , Y ₃ , Y ₅ , and Y ₇ are transferred to the register 58.

The selector 60 first selects the register 58 and the register 59 alternately, starting from the register 59.

The coefficient memory 8 stores (3) in its even address.
In the coefficient matrix of the equation, the coefficient matrix of the equation (4) is stored at an odd address, but the coefficient of each column in the coefficient matrix is placed at the same address.

Therefore, when the address is read while incrementing the address by 1 from the address 0, the equations (3) and (4) can be alternately calculated, and the result is (X ₀ + X ₇ ) /
_{2, (X 0 -X 7)} / 2, (X 1 + X 6) / 2, (X 1
_{-X 6) / 2, (X} 2 + X 5) / 2, (X 2 -X 5) /
_{2, (X 3 + X 4} ) / 2, resulting in the order of _{(X 3 -X 4) / 2} .

The functions of the registers 53 to 55 and the adder / subtractor 23 are the same as those in the second and fourth embodiments, and X ₀ ,
The original signal is obtained in the order of X ₇ , X ₁ , X ₆ , X ₂ , X ₅ , X ₃ , X ₄ .

In the above, each embodiment is an 8-point DCT.
The operation circuit and the 8-point IDCT operation circuit have been described, but in the case of the n-point DCT operation circuit and the n-point IDCT operation circuit (n = 2 ^k , k = 1, 2, 3, ...). Easy to extend.

[0108]

As described above, according to the present invention, DC
In the T arithmetic circuit, X ₀ , X _{n− 1} , X from the data memory
_{1, X n- 2, X n-} 3, ······, X n / 2- 1, X n / 2
Since the original signals are read in this order, a circuit for rearranging the original signals becomes unnecessary, and the amount of hardware can be reduced.

When n / 2 product-sum calculators are used, a circuit for sending the output of the product-sum calculator to the data memory in the DCT calculator and an output from the product-sum calculator in the IDCT calculator. Since the configuration of the circuit to be sent to the adder / subtractor can be made the same, when configuring an arithmetic circuit capable of executing both DCT operation and IDCT operation, some circuits can be shared and the structure is simple. Has the advantage that

Further, when using a product-sum operator consisting of n / 2 multipliers and an adder for adding their outputs, it is only necessary to read the original signal or the DCT coefficient one by one from the data memory. It has the advantage of improving.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an 8-point one-dimensional DCT arithmetic circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an address generation circuit used in the present invention.

FIG. 3 is an eight-point one-dimensional IDCT according to a second embodiment of the present invention.
It is a block diagram which shows the structure of an arithmetic circuit.

FIG. 4 is a block diagram showing a configuration of an 8-point one-dimensional DCT arithmetic circuit according to a first reference example of the present invention.

FIG. 5 is an eight-point one-dimensional IDCT according to a second reference example of the present invention.
It is a block diagram which shows the structure of an arithmetic circuit.

FIG. 6 is a block diagram showing a configuration of an 8-point one-dimensional DCT arithmetic circuit of a third reference example of the present invention.

FIG. 7 is an eight-point one-dimensional IDCT according to a fourth reference example of the present invention.
It is a block diagram which shows the structure of an arithmetic circuit.

FIG. 8 is a block diagram showing a configuration of an 8-point one-dimensional DCT arithmetic circuit of a first conventional example.

FIG. 9 is a block diagram showing a configuration of a conventional eight-point one-dimensional IDCT arithmetic circuit of a second example.

FIG. 10 is a block diagram showing a configuration of an 8-point one-dimensional DCT arithmetic circuit of a third conventional example.

FIG. 11 is a block diagram showing a configuration of a conventional eight-point one-dimensional IDCT arithmetic circuit of a fourth example.

[Explanation of symbols]

Address generation circuit in which the address increases by 1: +1
2, 17: data memory, 3, 15, 18, 20, 4
3, 56, 57: shift registers for shifting one by one for each clock, 4, 12, 13, 26 to 29, 40 to 4
2, 45a to 45d, 46a to 46d, 53 to 55, 5
8, 59: register, 51: address pointer, 5,
6,14,16,19,21,22,30-32,47
49:60: selector, 7,23: adder / subtractor, 8: coefficient memory, 9A-9D, 25A-25D, 44A-44
D: multiply-accumulate operator having one multiplier and one adder, 1
0: multiplier, 11, 50: adder, 24: data combiner, 39: address generating circuit of the present invention, 52: ex-O
R gate.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yutaka Tashiro Yutaka Tashiro, 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Inside Nippon Telegraph and Telephone Corporation (56) Reference JP-A-4-307662 (JP, A) JP-A 59-81761 (JP, A) JP-A-2-100577 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 17/00-17/14 G06T 1/00-1 / 60 H03H 17/00-17/08 H04N 1/41-1/419

Claims (2)

(57) [Claims] 1. The original signal is transferred from the lower address side to the upper address side of the address by X.
₀ , X ₁ , X ₂ , ..., X _n-2 , X _n-1 [n = 2 ^k (k
= 1,2,3, a first data memory storing in the order of ····)], X ₀ from the first data memory, X _n-1, X _1, X
_A first address generation circuit that generates addresses for reading the original signal in the order of _n-2 , X ₂ , X _n-3 , ..., X _{n / 2-1} , X _{n / 2} ; Repeat the intermediate register for storing the data read from the data memory, the addition and subtraction to input data stored in the intermediate _{register, X 0 + X n-1} , X 0 -X n-1 , X ₁ + X
_{n-2, X 1 -X n} -2, X 2 + X n-3, X 2 -X n-3, ···
.... An adder _/ subtractor that calculates X _{n / 2-1} + X _{n / 2} , X _{n / 2-1} −X _{n / 2} in this order, and the output of the adder _/ subtractor in order from X ₀ + X _n-1. A shift register that shifts for each clock, and one of a plurality of registers that configure the shift register
Corresponding to n / 2 registers on each stage ,
When the data stored in the corresponding register is fetched and X ₀ + X _n-1 is stored in the first register, the first multiply-accumulate operation unit starts the multiply-accumulate operation, and then every two clocks An n / 2 multiply-add calculator for the arithmetic unit to start calculation, a coefficient memory for sending n / 2 coefficients for DCT calculation to the n / 2 multiply-add calculator individually at one time, and The DCT coefficient Y ₀ ,
Y ₁ , Y ₂ , ..., Y _n-2 , Y _n-1 are taken out in this order, and the DCT coefficient is read from the lower address side to the higher address side Y ₀ ,
A second data memory for storing Y ₁ , Y ₂ , ..., Y _n-2 , Y _n-1 in this order, and the DCT coefficients Y ₀ , Y ₁ , Y ₂ ,. Y
_A second address generation circuit for supplying addresses to be written to the second data memory in the order of _n-2 and Y _n-1 , and a DCT arithmetic circuit. 2. A DCT coefficient is transferred from the lower side of the address to the upper side of the address Y ₀ , Y ₁ , Y ₂ , ..., Y _n-2 , Y _n-1 [n
= 2 ^k (k = 1,2,3, ...)] in the order, and Y ₀ , Y ₁ , Y ₂ , ... From the first data memory.
- a first address generating circuit for providing the address for reading the DCT coefficients in the order of _{Y n-2, Y n-} 1, the data read from the first data memory Y ₀
A shift register that shifts for each clock in order from 1 to 1 of a plurality of registers that configure the shift register
Corresponding to n / 2 registers on each stage ,
When the data stored in the corresponding register is fetched and the DCT coefficient Y ₀ is stored in the first register, the first product-sum calculation unit starts the product-sum calculation, and then the subsequent product-sum calculation is performed every two clocks. And a coefficient memory for sending n / 2 coefficients for IDCT operation to the above n / 2 product-sum calculators at a time, respectively. (X ₀ + X obtained from n / 2 product-sum operators
_{n-1) / 2, (} X 0 -X n-1) / 2, (X 1 + X n-2) / 2,
_{(X 1 -X n-2)} / 2, (X 2 + X n-3) / 2, (X 2 -
X _n-3 ) / 2, ..., (X _{n / 2-1} + X _{n / 2} ) / 2
, (X _{n / 2-1} −X _{n / 2} ) / 2, and the data stored in the intermediate register are input to repeat addition and subtraction to obtain X ₀ , X _n−1 , X ₁ , X _n-2 , X ₂ ,
X _n-3 , ..., X _{n / 2-1} , X _{n / 2} are calculated in this order to obtain an original signal, and an original signal is added from the lower address side to the higher address side of the adder / subtractor. ₀ , X ₁ , X
_2, a second data memory for storing in the order of _{··· X n-2, X n} -1, the original signal output from the adder-subtracter to said second data memory, X _0, X _n-1 , X ₁ , X _n-2 , X ₂ ,
X _n-3 , ..., X _{n / 2-1} , X _{n / 2} , a second address generation circuit that generates an address to be written in order, and an IDCT operation circuit.