KR0126109B1 - Vlsi processor for dct/idct - Google Patents

Abstract

The present invention relates to a processor of an integrated circuit for discrete cosine transform / inverse transform in brain processing, which is simple in structure and can be operated in reverse order, and can reduce the occupied space of the integrated circuit and improve its processing speed. To provide a processor that can.

Performing a pre-addition multiplication operation or a post-subtraction multiplication operation by combining the butterfly calculation means 2 for performing butterfly association, the multiplication operation means 3 for performing simple multiplication operation, and the multiplication operation means 3; The auxiliary additive subtraction unit 32 and the data register 4 which access the intermediate result of the calculation process by the pressure reading port are combined to perform three steps of butterfly operation and one step of one-dimensional DCT / IDCT operation. Forming six steps that can perform simple multiplicative operations and multiplicative operations involving two steps of subtraction and multiplicative operations, the parallel calculation of the pipeline work method is performed by the butterfly calculation means 2 and the multiplication operation means 3. Run

Description

Integrated Circuit Processor for Discrete Cosine and Inverse Transforms

1 is a block diagram showing one configuration of an integrated circuit processor for discrete cosine transform / inverse transform according to the present invention.

2 is a time chart illustrating the flow of DCT operations executed by the processor of FIG.

3 is a time chart showing the flow of IDCT operations executed by the processor of FIG.

4 is a block diagram showing another configuration of an integrated circuit processor for discrete cosine transform / inverse transform according to the present invention.

5 is a time chart illustrating the flow of DCT / IDCT operations executed by the processor of FIG.

6 is an explanatory diagram showing a flow of a discrete cosine transform.

7 is an explanatory diagram showing the definition of each operation used for the discrete cosine transform / inverse transform, where (a) is a butterfly operation, (b) a simple multiplication operation, (3) a preaddition multiplication operation, and (4) It shows the definition of post-subtraction multiplication operation.

8 is an explanatory diagram showing a discrete cosine inverse transform.

* Description of the symbols for the main parts of the drawings *

1: input means 2: butterfly operation means

3: multiplication operation means 4: data register

5: output means 6: control means

31: second premultiplexer 32: auxiliary adder and subtractor

33: multiplier 34: coefficient ROM

35: output selector

The present invention relates to an integrated circuit processor, and more particularly to an integrated circuit processor for discrete cosine transform capable of inverse order calculation.

Discrete Cosine Transform (hereinafter referred to as DCT) and its Inverse Discrete Cosine Transform (hereinafter referred to as IDCT) are each used in the compression or reconstruction process of a digital image. In the process of compressing a digital image, a normal image is subdivided into a plurality of blocks of 8x8 pixels, and then DCT conversion is performed for each block in turn to convert the data into frequency domain data. In the restoration process, the frequency domain data is restored to the image data via IDCT.

Therefore, when two-dimensional DCT / IDCT is executed, first one-dimensional row (or column) conversion is performed, and then another one-dimensional column (or row) is converted. For example, the one-dimensional DCT of any row or column of an 8 × 8 block can be expressed as the following equation.

[Equation 1]

F (k) = 1 / 2-C (k) S (m) cos [(2m + 1) k 16]

k = 0,1, ..... 7

C (k) = ^{1/2 1/2} (when k = 0)

C (k) = 1 (when K = 1,2, ... 7)

The relational expression is composed of a series of multiplications and cumulative numbers, where S (m) is image data of a spatial region, and F (k) is data of the region after conversion. A series of high-speed algorithms can be derived from this relation, and one-dimensional DCT can be executed by 13 multiplications and 29 additions and subtractions, and the processor is as shown in FIG.

In particular, three types of operations are defined in the processor. As shown in Figs. 7 (a) to (d), Instrinsic Multiplication, Butterfly Operation, and Pre-Addition Method are used. added Multiplication). Another combination operation shown in FIG. 7 is called post-subtracted multiplication and is used for the processing processor on the IDCT side. Therefore, it can be inferred that 12 butterfly operations, 5 pre-addition methods, and 8 simple multiplication methods have been executed from the process of the one-dimensional DCT, and these operations are further divided into six operating systems and performed in order. The order is

1st operation step: 4 times of butterfly operation

Second operation step: execution of two transposition addition operations;

Third operation step: execute the butterfly operation again 4 times,

Fourth operation step: execution of three transposition addition method,

Fifth Operation Step: Perform Four More Butterfly Operations,

6th operation step: execution of 8 simple multiplication operations,

In this way, the one-dimensional DCT is completed. If this one-dimensional operation step is reversed, one-dimensional IDCT as shown in Fig. 8 can be obtained. Similarly, this one-dimensional IDCT is performed in the order of six operating systems, but the simple multiplication operation is performed in the first operating system, the butterfly operation is performed in the second, fourth and sixth operating systems, and the third and fifth operations are performed. The operation of post-subtraction multiplication is performed in the operating system of.

The present invention relates to a DCT / IDCT integrated circuit processor designed as the basis of the high-speed calculation method, and according to the unique hardware configuration, for example, 8 × 8 block data can be sequentially calculated in the six operation steps, 1 After completing the DCT / IDCT of the dimension, it is possible to complete the two-dimensional transformation by transposing again one-dimensional DCT / IDCT. Conventional DCT / IDCT processors, on the other hand, use nearly massive hardwired logic to increase processing speeds to achieve tight pipeline operations, resulting in extremely high cost but virtually no ordinary application. The response conversion process can be achieved immediately without requiring close and high speed timing.

Accordingly, the present invention, in view of the shortcomings of the conventional DCT / IDCT processor, the hardware structure is simple, but can be reverse-order operation, and at the same time it can reduce the cost by greatly reducing the occupied space of the direct meeting, and also the general use environment The purpose of the present invention is to provide a DCT / IDCT integrated circuit processor capable of addressing real-time processing and increasing the processing speed, which can be applied to higher bit rates, and a processing method thereof.

In order to achieve the above object, the present invention provides an input sequence for inputting data from the outside, a butterfly calculation means for executing a butterfly operation, a multiplication operation means for performing a simple multiplication association, and the multiplication operation means. Two-dimensional one-dimensional DCT / A by combining auxiliary registers for performing pre-addition multiplication or post-subtraction multiplication, and data registers for writing and reading ports by four pins to access intermediate results of the calculation process. In addition to enabling IDCT operations, each one-dimensional DCT / IDCT operation consists of six operation steps including three steps of butterfly operation, one step of simple multiplication operation, and two steps of multiplication operation. do.

According to the present invention, the two-dimensional one-dimensional DCT / IDCT operation can be executed by each of the above-described calculation configurations, and the parallel operation of the pipeline work method can be performed by the butterfly calculation means and the multiplication operation means, respectively. The volume of the integrated circuit of the arithmetic processor can be greatly reduced, and at the same time, it can meet the needs of general real-time processing. In addition, when the two processors are serialized to each other, the first and second one-dimensional DCT / IDCT operations of the block data can be respectively performed from both pipeline working methods, thereby further improving the processing speed. Suitable for bit rate applications.

1 is an embodiment of an integrated circuit processor according to the present invention.

The integrated circuit processor includes an input means 1, a butterfly calculation means 2, a multiplication operation means 3, a data register 4, an output means 5 and a control means 6. Among them, the input means 1 is composed of a demultiplexer, and selects data Din from the outside according to a DCT operation or an IDCT operation and sends it to the butterfly calculation means 2 or the multiplication operation means 3.

The butterfly calculating means 2 comprises a first premultiplexer 21 and a butterfly calculator 22. The butterfly operator 22 is composed of a pair of adders and subtractors. The butterfly calculating means 2 selects the output data from the input means 1 or the data register 4 by the premultiplexer 21, and performs the butterfly calculation with the butterfly calculator 22, and the result of the calculation is calculated. It writes to the data register 4 or outputs it externally from the output means 5.

A second premultiplexer 31, an auxiliary adder and subtractor 32, a multiplication 33, a coefficient ROM 34, and an output selector 35 of the multiplication operation means 3 are provided. The coefficient ROM 34 stores the coefficient portion of the multiplication operation, where the stored data is used as an operand of the multiplier 33. The multiplication operation means (3) is responsible for the calculation of the simple multiplication method, the pre-addition multiplication method, and the post-subtraction multiplication method. (31) or the protection adder / subtractor 32, and the operation result is rewritten into the data register 4 via the output selector 35. The output of the multiplier 33 is sent to the outside via the output means 5. In addition, when the multiplication operation means 3 performs the simple multiplication operation, input data is given to the multiplier 33 by selection of the premultiplexer 31, and the corresponding address coefficient from the coefficient ROM 34 is By multiplication, the simple multiplication operation is completed. In addition, in the preaddition multiplicative operation, both data auxiliary subtractors 32 output from the data register 4 are added, both are added, and the result is sent to the multiplier 33 so that the corresponding address from the coefficient ROM 34 can be obtained. The multiplication with the coefficients completes the pre-add multiplication operation. In addition, in the case of post-subtraction multiplication, similarly, both data output from the data register 4 are sent to the second premultiplexer 31 and the other to the auxiliary adder 32 to the premultiplexer 31, respectively. The sent data is input to the multiplier 33, and a simple multiplication operation is performed, and the result of the operation is sent to the auxiliary adder and subtractor 32, and the difference between them is subtracted by another subtracted previously input data. Results in:

The data register 4 is constituted by four port register means, and stores intermediate result data of the calculation process by RAM or the like. The four-port structure can be divided into two pairs of write / read (WP1-RP1 and WP2-RP2), respectively, which are data access paths of the butterfly calculating means 2 and the multiplication operation means 3, respectively.

The output means 5 is provided with a multiplexer, and selects the output from the butterfly operator 22 or the multiplier 33 according to application of IDCT operation or DCT operation to output data to the outside. In addition, the control means 6 is used to generate a control sequence, and controls the operation procedure of each said means.

2 and 3 show the order in which the present processor performs a DCT / IDCT operation based on the above configuration. In the figure, two front and rear one-dimensional transformed first 1-D DCT / IDCT and second 1-D DCT / IDCT are executed for the block N, and six operation steps in each one-dimensional transform are performed. The butterfly operation and the multiplication operation in s are performed in order, and the butterfly operation means 2 and the multiplication operation means 3 each perform parallel processing in a pipeline working weave. In the DCT shown in FIG. 2, the butterfly operation is performed in the first, third, and fifth steps, the pre-addition multiplication operation is performed in the second and fourth steps, and the simple multiplication operation is performed in the sixth step. All. In the IDCT shown in FIG. 3, the simple multiplication operation is performed in the first step, the post-subtraction multiplication operation in the third and fifth steps, and the butter in the second, fourth and sixth steps. The fly operation is performed. Further, data is input from Din at the same time as the first step operation of the first one-dimensional transform (i.e., the first 1-D DCT / IDCT), and the second one-dimensional transform (i.e., 2 1-D DCT / IDCT). When the sixth step is executed, the result is output from the outside (Dout).

The operation data of each step removes inputs and outputs from the outside, and all data registers 4 are source or destination (destination). The access method of the data register 4 requires two one-dimensional transforms in the same block to be reversed. For example, if the first dimensional transform is accessed in the row order, the second method is used. The one-dimensional transform of is necessarily accessed in column order. And vice versa. However, the order of access between the adjacent two blocks, that is, the second one-dimensional transform of the previous block and the first one-dimensional transform of the next block is unchanged. In addition, the butterfly multiplication operation means 2 and the multiplication operation means 3 can perform data access to the data register 4 simultaneously from the individual write / read ports of the data 4, so that both calculation means ( Using 2) and (3), parallel processing can be performed by the pipeline work method, and the same kind of operation steps are executed in sequence in the same operation means.

The following description will be given with examples. (1) When DCT is executed, for example, 8 × 8 pixel blocks are input from Din in the order of rows (or columns) as 64 pixel data, and input means ( After selection 1), it is sent to the butterfly multiplication operation means 2 to perform the calculation of the first step. This is a butterfly operation, the result of which is written to the data register 4 from the write port WP1, and then to the data register 4 from the read port RP1, which is then read from the read port RP1 and multiplied. It is sent to the calculating means 3, and calculation of a 2nd step progresses. This is the transpositional multiplication operation. Subsequently, the result of the preaddition multiplication operation is rewritten from another write port WP2 to the data register 4 and waits for the completion of the operation of the first step, and then from the other exit port RP2. The result of the two step operations is read and sent to the butterfly multiplication method 2 to perform the third step operation. The result of the calculation is written back to the data register 4 by the write port WP1. In the same manner, the operation of the fourth step is performed by the multiplication operation means 3 after the operation of the second step, and the operation of the fifth step is performed by the butterfly multiplication operation means 2 after the operation of the third step. All. In the sixth step operation, after the fourth step operation, the simple multiplication operation is performed by the multiplication operation means 3, and these results are rewritten together in the data register 4 together. When the sixth step operation is completed, the first one-dimensional DCT is completed.

Then, the order is reversed, that is, the data is read from the data register 4 by RP1 in the order of the columns (or rows) and sent to the butterfly multiplication operation means 2, the first step of the second one-dimensional DCT. Start the operation. The operation method of each step thereafter is the same as that of the first one-dimensional DCT, but the difference is that the operation result of the sixth step at the end is not rewritten in the data register 4, but the multiplier of the multiplication operation means 3 directly ( 33 is outputted to the outside Dout via the output means 5. This final output is the DCT computed frequency domain data for the block pixel.

(2) In the case of executing IDCT, 64 frequency domain data are input from the Din to the input means 1 in the order of rows (or columns), and are sent to the multiplication operation means 3 according to the selection, and the first step. The operation is performed. This is a simple multiplication operation, the result of which is written to the data register 4 by the write port WP2, which is then read from the read port RP1 and sent to the butterfly multiplication operation means 2, whereby the second Step operation is performed. It belongs to the butterfly operation, and the result is written back to the data register 4 by the other write port WP1. The third system is a post subtraction multiplication operation, which reads the result of the second step operation by the read port RP2 and sends it to the multiplication operation means 3, which is subsequently executed after the first step operation. The result of the calculation is written back to the data register 4 by the WP2. In the same sense, the calculation of the fourth step is performed by the butterfly multiplication operation means 2 after the calculation of the second step, and the calculation of the fifth step is performed by the multiplication operation means 3 after the calculation of the third step. Is executed. The operation of the sixth step is executed by the butterfly multiplication operation means 2 after the fourth step operation, and the result of the operation is rewritten in the data register 4, and thus the sixth step operation is completed. One-dimensional IDCT of 1 is completed.

Thus, in RP2, data is read from the data register 4 in the order of columns (or rows) and sent to the multiplication operation means 3, whereby the operation of the first step in the second one-dimensional IDCT is started. do. The operation of each subsequent step is the same as that of the first one-dimensional IDCT, but the other is that the final six-step operation result is not rewritten into the data register 4, but is outputted through the output means 5 to the outside (Dout). Is in the output point. This final output is pixel data after IDCT reconstruction.

Figure 4 shows another embodiment of a processor according to the present invention, which is a series of both basic modules shown in Figure 1, by processing two one-dimensional DCT / IDCT of block data by a pipeline operation, In other words, the two modules each execute one step six operations of one-dimensional transformation in order.

The processor is mainly provided with a first one-dimensional processing means 7, a second one-dimensional processing means 8 and a control means 9. The first one-dimensional processing means 7 is the first butterfly calculating means 72 and the premultiplexer 731 having the input means 71, the premultiplexer 721, and the butterfly operator 722, the auxiliary addition and subtraction. A first multiplication operation means (73) having a calculator (732), a multiplier (733), a coefficient ROM (734), and an output selector (735), and a first for performing block data input or first one-dimensional conversion. Data register 74 is provided. The first data register 74 also serves as a transpose memory and serves as a source of input data of the second one-dimensional processing means 8.

On the other hand, the second one-dimensional processing means 8 includes the second butterfly computing means 81 having a premultiplexer 811 and a butterfly operator 812, a premultiplexer 821, and an auxiliary adder and subtractor 822. Second multiplication operation means 82 having a multiplier 823 and an output selector 824, a second data register 83, and an output means 84. The operation input terminal of the multiplier 823 of the second multiplication operation means 82 is connected to the first multiplication operation means 73, and can be shared with the coefficient ROM 734 of the first multiplication operation means 73. It is supposed to be. The second one-dimensional processing means 8 performs a second one-dimensional transform of the block data and outputs the final result. The control means 9 are used to control the execution process of these first and second one-dimensional processing means 7, 8.

According to the above arrangement, the execution order of the DCT / IDCT operation is as shown in FIG. 5, in which the DCT / IDCT operation of the block data is executed by the pipeline work of the one-dimensional processing means 7 and 8, As the input data of the block N enters the first one-dimensional processing means 7 from Din and the first one-dimensional conversion of the previous block N-1 is performed, the first data register 74 results. Is sent to the second one-dimensional processing means 8 from the read port RP1A (when executing the CTCT) or the RP2A (when executing the IDCT), and the one-dimensional processing means 7 and 8 are each one-time. The six step operations of the conversion are executed in order, and the last result of the previous block N-1 is sent from the output end of the output means 84 to the outside Dout. When the first one-dimensional transformed result of the block N is stored in the first data register 74, the first data register 74 always performs data access in a row or row compatibility order on the continuous block side. Do it. Such a structure can improve the processing speed and can be applied to a high byte rate application environment.

There are three basic ideas in this form, one for cyclic execution, the other for parallel processing, and one for speedup of processing speed.

Among them, the circuit execution means to accomplish a task by performing the circuit execution several times using the same hardware, that is, to convert the space to time to obtain space, and to mean the actual work time by reducing the hardware to reduce the cost.

In addition, parallel processing takes time by switching to space as opposed to circular execution, that is, parallel processing is performed using two independent means to achieve real-time speed under the configuration of the circular execution, so as not to delay the working time so much. I mean. Incidentally, the configuration of parallel processing in the above embodiment corresponds to this, and corresponds to the serial configuration of double speed improvement of the following processing speed.

In addition, the improvement of the processing speed is due to the fact that when processing at a higher bit rate under the configuration of the above-mentioned execution and parallel processing, it is necessary to obtain more time by changing the space in order to realize the processing in real time on the processing speed. Belongs to.

The arithmetic method according to the present invention includes the above three ideas, and thus includes two arithmetic operations in the same order, regardless of DCT or IDCT, and each arithmetic operation includes six arithmetic steps, respectively. The six operation steps can be classified into two types of operations (butterfly operation and multiplication operation), and these operations are performed alternately. In other words, this feature forms a configuration and an implementation method according to the present invention.

For example, in Fig. 1, both characteristics of the traversal execution and the parallel processing are used. When DCT / IDCT is performed in this configuration, 12 steps (2 times of 10D DCT / IDCT) need to be executed. In addition, since the parallel processing is divided into six steps by two independent calculation means (butterfly calculation means and multiplication operation means), 12 steps are required to process one block as shown in FIGS. Only six steps are sufficient, not a time, and both operations are almost completely operational at any point in time.

In addition, in order of execution, each step must process 64 data (in the order of columns or rows, each column or row contains 8 data or 8 columns or 8 rows each). A plurality of data must be processed in the step of, and after processing a plurality of data in the first step (although the plurality of data referred to here are slightly different in the DCT and IDCT), the second step is the result of the first step. The last step in the previous block (i.e., the sixth step in the second 1-D) is determined depending on how long it is, and the first block is processed from the beginning. The largest number of data is 8 (1 column or 1 row), DCT and IDCT. In addition, since the third step belongs to the same kind of operation as the first step, the first step is connected after the 64 data have been completely processed. It can be guaranteed that the processing is completed, and at least eight or more (one column or one row) of data can be processed in the third step and there is no need to wait.

The same applies to the fourth, fifth and sixth steps, and the operation method is one data followed by one data, one step followed by one step, and then one after one (i.e., the first one). -D, the second 1-D, the first 1-D, ...) is called a pipeline operation. This pipeline operation stops slightly between one block of both ordered operations (ie between the first 1-D and the second 1-D), but this does not require the data register means to change the access order between these thresholds. This is because the first step of the second 1-D always starts after the sixth step is completely completed, and continues directly after the fifth step of the first 1-D. This is because the data required by the first step of the second 1-D is not yet fully prepared at this time. Therefore, there is no way to start even if it intends to start. When the first system of the second 1-D is started, the execution order and time are the same as those of the first 1-D.

In addition, pipeline work between two adjacent blocks is not interrupted. Therefore, since the data of the next block comes in from Din, the first step does not need to be waited. After the step 5 is executed, the previous block data is also completed and sent to Dout in the sixth step of the second 1-D, so that the access order of the data register means does not need to be compatible with the columns and rows.

As described above, according to the present invention, since the configuration is simplified, the space occupied by the integrated circuit can be greatly reduced. As a result, the cost is reduced and the processing speed is improved. Therefore, the present invention can be applied to a high bit rate application environment in accordance with the requirements of real-time processing. .

Claims (8)

When performing discrete cosine transform (DCT), the input data of a series of pixel data blocks is processed by a 6-step DCT fast computation method to generate a series of transform data. The first, third and fifth steps including the ply operation, the second and fourth steps including the plurality of preliminary multiplication operations, and the sixth step including a plurality of simple multiplication operations. An integrated circuit processor for discrete cosine conversion, comprising: (a) extracting the input data from an input means (1), and (b) controlling the input means (1) to butter the input data. Sending to the fly calculating means 2 and activating the butterfly calculating means to perform DCT high-speed calculation of the first step; and (c) output data of the first stem of the butterfly calculating means 2; To the data register (4) (D) controlling the data register to send the output data of the first step to the multiplication operation means 3, and starting the multiplication operation means to execute the DCT fast operation of the second step. (E) controlling the data register to store output data of the second step of the multiplication operation means 3, and (f) controlling the data register to output the first and second steps The data is provided to the butterfly calculating means 2, and the butterfly calculating means executes the DCT high speed calculation in the third step after completion of the first step of the DCT fast calculation. (G) controlling the data register to store output data of the third step of the butterfly calculating means; and (h) controlling the data register to store the output data of the third step. Providing the multiplication operation means (3), starting the multiplication operation means to execute DCT high-speed operation of the step of the gen 4; (i) controlling the data register to control the multiplication operation means (3). Storing output data of the fourth step; and (j) controlling the data register to provide the output data of the third and fourth steps to the butterfly calculating means 2, and to the butterfly calculating means. Executing the butterfly calculating means by executing the DCT high speed operation of the third step and executing the DCT high speed operation of the fifth step; and (k) controlling the data register to control the butterfly calculating means (2). (1) controlling the data register to provide the fifth output data to the multiplication operation means (3), starting the multiplication operation means, and increasing the DCT of the sixth step. Performing the operation; and (m) taking out the output data of the Zen 6 step of the multiplication operation means 3 from the output means 5, and at the same time, the steps of (a) to (m). An integrated circuit processor for discrete cosine transform that performs data processing with 2. The method according to claim 1, wherein the data register 4 is controlled to store the output data of the six steps between the steps (l) and (m), and the data register is controlled to output the six steps. Providing data to the butterfly calculating means (2), and performing the DCT high-speed operation of the first step by the butterfly calculating means; and duplicating the data in the order of steps (c) to (l). Integrated circuit processor further comprising the step. When performing discrete cosine inverse transform (IDCT), a series of pixel data blocks are processed by a six-step IDCT fast operation method to generate a series of transform data, and this IDCT fast operation is performed by a plurality of simple multiplication methods. A first step comprising operations, second, fourth and sixth steps each comprising a plurality of butterfly operations, and third and fifth steps each comprising a plurality of post subtraction multiplication operations. An integrated circuit processor for inverse cosine inverse transformation, comprising: (a) extracting the input data from an input means (1), and (b) controlling the input means to multiply the input data by a multiplication operation means ( 3) and simultaneously executing the multiplication operation means to execute the IDCT fast operation of the first step; and (c) processing data of the first step of the multiplication operation means 3; Saving to) And (d) controlling the data register 4 to send the output data of the first system to the butterfly calculating means 2, and simultaneously starting the butterfly calculating means to perform IDCT high-speed operation of the second step. (E) controlling the data register to store output data of the second step of the butterfly calculating means 2, and (f) controlling the data register to perform the second step. Outputting the data to the multiplication operation means (3), starting the multiplication operation means to execute IDCT high-speed operation of the third step; (g) controlling the data register to control the multiplication operation means ( Storing the output data of the third step of 3); and (h) controlling the data register to provide the second and third output data to the butterfly calculating means 2, wherein the butterfly operation is performed. Number After the step executes the IDCT high speed operation of the second step, the butterfly calculating means executes the IDCT high speed operation of the fourth step; (i) controlling the data register to control the data register; Storing output data of the fourth step of 2), (j) controlling the data register to provide the output data of the fourth step to the multiplication operation means 3, and starting the multiplication operation means. Executing the IDCT fast computation of the fifth step; (k) controlling the data register to store output data of the fifth step of the multiplication operation means 3; and (l) storing the data register. Control to provide the fourth and fifth output data to the butterfly calculating means (2), and after the butterfly calculating means performs the IDCT high-speed operation of the fourth step, by the butterfly calculating means remind Performing a six-step IDCT high-speed operation, (m) extracting the output data of the sixth step of the butterfly calculating means 2 from the output means 5, and (a An integrated circuit processor for discrete cosine transform, performed in the order of (m) to (m). 4. The method according to claim 3, wherein the step of controlling the data register (4) to store the output data of the sixth step between the steps (l) and (m), and the control of the data register (4). Storing the output data of the sixth step, and providing the output data of the sixth step for controlling the data register 4 to the multiplication operation means 3, and by the multiplication operation means, And executing the IDCT high-speed operation and duplicating the steps in the order of (c) to (l). Direct for discrete cosine transform and inverse transform having input means (1), butterfly calculation means (2), multiplication operation means (3), data registers (4), output means (5) and control means (9). In the circuit processor, the input means (1) receives input data from the outside, and the butterfly calculating means (2) selects and outputs data from the input means (1) and the data register (4). A premultiplexer 721 of one, and a butterfly calculator 722 that receives output data from the first premultiplexer and performs a butterfly operation of addition and subtraction, wherein the multiplication operation 3 is the input. A second premultiplexer 731 for selectively outputting data from the means and the data registers; and an auxiliary adder for concatenating the data register 4 to perform the addition portion and the post subtraction subtraction portion of the pre-add operation; (732) A multiplier 733 connected to the second premultiplexer and the auxiliary adder and executing a multiplicative portion of the simple multiplication, preaddition, and post subtraction multiplication, and connected to the multiplier and accessed as a coefficient part of the multiplication; An output selector connected to the coefficient ROM 734 for supplying another operational input of the multiplier and the auxiliary subtractor and the multiplier, the output of the auxiliary adder and multiplier being sent to the data register 4; 735, wherein the data register 4 is concatenated with the butterfly calculating means 20 and the multiplication operation means 3, to access intermediate results of the calculation process, and the output means 5 It is connected to the butterfly calculating means 2 and the multiplication operation means 3, and selects the output data of the butterfly calculating means and the multiplication operation means and sends it to the outside, and An integrated circuit processor for discrete cosine transform and inverse transform, configured to control the operation sequence of the respective means of the control means according to the control sequence. 6. The data input device according to claim 5, wherein said input means (1) comprises a demultiplexer and is configured to select data input by DCT / IDCT operation and send it to said butterfly calculation means / multiplication operation means. Integrated circuit processor. A first one-dimensional processing means (7), a second one-dimensional processing means (8) and a control means (9), wherein the first one-dimensional processing means (7) includes an input means (71) and butter The fly calculating means 72, the multiplication operation means 73, and the first data register 74 are provided to receive input data from the outside of the input means 71, and the butterfly calculating means 72 A first premultiplexer 721 for selecting data output from the input means and the first data register, and is formed by a pair of adders and subtractors, and receives and adds and subtracts the data from the first premultiplexer. A second premultiplexer 731 having a butterfly subtractor 722 for performing a butterfly operation, wherein the multiplication operation means 73 selects data output from the input means and the first data register; Concatenated to the first data register 74 Auxiliary adder and subtractor 732 which executes the addition part of the preaddition multiplication operation and the subtraction part of the post subtraction multiplication operation, and the second premultiplexer and the auxiliary adder subtractor are connected to each other in the simple multiplication method, the preaddition multiplication method, and the post subtraction method. A multiplier 733 for executing the multiplication part, a coefficient ROM concatenated to the multiplier and accessed as a coefficient part of the multiplicative operation to give another operation input of the multiplier, and connected to the auxiliary adder and multiplier And an output selector 735 for selectively outputting output data of an adder / subtracter and a multiplier to the first data register 74, wherein the first data register 74 is the butterfly calculating means 72 and the multiplication method. It is connected to the calculation means 73 and is configured to access intermediate results in the calculation process. The second one-dimensional processing means 8 has a butterfly calculation means 81. A multiplication operation means 82, a second data register 83 and an output means 84, wherein the butterfly calculation means 81 is provided with the first and second data registers 74 and 83; A first premultiplexer 811 that selects output data of the first premultiplexer 811 and a pair of adders and subtractors that receive data from the first premultiplexer and perform butterfly operations for addition and subtraction A second premultiplexer 821, wherein the multiplication operation means 82 selects data output from the first and second data registers 74 and 83, and the second premultiplexer 821; A concatenated subtractor 822 concatenated to the data register 88 to execute the addition part of the whole addition multiplication operation and the subtraction part of the post subtraction multiplication operation, and the second pre-multiplexer and the auxiliary adder subtractor are connected in a simple manner. Multiplication, transposition addition and post sense A multiplier 823 which is connected to the coefficient ROM of the first one-dimensional processing means 7 and the auxiliary adder and the multiplier connected to the multiplier of the first multidimensional processing unit 7 is executed, and the output of this auxiliary adder and multiplier is output. An output selector 824 that selects data and sends it to the second data register 83, wherein the second data register 83 is provided to the butterfly calculating means 81 and the multiplication operation means 82; Are connected to access intermediate results in the calculation process, and the output means 84 is connected to the butterfly calculation means 81 and the multiplication operation means 82 to output the outputs of the butterfly calculation means and the multiplication operation means. Selected as output data to the outside, the control means 9 is configured to control the execution order of the first one-dimensional processing means 7 and the second one-dimensional processing means 8 in accordance with the control sequence This is characterized by Ever cosine integrated circuit processor for the transform and inverse transform. 8. The butterfly operation of the second one-dimensional processing means (8) according to claim 7, wherein the input means (71) comprises a demultiplexer and selects data input by a DCT / IDCT operation. And a first multiplication operation means.