KR960026621A - Method for manufacturing inter-element separator of highly integrated semiconductor device - Google Patents

Method for manufacturing inter-element separator of highly integrated semiconductor device Download PDF

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Publication number
KR960026621A
KR960026621A KR1019940040769A KR19940040769A KR960026621A KR 960026621 A KR960026621 A KR 960026621A KR 1019940040769 A KR1019940040769 A KR 1019940040769A KR 19940040769 A KR19940040769 A KR 19940040769A KR 960026621 A KR960026621 A KR 960026621A
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KR
South Korea
Prior art keywords
oxide film
field oxide
semiconductor device
highly integrated
integrated semiconductor
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KR1019940040769A
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Korean (ko)
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KR0140658B1 (en
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황준
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김주용
현대전자산업 주식회사
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Priority to KR1019940040769A priority Critical patent/KR0140658B1/en
Publication of KR960026621A publication Critical patent/KR960026621A/en
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Publication of KR0140658B1 publication Critical patent/KR0140658B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

고집적 반도체 소자 제조 방법.Highly integrated semiconductor device manufacturing method.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래의 로코스 방식에 따른 필드 산화막 형성시 필드 산화막의 버즈 비크(Bird's Beak)가 너무 크게 성장되어 엑티브 영역을 축소시키게 되는 문제점을 해소하고자 함.When the field oxide film is formed according to the conventional LOCOS method, it is intended to solve a problem in which the bud's beak of the field oxide film is grown too large to reduce the active area.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

이중으로 필드 산화막을 성장시킨 다음 2차로 성장된 필드 산화막의 식각시 1차 필드 산화막의 버즈 비크(Bird's Beak)부분을 함께 식각하므로써 보다 넓은 영역의 엑티브 영역의 확보가 가능하도록 함.When the field oxide layer is grown twice, the second field grown layer is etched together to etch the bird's beak portion of the primary field oxide layer to secure a wider active region.

4. 발명의 중요한 용도4. Important uses of the invention

고집적 반도체 소자, 특히 MOS 트렌지스터 제조에 이용됨.Used in the manufacture of highly integrated semiconductor devices, especially MOS transistors.

Description

고집적 반도체 소자의 소자간 분리막 제조 방법Method for manufacturing inter-element separator of highly integrated semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도는 내지 제 1E도는 본 발명의 반도체 소자의 소자간 분리막 형성 방법에 따른 제조 공정도, 제2A도및 제 2B도는 1D도의 필드 산화막의 버즈 비크 부분의 설명을 위한 부분 상세도.1A to 1E are manufacturing process diagrams according to the method for forming an inter-element separator of a semiconductor device of the present invention, and FIGS. 2A and 2B are partial detailed views for explaining the buzz beak portion of the field oxide film of FIG. 1D.

Claims (4)

반도체 소자의 분리막을 제조하는 방법에 있어서, 반도체 기판상에 산화막과 질화막을 차례로 형성하는단계와, 상기 질화막위에 포토레지스트를 도포한 후 포토마스크를 이용한 노광 공정을 통해 소자간 분리막이 형성될 부위가 노출되도록 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 페턴을 식각 마스크로 이용하여 상기 질화막의노출 부위를 식각하고 잔류 포토레지스트를 제거하는 단계와, 채널 스톱 영역을 형성하기 위한 이온 주입을 실시하는 단계와, 열적 산화막 성장 공정을 통해 소정의 두께를 가진 제1필드 산화막을 형성하고, 상기 질화막을 제거하는 단계와,열적 산화막 성장 공정을 통해 소정의 두께를 가진 제2필드 산화막을 형성하는 단계 및, 상기 제2필드 산화막 및 제1필드산화막의 일부를 식각하는 단계를 포함해서 이루어진 반도체 소자의 소자간 분리막 제조 방법.In the method of manufacturing a separator of a semiconductor device, a portion in which an interlayer separator is to be formed by sequentially forming an oxide film and a nitride film on a semiconductor substrate, applying a photoresist on the nitride film, and then using an exposure process using a photomask. Forming a photoresist pattern to be exposed, etching the exposed portion of the nitride film and removing residual photoresist using the photoresist pattern as an etch mask, and performing ion implantation to form a channel stop region Forming a first field oxide film having a predetermined thickness through a thermal oxide film growth process and removing the nitride film; forming a second field oxide film having a predetermined thickness through a thermal oxide film growth process; And etching a portion of the second field oxide film and the first field oxide film. A method for producing an inter-element separator of a semiconductor device. 제1항에 있어서, 상기 필드 산화막의 식각기, 제1필드 산화막의 버즈 비크 부분을 함께 식각하는 것을 특징으로 하는 반도체 소자의 소자간 분리막 제조 방법.2. The method of claim 1, wherein the etcher of the field oxide film and the buzz beak portion of the first field oxide film are etched together. 제1항에 있어서, 상기 제1필드 산화막의 성장 두께는 약 5000Å 내지 10000Å인 것을 특징으로 하는 반도체 소자의 소자간 분리막 제조 방법.The method of claim 1, wherein the growth thickness of the first field oxide film is about 5000 kPa to about 10000 kPa. 제1항 또는 제3항에 있어서, 상기 제2필드 산화막의 성장 두께는 약 1000Å 내지 2000Å인 것을 특징으로하는 반도체 소자의 소자간 분리막 제조 방법.The method of claim 1 or 3, wherein the growth thickness of the second field oxide film is about 1000 GPa to 2000 GPa. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040769A 1994-12-30 1994-12-30 Manufacture of element isolation for semiconductor integrated circuit device KR0140658B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940040769A KR0140658B1 (en) 1994-12-30 1994-12-30 Manufacture of element isolation for semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940040769A KR0140658B1 (en) 1994-12-30 1994-12-30 Manufacture of element isolation for semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
KR960026621A true KR960026621A (en) 1996-07-22
KR0140658B1 KR0140658B1 (en) 1998-07-15

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100419876B1 (en) * 1996-10-30 2004-05-10 주식회사 하이닉스반도체 Method for forming isolation layer of semiconductor device

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