KR100239403B1 - Method for forming isolation film - Google Patents
Method for forming isolation film Download PDFInfo
- Publication number
- KR100239403B1 KR100239403B1 KR1019960061256A KR19960061256A KR100239403B1 KR 100239403 B1 KR100239403 B1 KR 100239403B1 KR 1019960061256 A KR1019960061256 A KR 1019960061256A KR 19960061256 A KR19960061256 A KR 19960061256A KR 100239403 B1 KR100239403 B1 KR 100239403B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- forming
- insulating film
- isolation region
- insulating
- Prior art date
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 4
- 239000004065 semiconductor Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
본 발명은 격리막 형성 방법에 관한 것으로, 특히 활성 영역을 크게 하는 격리막 형성 방법에 관한 것이다.The present invention relates to a method for forming a separator, and more particularly, to a method for forming a separator that enlarges an active region.
이를 위한 본 발명의 격리막 형성 방법은 기판상에 제 1, 제 2 절연막을 형성하고, 격리 영역의 제 2 절연막을 선택적으로 제거하는 단계, 상기 제 2 절연막을 마스크로 이용하여 노출된 제 1 절연막을 오버 에치하는 단계, 전면에 제 3 절연막을 형성하고, 상기 격리 영역의 제 3 절연막을 선택적으로 제거하는 단계와 상기 격리 영역에 제 4 절연막을 형성하고, 열처리하여 필드 산화막을 형성한 후, 상기 제 1, 제 2, 제 3 절연막을 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.According to the present invention, a method of forming an isolation layer may include forming first and second insulation layers on a substrate, selectively removing the second insulation layer in the isolation region, and exposing the exposed first insulation layer using the second insulation layer as a mask. Overetching, forming a third insulating film on the entire surface, selectively removing the third insulating film in the isolation region, forming a fourth insulating film in the isolation region, and performing a heat treatment to form a field oxide film. And removing the first, second, and third insulating films.
Description
본 발명은 격리막 형성 방법에 관한 것으로, 특히 활성 영역을 크게하는 격리막 형성 방법에 관한 것이다.The present invention relates to a method for forming a separator, and more particularly, to a method for forming a separator that enlarges an active region.
이하 첨부된 도면을 참조하여 종래의 격리막 형성 방법을 설명하면 다음과 같다.Hereinafter, a method of forming a conventional separator will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래 기술에 따른 격리막 형성 방법을 나타낸 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a separator according to the prior art.
도 1a에서와 같이, 격리 영역이 정의된 반도체 기판(11)상에 제 1 산화막(12), 질화막(13)과 감광막(14)을 차례로 형성한 다음, 상기 감광막(14)을 상기 격리 영역 상측에만 제거되도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 감광막(14)을 마스크로 이용하여 상기 질화막(13)과 제 1 산화막을 선택적으로 식각하고 상기 감광막(14)을 제거한다.As shown in FIG. 1A, a first oxide film 12, a nitride film 13, and a photosensitive film 14 are sequentially formed on the semiconductor substrate 11 on which the isolation region is defined, and then the photosensitive film 14 is formed above the isolation region. After selectively exposing and developing to be removed only, the nitride film 13 and the first oxide film are selectively etched using the selectively exposed and developed photosensitive film 14 as a mask, and the photosensitive film 14 is removed.
도 1b에서와 같이, 상기 질화막(13)을 마스크로 이용하여 전면에 열을 가하므로 상기 격리 영역의 반도체 기판(11) 표면에 필드 산화막(15)을 성장시킨다.As shown in FIG. 1B, the field oxide film 15 is grown on the surface of the semiconductor substrate 11 in the isolation region because heat is applied to the entire surface using the nitride film 13 as a mask.
도 1c에서와 같이, 상기 반도체 기판(11)상에 형성된 제 1 산화막(12)과 질화막(13)을 제거한다.As shown in FIG. 1C, the first oxide film 12 and the nitride film 13 formed on the semiconductor substrate 11 are removed.
종래의 격리막 형성 방법은 필드 산화막 성장시 버즈빅(Bird's Beak)이 커져 활성 영역이 작아지는 문제점이 있었다.The conventional isolation layer formation method has a problem in that an active region is reduced due to an increase in Bird's Beak when growing a field oxide layer.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 기판상의 활성 영역과 격리 영역 경계부위에 질화막을 형성하여 버즈빅을 줄임으로써 활성 영역을 크게하는 격리막 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for forming an isolation layer which increases the active region by reducing a buzz big by forming a nitride film at the boundary between the active region and the isolation region on the substrate.
제1a도 내지 제1c도는 종래 기술에 따른 격리막 형성 방법을 나타낸 공정 단면도.1A to 1C are cross-sectional views illustrating a method of forming a separator according to the prior art.
제2a도 내지 제2f도는 본 발명의 실시예에 따른 격리막 형성 방법을 나타낸 공정 단면도.2A to 2F are cross-sectional views illustrating a method of forming a separator according to an embodiment of the present invention.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
31 : 반도체 기판 32 : 제 1 산화막31 semiconductor substrate 32 first oxide film
33 : 제 1 질화막 34 : 제 1 감광막33: first nitride film 34: first photosensitive film
35 : 제 2 질화막 36 : 제 2 감광막35 second nitride film 36 second photosensitive film
37 : 필드 산화막37: field oxide film
본 발명의 격리막 형성 방법은 기판상에 제 1, 제 2 절연막을 형성하고, 격리 영역의 제 2 절연막을 선택적으로 제거하는 단계, 상기 제 2 절연막을 마스크로 이용하여 노출된 제 1 절연막을 오버 에치하는 단계, 전면에 제 3 절연막을 형성하고, 상기 격리 영역의 제 3 절연막을 선택적으로 제거하는 단계와 상기 격리 영역에 제 4 절연막을 형성하고, 열처리하여 필드 산화막을 형성한 후, 상기 제 1, 제 2, 제 3 절연막을 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.According to the method for forming an isolation film of the present invention, forming a first and a second insulating film on a substrate, selectively removing the second insulating film in the isolation region, and overlying the exposed first insulating film using the second insulating film as a mask. Placing a third insulating film on the entire surface, selectively removing the third insulating film in the isolation region, forming a fourth insulating film in the isolation region, and performing a heat treatment to form a field oxide film. And removing the second and third insulating films.
상기와 같은 본 발명에 따른 격리막 형성 방법의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the separator according to the present invention as follows.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 격리막 형성 방법을 나타낸 공정 단면도이다.2A to 2F are cross-sectional views illustrating a method of forming a separator according to an embodiment of the present invention.
도 2a에서와 같이, 격리 영역이 정의된 반도체 기판(31)상에 제 1 산화막(32), 제 1 질화막(33)과 제 1 감광막(34)을 차례로 형성한 다음, 상기 제 1 감광막(34)을 상기 격리 영역 상측에만 제거되도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 1 감광막(34)을 상기 격리 영역 상측에만 제거되도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 1 감광막(34)을 마스크로 이용하여 상기 제 1 질화막(33)을 선택적으로 식각하고 상기 제 1 감광막(34)을 제거한다.As shown in FIG. 2A, a first oxide film 32, a first nitride film 33, and a first photosensitive film 34 are sequentially formed on the semiconductor substrate 31 on which the isolation region is defined, and then the first photosensitive film 34 is formed. ) Is selectively exposed and developed so as to be removed only above the isolation region, and then selectively exposed and developed so that the selectively exposed and developed first photosensitive film 34 is removed only above the isolation region, and then selectively exposed. And using the developed first photosensitive film 34 as a mask, selectively etching the first nitride film 33 and removing the first photosensitive film 34.
여기서 상기 제 1 산화막(32)은 상기 제 1 질화막(33)에 의해 유발되는 상기 반도체 기판(31)의 스트레스를 줄이기 위해 즉 완충 역할을 한다.In this case, the first oxide film 32 serves as a buffer to reduce the stress of the semiconductor substrate 31 caused by the first nitride film 33.
도 2b에서와 같이, 상기 제 1 질화막(33)을 마스크로 이용하여 상기 제 1 산화막(32)을 선택적으로 습식 식각한다.As shown in FIG. 2B, the first oxide layer 32 is selectively wet etched using the first nitride layer 33 as a mask.
도 2c에서와 같이, 상기 습식 식각된 제 1 산화막(32)을 포함한 전면에 제 2 질화막(35)을 형성한다.As shown in FIG. 2C, a second nitride film 35 is formed on the entire surface including the wet etched first oxide film 32.
도 2d에서와 같이, 상기 제 2 질화막(35)상에 제 2 감광막(36)을 도포하고 상기 격리 영역 상측에만 제거되도록 선택적으로 노광 및 현상한 다음, 상기 선택적으로 노광 및 현상된 제 2 감광막(36)을 마스크로 이용하여 상기 제 2 질화막(35)을 선택적으로 식각한 후, 상기 제 2 감광막(36)을 제거한다.As shown in FIG. 2D, a second photosensitive film 36 is applied on the second nitride film 35 and selectively exposed and developed to be removed only above the isolation region, and then the selectively exposed and developed second photosensitive film ( After selectively etching the second nitride film 35 using 36 as a mask, the second photosensitive film 36 is removed.
도 2e에서와 같이, 상기 제 1, 제 2 질화막(33, 35)을 마스크로 이용하여 전면에 열을 가하므로 상기 격리 영역의 반도체 기판(31)표면에 필드 산화막(37)을 성장시킨다. 여기서 상기 제 1, 제 2 질화막(33, 35)이 있는 부분은 산소의 확산이 안되므로 산화막이 성장되지 않는다.As shown in FIG. 2E, heat is applied to the entire surface using the first and second nitride films 33 and 35 as a mask, thereby growing the field oxide film 37 on the surface of the semiconductor substrate 31 in the isolation region. Here, since the oxygen is not diffused in the portion where the first and second nitride films 33 and 35 are located, the oxide film does not grow.
도 2f에서와 같이, 상기 반도체 기판(31)상에 형성된 제 1 산화막(32)과 제 1, 제 2 질화막(33, 35)을 제거한다.As shown in FIG. 2F, the first oxide film 32 and the first and second nitride films 33 and 35 formed on the semiconductor substrate 31 are removed.
본 발명의 격리막 형성 방법은 기판상의 활성 영역과 격리영역 경계 부위에 질화막을 형성하여 버즈빅을 줄임으로써 활성 영역을 크게하는 효과가 있다.The isolation film formation method of the present invention has the effect of increasing the active area by reducing the buzz big by forming a nitride film in the boundary between the active area and the isolation area on the substrate.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960061256A KR100239403B1 (en) | 1996-12-03 | 1996-12-03 | Method for forming isolation film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960061256A KR100239403B1 (en) | 1996-12-03 | 1996-12-03 | Method for forming isolation film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980043409A KR19980043409A (en) | 1998-09-05 |
| KR100239403B1 true KR100239403B1 (en) | 2000-01-15 |
Family
ID=19485532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960061256A KR100239403B1 (en) | 1996-12-03 | 1996-12-03 | Method for forming isolation film |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100239403B1 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629283A (en) * | 1992-07-07 | 1994-02-04 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH06232119A (en) * | 1992-12-10 | 1994-08-19 | Matsushita Electric Ind Co Ltd | Formation of element isolation |
-
1996
- 1996-12-03 KR KR1019960061256A patent/KR100239403B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629283A (en) * | 1992-07-07 | 1994-02-04 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH06232119A (en) * | 1992-12-10 | 1994-08-19 | Matsushita Electric Ind Co Ltd | Formation of element isolation |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980043409A (en) | 1998-09-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100239403B1 (en) | Method for forming isolation film | |
| KR100186514B1 (en) | Isolation method of semiconductor device | |
| KR0176193B1 (en) | Isolation method of semiconductor device | |
| JPH09232304A (en) | Locos isolation method of semiconductor device | |
| KR100198620B1 (en) | Manufacturing method of isolation film using trench | |
| KR0166835B1 (en) | Method for forming isolation on a semiconductor device | |
| KR100249167B1 (en) | Isolating film manufacturing method | |
| KR960014450B1 (en) | Method of isolation of a semiconductor device | |
| KR0168148B1 (en) | Method of forming field oxide film in a semiconductor device | |
| KR100248813B1 (en) | Method for manufacturing field oxidation film | |
| KR100198600B1 (en) | Method of forming planar isolation area for semiconductor device | |
| JP2939538B2 (en) | Method for forming isolation layer of semiconductor device | |
| KR0151607B1 (en) | A field oxide film forming method of a semiconductor device | |
| KR100439107B1 (en) | Method for forming isolation layer of semiconductor device to prevent leakage current | |
| KR100422960B1 (en) | Method for forming isolation layer of semiconductor device | |
| KR100196422B1 (en) | Method for forming an element isolation region in a semiconductor device | |
| KR0180782B1 (en) | Method for isolating semiconductor device | |
| KR100226724B1 (en) | Method of forming a device isolation film of semiconductor device | |
| KR100249183B1 (en) | Isolating film manufacturing method | |
| KR100335776B1 (en) | Method for fabricating field oxide layer of semiconductor device | |
| KR20040002121A (en) | Method for Forming Field Area in Semiconductor Device | |
| KR100221633B1 (en) | Isolation method for a semiconductor device | |
| KR100418300B1 (en) | Method for forming isolation layer of semiconductor device | |
| KR19980067839A (en) | Separator Formation Method | |
| KR950004489A (en) | Isolation Method of Semiconductor Devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20070914 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |