KR960019661A - Device Separator Formation Method - Google Patents

Device Separator Formation Method Download PDF

Info

Publication number
KR960019661A
KR960019661A KR1019940031603A KR19940031603A KR960019661A KR 960019661 A KR960019661 A KR 960019661A KR 1019940031603 A KR1019940031603 A KR 1019940031603A KR 19940031603 A KR19940031603 A KR 19940031603A KR 960019661 A KR960019661 A KR 960019661A
Authority
KR
South Korea
Prior art keywords
layer
dangling bond
semiconductor substrate
nitrogen dangling
forming
Prior art date
Application number
KR1019940031603A
Other languages
Korean (ko)
Other versions
KR0137585B1 (en
Inventor
엄금용
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940031603A priority Critical patent/KR0137585B1/en
Publication of KR960019661A publication Critical patent/KR960019661A/en
Application granted granted Critical
Publication of KR0137585B1 publication Critical patent/KR0137585B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 소자분리막 형성방법에 있어서, 반도체기판(11) 상부에 소정두께의 제1니트로젠 댕글링 본드층(12)을 형성하는 제1단계; 상기 제1니트로젠 댕글링 본드층(12)상에 스트래스 방지층(13), 제1산화방지층(14,15)을 차례로 형성하는 제2단계; 상기 제1산화방지층(14,15), 스트래스 방지층(13), 제1니트로젠 댕글링 본드층(12)을 차례로 패터닝하는 제3단계; 상기 반도체기판(11)을 산화시키는 제4단계를 포함하는 것을 특징으로 하여, 기판 산화시의 부피 팽창을 최소화시켜, 즉 버드빅을 최소화시킴으로써 큰 활성영역을 확보할 수 있는 특유의 효과가 있는 소자분리막 형성방법에 관한 것이다.In the device isolation film forming method, the first step of forming a first nitrogen dangling bond layer 12 of a predetermined thickness on the semiconductor substrate 11; A second step of sequentially forming the anti-stress layer 13 and the first antioxidant layers 14 and 15 on the first nitrogen dangling bond layer 12; A third step of patterning the first antioxidant layers 14 and 15, the anti-stress layer 13, and the first nitrogen dangling bond layer 12 in order; And a fourth step of oxidizing the semiconductor substrate 11 to minimize the volume expansion during the oxidation of the substrate, that is, the device having a unique effect of securing a large active area by minimizing Budvik. It relates to a separator forming method.

Description

소자분리막 형성 방법Device Separator Formation Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2E도는 본 발명의 일실시예에 따른 필드산화막 형성과정을 도시한 공정 단면도.2E is a cross-sectional view illustrating a process of forming a field oxide film according to an embodiment of the present invention.

Claims (10)

소자분리막 형성방법에 있어서, 반도체기판 상부에 소정두께의 제1니트로젠 댕글링 본드층을 형성하는 제1단계; 상기 제1니트로젠 댕글링 본드층 상에 스트래스 방지층, 제1산화방지층을 차례로 형성하는 제2단계; 상기 제1산화방지층, 스트래스 방지층, 제1니트로젠 댕글링 본드층을 차례로 패터닝하는 제3단계; 상기 반도체 기판을 산화시키는 제4단계를 포함하는 것을 특징으로 하는 소자분리막 형성방법.A device isolation film forming method comprising: a first step of forming a first nitrogen dangling bond layer having a predetermined thickness on an upper surface of a semiconductor substrate; A second step of sequentially forming a stress preventing layer and a first antioxidant layer on the first nitrogen dangling bond layer; A third step of sequentially patterning the first antioxidant layer, the anti-stress layer, and the first nitrogen dangling bond layer; And a fourth step of oxidizing the semiconductor substrate. 제1항에 있어서, 상기 제3단계 수행후, 상기 패터닝된 제1산화방지층, 스트래스 방지층, 제1니트로젠 댕글링 본드층 표면에 소정두께의 제2산화방지층을 형성한 후 상기 제4단계를 수행하는 제5단계를 포함하는 것을 특징으로 하는 소자분리막 형성방법.The method of claim 1, wherein after performing the third step, after forming the second antioxidant layer having a predetermined thickness on the surface of the patterned first antioxidant layer, the anti-stress layer, and the first nitrogen dangling bond layer, the fourth step is performed. And a fifth step of performing the device isolation film forming method. 제2항에 있어서, 상기 제5단계는, 상기 패터닝된 제1산화방지층, 스트래스 방지층, 제1니트로젠 댕글링 본드층 표면에 소정두께의 제2산화방지층을 형성한 후, 상기 제2산화방지층 주위의 반도체 기판의 일부두께를 제거해서 계단형태를 형성한 후 상기 제4단계를 수행하는 것을 특징으로 하는 소자분리막 형성방법.3. The method of claim 2, wherein the fifth step comprises forming a second antioxidant layer having a predetermined thickness on the surface of the patterned first antioxidant layer, the anti-stress layer, and the first nitrogen dangling bond layer. Forming a step shape by removing a part of the thickness of the surrounding semiconductor substrate, and then performing the fourth step. 제2항에 있어서, 상기 제2산화방지층은, 100 내지 500Å의 두께로 형성되는 것을 특징으로 하는 소자분리막 형성방법.The method of claim 2, wherein the second antioxidant layer is formed to a thickness of 100 to 500 kPa. 제1항에 있어서, 상기 제3단계 수행후, 상기 패터닝된 제1니트로젠 댕글링 본드층 주위의 반도체 기판의 일부두께를 제거해서 계단형태를 형성한 후 상기 제4단계를 수행하는 제6단계를 포함하는 것을 특징으로 하는 소자분리막 형성방법.The sixth step of claim 1, wherein after the third step is performed, a step shape is formed by removing a portion of the semiconductor substrate around the patterned first nitrogen dangling bond layer to form a step shape. Device isolation film forming method comprising a. 제3항 또는 제5항에 있어서, 상기 반도체기판에 계단형태를 형성한 후, 노출된 반도체기판 표면에 제2니트로젠 댕글링 본드층을 소정 두께 형성하는 것을 특징으로 하는 소자분리막 형성방법.The method of claim 3 or 5, wherein after forming a stepped shape on the semiconductor substrate, a second nitrogen dangling bond layer is formed on the exposed surface of the semiconductor substrate by a predetermined thickness. 제6항에 있어서, 상기 제2니트로젠 댕글링 본드층은, 15 내지 30Å 두께로 형성되는 것을 특징으로 하는 소자분리막 형성방법.The method of claim 6, wherein the second nitrogen dangling bond layer is formed to a thickness of 15 to 30 μm. 제1항에 있어서, 상기 산화방지층은, 나이트라이드층으로 구성되는 것을 특징으로 하는 소자분리막 형성방법.The method of claim 1, wherein the anti-oxidation layer is formed of a nitride layer. 제1항에 있어서, 상기 산화방지층은, 폴리실리콘층, 나이트라이드층이 차례로 적층된 구조를 형성하고 있는 것을 특징으로 하는 소자분리막 형성방법.The method of claim 1, wherein the anti-oxidation layer has a structure in which a polysilicon layer and a nitride layer are sequentially stacked. 제1항에 있어서, 상기 제1니트로젠 댕글링 본드층은, 15 내지 30Å 두께로 형성되는 것을 특징으로 하는 소자분리막 형성방법.The method of claim 1, wherein the first nitrogen dangling bond layer is formed to a thickness of 15 to 30 μm. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940031603A 1994-11-28 1994-11-28 Formation of element isolation KR0137585B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940031603A KR0137585B1 (en) 1994-11-28 1994-11-28 Formation of element isolation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940031603A KR0137585B1 (en) 1994-11-28 1994-11-28 Formation of element isolation

Publications (2)

Publication Number Publication Date
KR960019661A true KR960019661A (en) 1996-06-17
KR0137585B1 KR0137585B1 (en) 1998-06-01

Family

ID=19399349

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940031603A KR0137585B1 (en) 1994-11-28 1994-11-28 Formation of element isolation

Country Status (1)

Country Link
KR (1) KR0137585B1 (en)

Also Published As

Publication number Publication date
KR0137585B1 (en) 1998-06-01

Similar Documents

Publication Publication Date Title
KR970030640A (en) Method of forming device isolation film in semiconductor device
KR960019661A (en) Device Separator Formation Method
KR960012425A (en) Device Separator Formation Method of Semiconductor Device
KR960002744A (en) Device Separating Method of Semiconductor Device
KR950021401A (en) Trench Type Device Separator Manufacturing Method
KR970053396A (en) Device isolation oxide film fabrication method for highly integrated semiconductor devices
KR940016768A (en) Device isolation film formation method using trench
KR960035961A (en) Device Separator Formation Method
KR960002714A (en) Device isolation insulating film formation method of semiconductor device
KR960032674A (en) Field oxide layer formation method of semiconductor device
KR940016879A (en) Method for forming self-aligned contact of semiconductor device
KR960005939A (en) Method of forming semiconductor device isolation film
KR970052879A (en) Manufacturing method of semiconductor device
KR970052381A (en) Metal layer formation method of semiconductor device
KR960015855A (en) SOI structure and its manufacturing method
KR970030643A (en) Method of forming device isolation film of semiconductor device
KR960043105A (en) Device Separation Method of Semiconductor Device
KR950001908A (en) Contact hole formation method of semiconductor device
KR960026575A (en) Device Separating Method of Semiconductor Device
KR960035877A (en) Gate electrode formation method
KR950021096A (en) Contact hole formation method of semiconductor device
KR960035831A (en) Metal wiring formation method of semiconductor device
KR970053429A (en) Device Separation Method of Semiconductor Device
KR980005474A (en) Semiconductor device manufacturing method
KR960026555A (en) Method of forming device isolation layer of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060124

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee