KR960032674A - Field oxide layer formation method of semiconductor device - Google Patents

Field oxide layer formation method of semiconductor device Download PDF

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Publication number
KR960032674A
KR960032674A KR1019950003734A KR19950003734A KR960032674A KR 960032674 A KR960032674 A KR 960032674A KR 1019950003734 A KR1019950003734 A KR 1019950003734A KR 19950003734 A KR19950003734 A KR 19950003734A KR 960032674 A KR960032674 A KR 960032674A
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South Korea
Prior art keywords
layer
oxide layer
field oxide
forming
semiconductor device
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KR1019950003734A
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Korean (ko)
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KR100190361B1 (en
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엄금용
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김주용
현대전자산업 주식회사
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Priority to KR1019950003734A priority Critical patent/KR100190361B1/en
Publication of KR960032674A publication Critical patent/KR960032674A/en
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Publication of KR100190361B1 publication Critical patent/KR100190361B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체 소자의 필드 산화층 형성방법에 관한 것으로, 산소의 측면확산을 방지하여 버즈빅을 최소화 시키고, 이에 따라 큰 활성영역(Active area)을 확보할 수 있어 수율을 증대시키는 특유의 효과가 있는 반도체 소자의 필드산화층 형성방법에 관한 것이다.The present invention relates to a method for forming a field oxide layer of a semiconductor device, which minimizes buzz big by preventing side diffusion of oxygen, thereby securing a large active area, thereby increasing yield. A field oxide layer forming method of a semiconductor device.

Description

반도체 소자의 필드산화층 형성방법Field oxide layer formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명의 일실시예에 따른 필드산화층 형성과정을 도시한 공정 단면도2A through 2C are cross-sectional views illustrating a process of forming a field oxide layer according to an embodiment of the present invention.

Claims (8)

반도체 소자의 필드산화층 형성방법에 있어서, 반도체기판 상부에 제1나이트로젠 댕글링 본드층, 스트레스 방지층, 산화 방지층을 차례로 형성한 후, 상기 산화 방지층, 스트레스 방지층, 제1나이트로젠댕글링 본드층의 예정된 부위를 제거하여 필드산화층 형성을 위한 마스크 패턴을 형성하는 제1단계; 상기 마스크 패턴의 표면을 둘러싸도록 나이트라이드층을 형성하는 제2단계; 산화공정을 수행하는 제3단계를 포함하는 것을 특징으로 하는 반도체 소자의 필드산화층 형성방법In the method for forming a field oxide layer of a semiconductor device, after forming a first nitrogen dangling bond layer, a stress prevention layer, and an anti-oxidation layer on the semiconductor substrate, the anti-oxidation layer, the anti-stress layer, and the first nitrogen dangling bond layer Removing a predetermined portion to form a mask pattern for forming a field oxide layer; Forming a nitride layer to surround a surface of the mask pattern; A method of forming a field oxide layer in a semiconductor device comprising a third step of performing an oxidation process 제1항에 있어서, 상기 제1나이트로젠 댕글링 본드층은, 10 내지 30Å 두께로 형성되는 것을 특징으로 하는 반도체 소자의 필드산화층 형성방법The method of claim 1, wherein the first nitrogen dangling bond layer is formed to a thickness of 10 to 30 μm. 제1항에 있어서, 상기 스트레스 방지층은, 패드산화층, 폴리실리콘층이 차례로 적층된 구조를 갖는 것을 특징으로 하는 반도체 소자의 필드산화층 형성방법The method of claim 1, wherein the anti-stress layer has a structure in which a pad oxide layer and a polysilicon layer are sequentially stacked. 제1항 및 제3항에 있어서, 상기 스트레스 방지층의 예정된 부위 제거는, 상기 폴리실리콘층의 측면이 패드산화층에 비해 과도하게 제거되도록 하여 계단형태를 이루게 하는 것을 특징으로 하는 반도체 소자의 필드산화층 형성 방법The field oxide layer formation of the semiconductor device according to claim 1, wherein the predetermined portion of the anti-stress layer is removed so that the side surface of the polysilicon layer is excessively removed compared to the pad oxide layer to form a step shape. Way 제1항에 있어서, 상기 제2단계와 제3단계 사이에, 상기 반도체 기판 중 상기 마스크 패턴 주위의 일부두께를 제거해서 계단형태를 형성하는 제4단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 필드 산화층 형성 방법The semiconductor device of claim 1, further comprising a fourth step between the second and third steps, forming a stepped shape by removing a portion of the thickness around the mask pattern of the semiconductor substrate. Field oxide layer formation method 제5항에 있어서, 상기 제4단계 수행후, 노출된 상기 반도체 기판의 표면에 제2나이트로젠 댕글링 본드층을 형성하는 제5단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 필드산화층 형성방법The method of claim 5, further comprising, after performing the fourth step, forming a second nitrogen dangling bond layer on the exposed surface of the semiconductor substrate. 제6항에 있어서, 상기 제2나이트로젠 댕글링 본드층은, 10 내지 30Å두께로 형성되는 것을 특징으로 하는 반도체 소자의 필드산화층 형성방법7. The method of forming a field oxide layer of a semiconductor device according to claim 6, wherein the second nitrogen dangling bond layer is formed to have a thickness of 10 to 30 microseconds. 제1항에 있어서, 상기 나이트라이드층은, 100 내지 500Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 필드산화층 형성방법The method of claim 1, wherein the nitride layer is formed to a thickness of 100 to 500 GPa. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950003734A 1995-02-24 1995-02-24 Method of forming field oxide layer in a semiconductor device KR100190361B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950003734A KR100190361B1 (en) 1995-02-24 1995-02-24 Method of forming field oxide layer in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950003734A KR100190361B1 (en) 1995-02-24 1995-02-24 Method of forming field oxide layer in a semiconductor device

Publications (2)

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KR960032674A true KR960032674A (en) 1996-09-17
KR100190361B1 KR100190361B1 (en) 1999-06-01

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