KR960015629U - 반도체 패키지 - Google Patents
반도체 패키지Info
- Publication number
- KR960015629U KR960015629U KR2019940026407U KR19940026407U KR960015629U KR 960015629 U KR960015629 U KR 960015629U KR 2019940026407 U KR2019940026407 U KR 2019940026407U KR 19940026407 U KR19940026407 U KR 19940026407U KR 960015629 U KR960015629 U KR 960015629U
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor package
- package
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019940026407U KR200159720Y1 (ko) | 1994-10-10 | 1994-10-10 | 반도체 패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019940026407U KR200159720Y1 (ko) | 1994-10-10 | 1994-10-10 | 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960015629U true KR960015629U (ko) | 1996-05-17 |
KR200159720Y1 KR200159720Y1 (ko) | 1999-11-01 |
Family
ID=19395162
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019940026407U KR200159720Y1 (ko) | 1994-10-10 | 1994-10-10 | 반도체 패키지 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR200159720Y1 (ko) |
-
1994
- 1994-10-10 KR KR2019940026407U patent/KR200159720Y1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR200159720Y1 (ko) | 1999-11-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69518935D1 (de) | Halbleiterpackung | |
KR960012443A (ko) | 반도체 패키지 | |
KR960025455U (ko) | 반도체 패키지 | |
KR960006383U (ko) | 반도체 패키지 | |
KR960012677U (ko) | 반도체 패키지 | |
KR960015635U (ko) | 반도체패키지 | |
KR970059871U (ko) | 반도체 패키지 | |
KR980005467U (ko) | 반도체 패키지 | |
KR970056088U (ko) | 반도체 패키지 | |
KR960003142U (ko) | 반도체 패키지 | |
KR960025473U (ko) | 반도체 패키지 | |
KR960015629U (ko) | 반도체 패키지 | |
KR960006382U (ko) | 반도체 패키지 | |
KR960015631U (ko) | 반도체 패키지 | |
KR960025523U (ko) | 반도체 패키지 | |
KR960006374U (ko) | 반도체 패키지 | |
KR960025464U (ko) | 반도체 패키지 | |
KR960025466U (ko) | 반도체 패키지 | |
KR960006384U (ko) | 반도체 패키지 | |
KR960025490U (ko) | 반도체 패키지 | |
KR960025493U (ko) | 반도체 패키지 | |
KR950034382U (ko) | 반도체 패키지 | |
KR960025521U (ko) | 반도체 패키지 | |
KR950025925U (ko) | 반도체 패키지 | |
KR950028707U (ko) | 반도체 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
REGI | Registration of establishment | ||
FPAY | Annual fee payment |
Payment date: 20050721 Year of fee payment: 7 |
|
LAPS | Lapse due to unpaid annual fee |