KR960011697A

KR960011697A - Multi Channel Error Monitor Circuit

Info

Publication number: KR960011697A
Application number: KR1019940023743A
Authority: KR
Inventors: 이심호
Original assignee: 정장호; 엘지정보통신 주식회사
Priority date: 1994-09-16
Filing date: 1994-09-16
Publication date: 1996-04-20
Also published as: KR0171278B1

Abstract

본 발명은 다중 채널 에러 모니터(MULTI-CHANNEL ERROR MONITOR)회로에 관한 것으로, 특히 이격되어 있는 래크(RACK)나 셀프(SHELF)간의 데이타 전송시 여러 채널에 대한 데이타 페리티(parity)를 하나의 라인에 수용하고, 페리티 계산 회로에서도 간결하게 압축된 구성을 사용함으로써 전송 라인을 경감할 수 있도록 한 다중채널에러 모니터 회로에 관한 것이다.The present invention relates to a multi-channel error monitor (MULTI-CHANNEL ERROR MONITOR) circuit, in particular the data parity (parity) for several channels in the data transfer between the spaced rack (RACK) or self (SHELF) in one line And a multi-channel error monitor circuit that can reduce transmission lines by using a condensed compressed configuration in a parity calculation circuit.

이러한 본 발명은 각 채널(CH1∼CH3)로 부터 얻어진 직렬데이타(CH1-RXD∼CH3-RXD)와 페리티 리세트신호(PTRST)와를 배타적 논리합하는 배타적 오아게이트(100)와, 상기 직렬 데이타(CH1-RXD∼CH3-RXD)를 시스템 클럭(SYSCLK)에 동기시켜 시프트 시키는 JK플립플롭(101)과, 상기 JK플립플롭(101)의 출력 데이타를 상기 시스템 클럭(SYSCLK)에 동기시켜 출력하는 제1D플립플롭(102)과, 상기 시스템 클럭(SYSCLK)에 따라 프레임 펄스비트(FPBIT)를 카운트하는 카운터(103)와, 상기 카운터(103)의 출력신호(AQ1)(AQ2)를 논리조합하여 인에이블 펄스(PT1EN∼PT3EN)를 생성하는 인에이블 신호 발생부(104)와, 상기 인에이블 신호 발생부(104)의 출력신호와 상기 제1D플립플롭(102)의 출력신호와를 논리곱하여 출력하는 논리조합부(105)와, 상기 논리조합부(105)의 출력신호를 상기 시스템 클럭(SYSCLK)에 동기시켜 각 채널에 대한 페리티(PT1∼PT3)를 발생하는 페리티 발생부(106)와, 상기 페리티 발생부(106)에서 얻어진 각 채널에 대한 페리티를 논리합하여 출력하는 오아게이트(107)와, 상기 오아게이트(017)의 출력데이타를 상기 시스템 클럭(SYSCLK)에 동기시켜 출력하는 제2D플립플롭(108)으로 이루어진다.The present invention relates to an exclusive oragate 100 exclusively ORing the serial data CH1-RXD to CH3-RXD obtained from the respective channels CH1 to CH3 and the parity reset signal PTRST, and the serial data ( A JK flip-flop 101 for shifting CH1-RXD to CH3-RXD in synchronization with the system clock SYSCLK, and an output data in synchronization with the system clock SYSCLK for output data of the JK flip-flop 101; Logically combines the 1D flip-flop 102, the counter 103 for counting the frame pulse bits FPBIT in accordance with the system clock SYSCLK, and the output signals AQ1 and AQ2 of the counter 103. Enable and output the enable signal generator 104 generating the enable pulses PT1EN to PT3EN, the output signal of the enable signal generator 104 and the output signal of the first D flip-flop 102 Synchronizes the logic combiner 105 and the output signal of the logic combiner 105 with the system clock SYSCLK In turn, the parity generator 106 generates a parity (PT1 to PT3) for each channel, and the oragate 107 outputs the logical result of the parity for each channel obtained by the parity generator 106. And a second D flip-flop 108 which outputs the output data of the orifice 017 in synchronization with the system clock SYSCLK.

Description

Multi Channel Error Monitor Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명 다중 채널 에러 모니터 회로 개념도.3 is a conceptual diagram of a multi-channel error monitor circuit of the present invention.

제4도는 본 발명 다중 채널 에러 모니터 회로 구성도.4 is a schematic diagram of a multi-channel error monitor circuit of the present invention.

제5도는 (a) 내지 (k)는 제4도의 각부 입,출력 파형도.5 is a (a) to (k) is the input and output waveform diagram of each part of FIG.

Claims

An exclusive oragate 100 exclusively ORing the serial data CH1-RXD to CH3-RXD obtained from the channels CH1 to CH3 and the parity reset signal PTRST, and the serial data CH1-RXD to JK flip-flop 101 for shifting CH3-RXD in synchronization with the system clock SYSCLK, and first D flip-flop for outputting the output data of the JK flip-flop 101 in synchronization with the system clock SYSCLK. 102, the counter 103 for counting the frame pulse bits FPBIT in accordance with the system clock SYSCLK, and the enable signal PT1EN by logically combining the output signals AQ1 and AQ2 of the counter 103. Logical combination unit for outputting the enable signal generating unit 104 to generate PT-3EN, and the output signal of the enable signal generating unit 104 and the output signal of the first D flip-flop 102 105 and the output signal of the logic combination unit 105 in synchronization with the system clock (SYSCLK) for each channel A parity generator 106 for generating parities PT1 to PT3, an oragate 107 for logically outputting the parity for each channel obtained by the parity generator 106, and the oragate And a second D flip-flop (108) for outputting the output data in synchronization with the system clock (SYSCLK).

The first and second 104 gate signals of claim 1, wherein the enable signal generator 104 logically multiplies the inverted signals of the first and second signals AQ1 and AQ2 output from the counter 103. ), A second and gate 104b for ANDing the first time signal AQ1 output from the counter 103 and the inverted signal of the second signal AQ2, and the second output signal from the counter 103. A multi-channel error monitor circuit comprising: a third end gate (104C) that ANDs the signal (AQ2) with the inverted signal of the first signal (AQ1).

The logic combination unit (105) of claim 1 or 2, wherein the logic combination unit (105) is formed of the first channel parity (CH1-PT) obtained from the first flip-flop (102) and the enable signal generator (104). A first end gate 105a that is logically multiplied by the output signal of the first end gate 104a, a second channel parity CH2-PT obtained by the first D flip-flop 102, and the enable signal generator ( The second and gate 105b, which is ANDed by the output signal of the second and gate 104b in 104, the third channel parity CH3-PT obtained from the first D flip-flop 102, and the enable. And a third end gate (105C) that logically multiplies the output signal of the third end gate (104C) in the signal generator (104).

The parity generator 106 of claim 1, wherein the parity generator 106 synchronizes the output data of the first gate 105a in the logic combination unit 105 with the system clock SYSCLK. The first D flip-flop 106a which generates PT1 and the output data of the second and gate 105b in the logic combination unit 105 are synchronized with the system clock SYSCLK for the second channel. The 2D flip-flop 106b which generates PT2 and the output data of the 3rd gate 105c in the said logic combination part 105 are synchronized with the system clock SYSCLK, and the ferrimony for the 3rd channel is carried out. And a 3D flip-flop (106c) generating PT3.

※ Note: The disclosure is based on the initial application.