KR950033810A - Partial Product Row Generation Circuit in Modified Booth Multiplier - Google Patents

Abstract

The partial product row generation circuit performs a parallel processing of one partial product row generation process in a modified booth multiplier and uses a signal that reestablishes the relationship between the multiplier and the multiplier in consideration of the complementary processing performed at the partial product row generation. It can reduce the time required to generate partial product rows without going through the process. To this end, the circuit comprises: output means for dividing a bit of one partial product row into at least three parts; And a signal generating means for generating an input signal corresponding to the size of the bit data of the partial product row output from the output means and a control signal for controlling the operation of the output means using the multiplicand and the multiplier, and transmitting the generated signal to the output means. It is configured to include.

Description

Partial Product Row Generation Circuit in Modified Booth Multiplier

Since this is an open matter, no full text was included.

2 is a partial product row generation circuit in a modified bus multiplier according to the present invention.

Claims (6)

A partial product row generation circuit for performing a modified booth multiplication using a multiplier of a first predetermined bit and a multiplier of a second predetermined bit; Output means for generating a bit of one partial product row by dividing it into at least three parts; And generating an input signal corresponding to the size of the bit data of the partial product row output from the output means and a control signal for controlling the operation of the output means by using the multiplier and the multiplier, and transmitting the generated control signal to the output means. A partial product row generation circuit comprising signal generation means. The partial product row generation circuit according to claim 1, wherein the output means is configured such that the bits of the partial product row are divided into the least significant bit, the most significant bit, and the remaining bits except the least significant bit and most significant bit. 3. The bit of the partial product row according to claim 2, wherein said output means selectively outputs a multiplexer for selectively outputting at least two input signals provided from said signal generating means by at least one control signal provided from said signal generating means. A partial product row generation circuit, characterized in that it is provided so as to correspond to the number divided by. 4. The partial product row generation circuit according to claim 3, wherein the signal generation means comprises a number of signal generators corresponding to the multiplexer. The signal generating means according to claim 2, wherein the signal generating means generates a signal by generating the input signal and the control signal corresponding to the most significant bit, the least significant bit, and the remaining bit by logically combining the bits of the multiplier and the multiplier according to a predetermined rule. A partial product row generation circuit comprising a generator. 6. The signal generating means according to claim 5, wherein the signal generating means comprises Z0 and S1 by a logical combination as shown in Equation (1) to generate data of least significant bit of the partial product row when the multiplicand and the multiplier are each 6 bits. A first signal generator for generating the most significant bit of the multiplier used (X3 when generating the second partial product row), S1 = X2 XOR X1 (where X2 and X1 are bits of the multiplier used, where X2 is the second) Bit, and X1 is the least significant bit.) Z0 = Y0 (least significant bit of multiplicand) XOR X3 (least significant bit of multiplier used) (1) Generating the control signal S3, the most significant bit (X3) of the multiplier and the most significant bit (Z5) of the multiplier as input signals to generate data of the remaining bits of the partial product row as shown in Equation (2) A second signal generator, and S3 = (X3 XOR X2) XOR (X2 XOR X1) (2) And a third signal generator 23 for generating the control signals S2 and the input signals Zi and Ki by a logical combination as shown in Equation (3) to generate the most significant bit data of the partial product row. Partial row generation circuit, characterized in that. S2 = S1 (3) Ki = (Zi-1 AND K＿OR) OR K＿AND K＿AND = X3 AND X2 K＿OR = X3 OR X2 ※ Note: The disclosure is based on the initial application.