KR950006584A - A multiplication circuit - Google Patents

A multiplication circuit Download PDF

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Publication number
KR950006584A
KR950006584A KR1019930016219A KR930016219A KR950006584A KR 950006584 A KR950006584 A KR 950006584A KR 1019930016219 A KR1019930016219 A KR 1019930016219A KR 930016219 A KR930016219 A KR 930016219A KR 950006584 A KR950006584 A KR 950006584A
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KR
South Korea
Prior art keywords
complement
multiplication
unsigned
input
enable signal
Prior art date
Application number
KR1019930016219A
Other languages
Korean (ko)
Inventor
김영준
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019930016219A priority Critical patent/KR950006584A/en
Publication of KR950006584A publication Critical patent/KR950006584A/en

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Abstract

본 발명은 언사인드와 2의 보수를 모두 수행하는 승산회로에 관한 것이다.The present invention relates to a multiplication circuit that performs both unsigned and two's complement.

본 발명은 2의 보수 입력시 2의 보수처리를 하여 출력하고, 동시에 2의 보수 인에이블 신호를 생성하여 출력하는 제1보수부와, 이 제1보수부의 출력에 언사인드 승산을 수행하는 승산부와, 이 제1보수부에서 출력되는 2의 보수인에이블 신호가 입력되면 승산부의 승산 결과에 2의 보수 처리를 하여 출력하는 제2보수부로 구성됨으로서, 언사인드와 2의 보수기능을 모두 수행하면서도 회로의 간소화가 도모되는 것이다.The present invention provides a first maintenance unit that performs two's complement processing at the input of two's complement, generates and outputs a two's complement enable signal, and a multiplier that performs unsigned multiplication to the output of the first complement. And a second maintenance unit that outputs two's complement processing to the multiplication result of the multiplication unit when the two's complement enable signal output from the first maintenance unit is input, thereby performing both an unsigned and two's complement function. The circuit is simplified.

Description

승산회로A multiplication circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 승산회로를 나타낸 블록도.1 is a block diagram showing a multiplication circuit according to the present invention.

제2도는 본 발명에 따른 언사인드 승산 과정과 2의 보수처리 과정의 시뮬레이션 결과를 나타낸 타이밍도이다.2 is a timing diagram showing simulation results of an unsigned multiplication process and a two's maintenance process according to the present invention.

Claims (1)

2의 보수 입력시 2의 보수처리를 하여 출력하고, 동시에 2의 보수 인에이블 신호를 생성하여 출력하는 제1보수수단과; 상기 제1보수수단의 출력에 언사인드 승산을 수행하는 승산수단과; 상기 제1보수수단에서 출력되는 2의 보수 인에이블 신호가 입력되면 상기 승산수단의 승산 결과에 2의 보수 처리를 하여 출력하는 제2보수수단으로 이루어진 승산회로.First complementary means for performing two's complement processing at the input of two's complement and simultaneously generating and outputting a two's complement enable signal; Multiplication means for performing an unsigned multiplication on the output of the first repair means; And a second repair means for outputting a two's complement process to a multiplication result of the multiplication means when the two's complement enable signal output from the first repair means is input. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930016219A 1993-08-20 1993-08-20 A multiplication circuit KR950006584A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930016219A KR950006584A (en) 1993-08-20 1993-08-20 A multiplication circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930016219A KR950006584A (en) 1993-08-20 1993-08-20 A multiplication circuit

Publications (1)

Publication Number Publication Date
KR950006584A true KR950006584A (en) 1995-03-21

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ID=66817705

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930016219A KR950006584A (en) 1993-08-20 1993-08-20 A multiplication circuit

Country Status (1)

Country Link
KR (1) KR950006584A (en)

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