KR960009986B1 - Manufacturing method of semiconductor device metal wiring - Google Patents

Manufacturing method of semiconductor device metal wiring Download PDF

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KR960009986B1
KR960009986B1 KR1019930016051A KR930016051A KR960009986B1 KR 960009986 B1 KR960009986 B1 KR 960009986B1 KR 1019930016051 A KR1019930016051 A KR 1019930016051A KR 930016051 A KR930016051 A KR 930016051A KR 960009986 B1 KR960009986 B1 KR 960009986B1
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metal layer
forming
protective film
metal wiring
metal
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KR1019930016051A
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Korean (ko)
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KR950007065A (en
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박상훈
박대일
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현대전자산업 주식회사
김주용
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Abstract

removing a native oxide film formed on a metal layer(3); unetching the metal layer(3) at 60 or 90 %; forming a side passivation film to protect the side wall of the metal layer(3); overetching the metal layer(3); forming a passivation film; and proceeding the process of forming the passivation by CHF3 gas for one or five minutes to prevent the corrosion. The method improves the electrical characteristics of the metal wire.

Description

반도체 소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

제1도는 일반적인 금속배선 구조도.1 is a general metal wiring structure diagram.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 절연층2 : 장벽금속층1 Insulation layer 2 Barrier metal layer

3 : 금속층3: metal layer

본 발명은 반도체 소자의 제조공정중 소자간의 전기적 접속을 위한 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming metal wirings for semiconductor devices for electrical connection between the devices in the manufacturing process of the semiconductor devices.

장벽금속(barrier metal)이 포함된 일반적인 금속배선 구조는 첨부된 도면 제1도에 도시된 바와 같고, 도면 부호 1은 절연층, 2는 장벽금속층, 3은 금속층을 각각 나타낸다. 이때 상기 절연층은 통상 BPSG(Boro Phospho Silicate Glass)막, 장벽금속막은 1000Å 두께의 티타늄나이트라이드(TiN)막 또는 티타늄(Ti)막, 금속층은 1000Å 두께의 알루미늄막으로 이루어진다.A general metallization structure including a barrier metal is as shown in FIG. 1, the reference numeral 1 denotes an insulating layer, 2 denotes a barrier metal layer, and 3 denotes a metal layer. In this case, the insulating layer is typically a BPSG (Boro Phospho Silicate Glass) film, the barrier metal film is made of a titanium nitride (TiN) film or a titanium (Ti) film having a thickness of 1000 Å, and the metal layer is an aluminum film having a thickness of 1000 Å.

한편, 금속배선층 형성을 위한 패턴 형성시 RIE(reactive ion etchig; 이하 RIE라 칭함) 방식으로 식각하는데 이 방법은 원자에 고에너지를 가해 이온 충걱(ion bombardment) 기법으로 식각함으로써 감광막 패턴의 미세선폭을 정확하게 묘획할 수 있어 정확한 패턴형성에 주로 이용된다.On the other hand, when forming a pattern for forming a metal wiring layer is etched by a reactive ion etchig (RIE) method, a method of applying a high energy to the atoms to etch by ion bombardment technique to reduce the fine line width of the photoresist pattern It can be accurately drawn and is mainly used for accurate pattern formation.

장벽금속이 있는 금속배선층을 RIE 방식으로 식각하는 종래의 기술을 통상 다음과 같다.Conventional techniques for etching a metal wiring layer having a barrier metal by the RIE method are generally as follows.

먼저, 제1단계는 금속층 상에 형성된 자연산화막을 제거하는 공정으로 10Cl2/140BCl3/25mT/-250V/150sec의 공정조건하에서 진행한다.First, the first step is a process of removing the natural oxide film formed on the metal layer and proceeds under process conditions of 10Cl 2 / 140BCl 3 / 25mT / -250V / 150sec.

제2단계는 금속층을 식각하는 공정으로 38Cl2/150BCl2/10CHF3/25mT/-200V/16min의 공정조건 하에서 진행한다.The second step is to etch the metal layer and proceed under the process conditions of 38Cl 2 / 150BCl 2 / 10CHF 3 / 25mT / -200V / 16min.

제3단계는 상기 금속층을 과도식각하는 공정으로 20Cl2/150BCl2/15CHF3/30mT/-210V/18min의 공정조건 하에서 진행한다.The third step is a process of over-etching the metal layer and proceeds under process conditions of 20Cl 2 / 150BCl 2 / 15CHF 3 / 30mT / -210V / 18min.

제4단계는 F기에 의하여 Cl기를 치환하여 보호막을 형성하는 공정으로 50CF4/15CHF3/80mT/250w/10 내지 20min의 공정조건 하에서 진행한다.The fourth step is to form a protective film by replacing the Cl group by the F group to proceed under the process conditions of 50CF 4 / 15CHF 3 / 80mT / 250w / 10 to 20min.

여기서 상기 제3단계의 과도식각 공정은 적절한 조절을 위해 35Cl2/140BCl3/15CHF3/25mT/－200V/6min,20Cl2/150BCl3/15CHF3/30mT/250w/2min의 2단계로 분할하여 진행할 수도 있다.Here, the third etching process is divided into two stages of 35Cl 2 / 140BCl 3 / 15CHF 3 / 25mT / -200V / 6min and 20Cl 2 / 150BCl 3 / 15CHF 3 / 30mT / 250w / 2min for proper control. You can also proceed.

그러나 상기와 같은 종래방법으로는 단차가 큰 부위가 금속배선이 좁아지게되는 네킹(necking) 현상과 금속배선의 단면이 음의 기울기(negative-slope)를 갖게되어 금속배선이 단선되는 등의 소자 불량을 초래하게 된다.However, in the conventional method as described above, a device defect such as a necking phenomenon in which a large step is narrowed and a cross-section of the metal wiring has a negative slope due to a narrowing of the metal wiring are broken. Will result.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 금속배선형성을 위한 장벽금속 식각시 발생되는 제반 문제를 해결하여 금속배선의 전기적 특성을 향상시키는 반도체 소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method for forming a metal wiring of the semiconductor device to improve the electrical properties of the metal wiring by solving the problems caused during the etching of the barrier metal for metal wiring formation. have.

상기 목적을 달성하기 위하여 본 발명의 반도체 소자의 금속배선 형성방법은 금속층 상에 형성된 자연산화막을 제거하는 제1단계와, 상기 금속층을 60 내지 90%로 과소식각하는 제2단계와, 상기 금속층 측면을 보호하기 위한 측면보호막을 형성하는 제3단계와, 상기 금속층을 과도식각하는 제4단계와, 보호막을 형성하는 제5단계와, 상기 보호막 형성시 불완전한 반응에 의한 부식현상을 예방하기 위해 CHF3가스에 의한 보호막 형성공정을 1 내지 5분간 추가로 진행하는 제6단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a method for forming a metal wiring of a semiconductor device according to the present invention includes a first step of removing a natural oxide film formed on a metal layer, a second step of overetching the metal layer by 60 to 90%, and the side of the metal layer. A third step of forming a side protective film to protect the metal layer, a fourth step of overetching the metal layer, a fifth step of forming a protective film, and CHF 3 to prevent corrosion due to an incomplete reaction when forming the protective film. And a sixth step of further performing the protective film forming process by gas for 1 to 5 minutes.

이하, 본 발명을 상술한다.Hereinafter, the present invention will be described in detail.

본 발명은 금속층 식각시 일차로 70 내지 80%의 금속층을 식각하는 과소식각(unetch) 공정을 진행한 다음 CHF3가스에 의한 금속층의 측면을 보호하기 위한 보호막을 형성하고 이후에 나머지 부분을 과도식각(overetch) 하는 기술이다.In the present invention, during the etching of the metal layer, an unetch process of etching 70 to 80% of the metal layer is first performed, followed by forming a protective film for protecting the side of the metal layer by CHF 3 gas, and then over-etching the remaining portion. (overetch) technology.

상기 기술적 원리를 구현하기 위한 공정절차를 단계별로 구체적으로 보면 다음과 같다.Looking at the step-by-step process procedure for implementing the above technical principle in detail.

제1단계는 금속층 상에 형성된 자연산화막을 제거하는 공정으로 10Cl2/140BCl3/25mT/-250V/2 내지 3min의 공정조건하에서 진행한다.The first step is to remove the natural oxide film formed on the metal layer and proceeds under process conditions of 10Cl 2 / 140BCl 3 / 25mT / -250V / 2 to 3min.

제2단계는 금속층을 과소식각하는 공정으로 35Cl2/150BCl2/15CHF3/30mT/-180V/12 내지 14min의 공정조건 하에서 진행한다.The second step is carried out under process conditions 35Cl the step of under-etching the metal layer 2 / 150BCl 2 / 15CHF 3 / 30mT / -180V / 12 to 14min.

제3단계는 상기 금속층 측면을 보호하기 위한 측면보호막을 형성하기 위한 공정으로 50CHF3/100mT/160w/5 내지 8min의 공정조건 하에서 진행한다.The third step is a process for forming a side protective film for protecting the side of the metal layer and proceeds under process conditions of 50CHF 3 / 100mT / 160w / 5 to 8min.

제4단계는 상기 금속층을 과도식각하는 공정으로 20Cl2/150BCl3/15CHF3/30mT/-250V/16 내지 18min의 공정조건하에서 진행한다.The fourth step is a process of over-etching the metal layer and proceeds under process conditions of 20Cl 2 / 150BCl 3 / 15CHF 3 / 30mT / -250V / 16 to 18min.

제5단계는 F기에 의하여 Cl기를 치환하여 보호막을 형성하는 공정으로 50CF4/50CHF3/80mT/250w/10min의 공정조건 하에서 진행한다.The fifth step is to form a protective film by replacing the Cl group by the F group to proceed under the process conditions of 50CF 4 / 50CHF 3 / 80mT / 250w / 10min.

제6단계는 F기에 의하여 Cl기를 치환하여 보호막을 형성하는 상기 제5단계의 불충분한 보호막을 추가로 형성하기 위해 50CHF3/100mT/160w/3min의 공정을 추가로 진행함으로써 네킹현상 및 부식현상을 방지할 수 있다.The sixth step further proceeds with 50CHF 3 / 100mT / 160w / 3min to form an inadequate protective film of the fifth step in which the Cl group is replaced by the F group to form a protective film. You can prevent it.

또한 식각후의 감광막 제거시 O2플라즈마를 이용한 건식식각만으로는 감광막을 완전히 제거할 수 없으므로 반드시 감광막 제거용의 화학용제를 사용해야 한다.In addition, when the photoresist film is removed after etching, dry etching using O 2 plasma alone cannot completely remove the photoresist film. Therefore, a chemical solvent for photoresist film removal must be used.

상기와 같은 공정수순을 밟아 이루어지는 본 발명의 반도체 소자의 금속배선 형성방법은 네킹현상 및 부식현상을 방지하고 양호한 금속배선을 형성할 수 있으므로 소자의 특성 및 신뢰성 향상의 효과를 얻을 수 있다.The metal wiring forming method of the semiconductor device of the present invention, which is subjected to the above-described process procedure, can prevent necking and corrosion and can form a good metal wiring, thereby improving the characteristics and reliability of the device.

Claims (2)

소자간의 전기적 접속을 위한 반도체 소자의 금속배선 형성방법에 있어서, 금속층 상에 형성된 자연산화막을 제거하는 제1단계와, 상기 금속층을 60 내지 90%로 과소식각하는 제2단계와, 상기 금속층 측면을 보호하기 위한 측면보호막을 형성하는 제3단계와, 상기 금속층을 과도식각하는 제4단계와, 보호막을 형성하는 제5단계와, 상기 보호막 형성시 불완전한 반응에 의한 부식현상을 예방하기 위해 CHF3가스에 의한 보호막 형성공정을 1 내지 5분간 추가로 진행하는 제6단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.A method for forming a metal wiring of a semiconductor device for electrical connection between devices, the method comprising: a first step of removing a natural oxide film formed on a metal layer, a second step of overetching the metal layer by 60 to 90%, and a side surface of the metal layer A third step of forming a side protective film for protection, a fourth step of overetching the metal layer, a fifth step of forming a protective film, and a CHF 3 gas to prevent corrosion due to an incomplete reaction when forming the protective film. And a sixth step of further performing the protective film forming process for 1 to 5 minutes. 제1항에 있어서, 상기 CHF3가스에 의한 보호막 형성시 공정조건은 50 내지 100sccm의 CHF3, 80 내지 120mTorr의 압력, 140 내지 200W의 전력, 3 내지 10분간의 시간인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the CHF upon process conditions to form a protective film according to the third gas has a semiconductor element, characterized in that from 50 to CHF 3, from 80 to 120mTorr pressure of 100sccm, 140 to 200W of power, of 3 to 10 seconds for Metal wiring formation method.
KR1019930016051A 1993-08-18 1993-08-18 Manufacturing method of semiconductor device metal wiring KR960009986B1 (en)

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KR100431317B1 (en) * 1997-06-30 2004-07-19 주식회사 하이닉스반도체 Method of forming metal line of semiconductor device using protection layer
KR101016305B1 (en) * 2004-02-09 2011-02-22 엘지전자 주식회사 Motor Locking System of a Washing Machine and a Controlling Method for the Same

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