KR100431317B1 - Method of forming metal line of semiconductor device using protection layer - Google Patents

Method of forming metal line of semiconductor device using protection layer Download PDF

Info

Publication number
KR100431317B1
KR100431317B1 KR1019970030416A KR19970030416A KR100431317B1 KR 100431317 B1 KR100431317 B1 KR 100431317B1 KR 1019970030416 A KR1019970030416 A KR 1019970030416A KR 19970030416 A KR19970030416 A KR 19970030416A KR 100431317 B1 KR100431317 B1 KR 100431317B1
Authority
KR
South Korea
Prior art keywords
film
metal
forming
etching
semiconductor device
Prior art date
Application number
KR1019970030416A
Other languages
Korean (ko)
Other versions
KR19990006194A (en
Inventor
박현
심규철
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019970030416A priority Critical patent/KR100431317B1/en
Publication of KR19990006194A publication Critical patent/KR19990006194A/en
Application granted granted Critical
Publication of KR100431317B1 publication Critical patent/KR100431317B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: A method of forming a metal line of a semiconductor device is provided to obtain uniform line width in metal lines by preventing a sidewall of the metal line from being etched using a protecting layer. CONSTITUTION: A metal film(210) made of a Cu film, an Al film or a polysilicon layer is formed on a lower layer(200). A mask pattern(220) is formed thereon. A metal line is formed by etching selectively the metal film using an etching gas. At this time, A protection layer(230) is formed at both sidewalls of the metal line by flowing one selected from a group consisting of oxygen, ammonium or CHF3 as a reaction gas.

Description

반도체 소자의 금속 배선 방법Metal wiring method of semiconductor device

본 발명은 반도체 소자의 금속 배선 방법에 관한 것으로, 특히 금속 배선을 형성을 위한 식각 공정 진행시 식각으로 노출되는 금속 배선의 측벽에 보호막이 형성되도록 하여 금속 배선의 측벽이 식각되는 것을 방지함으로써 균일한 선폭을 갖는 반도체 소자의 금속 배선 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring method of a semiconductor device. In particular, a protective film is formed on a sidewall of a metal wiring exposed by etching during an etching process for forming a metal wiring, thereby preventing the sidewall of the metal wiring from being etched. A metal wiring method of a semiconductor device having a line width.

일반적으로, 구리는 전기 비저항(1.7 ????-cm)이 낮고 일렉트로마이크레이션에 대해 높은 저항성을 갖기 때문에 서브마이크론 이하로 반도체 소자를 제조하는 경우 전도성 물질로 유망하다.In general, copper is promising as a conductive material when fabricating semiconductor devices below submicron because of its low electrical resistivity (1.7 ° -cm) and high resistance to electromigration.

반도체 소자의 구리 배선은 하기의 반응식을 이용하여 화학적으로 식각하며, 플라즈마를 이용하여 물리적으로 방향성을 갖는 식각을 한다.The copper wiring of the semiconductor device is chemically etched using the following reaction formula, and physically directionally etched using plasma.

Cu2+(hfac)2(g)+ 2VTMS+ Cu(s)→2cu2+(hfac)·VTMS(g) Cu 2+ (hfac) 2 (g) + 2VTMS + Cu (s) → 2cu 2+ (hfac) VTMS (g)

(여기서, hfac: Hexa fluoro acethyl acetonate이고,(Here, hfac: Hexa fluoro acethyl acetonate,

VTMS: Vinl tri-methyl silane)VTMS: Vinl trimethyl silane)

도 1A 및 도 1B는 종래의 구리 배선 형성 과정을 나타내는 공정 단면도로, 충간 절연막과 같은 하부층(100) 상에 구리막(110)이 증착되어 있고, 구리막 상부에 구리 배선 형성을 위한 마스크 패턴(120)이 형성되어 있다.1A and 1B are cross-sectional views illustrating a conventional copper wiring forming process, in which a copper film 110 is deposited on a lower layer 100 such as an interlayer insulating film, and a mask pattern for forming copper wiring on the copper film ( 120 is formed.

이어서, 상기 마스크 패턴(120)을 이용하여 상기의 반응식으로 구리막(110)을 식각한다.Subsequently, the copper layer 110 is etched using the mask pattern 120 by the reaction scheme.

그러나, 도 1B와 같이 구리막의 식각이 진행됨에 따라 식각으로 인해 노출되는 구리 배선의 측벽도 물리적 또는 화학적 반응으로 인해 식각된다. 이와 같은 구리 배선의 측벽 식각이 심한 경우 그 부분의 전류 밀도가 높아져 단선 가능성이 있다.However, as the etching of the copper film proceeds as shown in FIG. 1B, the sidewalls of the copper wiring exposed by the etching are also etched due to the physical or chemical reaction. If the sidewall etching of such a copper wiring is severe, there is a possibility that the current density of the portion will be high, resulting in disconnection.

따라서, 이와 같은 구리 배선 식각 방법은 금속 배선의 선폭을 불균일하게하여 금속 배선에 대한 신뢰성을 저하시킨다. 그러나, 상기와 같은 문제점은 구리 금속에만 한정되는 것이 아니고, 알루미늄이나 폴리실리콘을 사용하는 경우에도 발생한다.Therefore, such a copper wiring etching method uneven the line width of the metal wiring, thereby lowering the reliability of the metal wiring. However, the above problems are not limited to copper metal, but occur even when aluminum or polysilicon is used.

상기에서 언급한 바와 같이 종래의 구리 배선 공정은 식각시 원치 않는 구리 배선의 측벽 식각으로 인하여 선폭이 불균일하거나 단선되어 반도체 소자의 금속 배선에 대한 신뢰성을 저하시키는 문제점이 있다.As mentioned above, the conventional copper wiring process has a problem in that the line width is uneven or disconnected due to sidewall etching of the unwanted copper wiring during etching, thereby lowering the reliability of the metal wiring of the semiconductor device.

따라서, 본 발명은 구리, 알루미늄 등을 사용한 반도체 소자의 금속 배선 형성시 식각 가스와 함께, 금속과 반응하여 박막을 형성하는 반응 가스를 주입함으로써 식각으로 노출된 금속 배선의 측벽에 보호막을 형성하여 금속 배선의 측벽 식각을 방지함으로써 균일한 선폭의 금속 배선을 형성할 수 있는 반도체 소자의 금속 배선 방법을 제공하는데 그 목적이 있다.Therefore, in the present invention, a protective film is formed on the sidewall of the metal wiring exposed by etching by injecting a reaction gas which forms a thin film by reacting with the metal together with the etching gas when forming the metal wiring of the semiconductor device using copper, aluminum, or the like. SUMMARY OF THE INVENTION An object of the present invention is to provide a metal wiring method of a semiconductor device capable of forming a metal wiring having a uniform line width by preventing sidewall etching of the wiring.

도 1A 및 도 1B는 종래 반도체 소자의 금속 배선 공정을 나타내는 단면도.1A and 1B are cross-sectional views illustrating a metal wiring process of a conventional semiconductor device.

도 2A및 도 2B는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 공정을 나타내는 단면도.2A and 2B are cross-sectional views illustrating a metal wiring process of a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100, 200: 하부층 110, 210: 구리막100, 200: lower layer 110, 210: copper film

120, 220: 마스크 패턴 230: 보호막120, 220: mask pattern 230: protective film

상기 목적을 달성하기 위하여, 본 발명에 따른 반도체 소자의 금속 배선을 형성하기 위하여 반도체 기판 상에 금속막이 기형성된 반도체 소자의 금속 배선 방법으로서, 상기 금속막 상에, 사진 공정을 통하여 금속 배선 형성을 위한 마스크 패턴을 형성하는 단계;및 상기 마스크 패턴과 식각 가스를 사용하여 상기 금속막을 식각하며, 상기 식각 가스와 함께 금속막과 반응하는 반응 가스를 주입하여 식각으로 인해 노출되는 금속 배선의 측벽에 보호막을 형성함으로써 상기 금속 배선의 측벽이 식각되는 것을 방지하여 균일한 선폭의 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a metal wiring method of a semiconductor device with a metal film pre-formed on a semiconductor substrate in order to form a metal wiring of the semiconductor device according to the present invention, on the metal film, forming a metal wiring through a photo process Forming a mask pattern for etching the metal film using the mask pattern and an etching gas, and implanting a reaction gas reacting with the metal film together with the etching gas to protect a sidewall of a metal wiring exposed by etching Forming a metal wire having a uniform line width by preventing the sidewall of the metal wire from being etched by forming a metal wire.

[실시예]EXAMPLE

이하, 첨부된 도면을 참조로하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 2A 및 도 2B는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성과정을 나타내는 공정 단면도이다.2A and 2B are cross-sectional views illustrating a process of forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

먼저, 층간 절연막과 같은 하부층(200) 상에 구리막(210)이 증착되어 있고, 구리막 상부에 금속 배선 형성을 위한 마스크 패턴(220)이 형성되어 있다.First, a copper film 210 is deposited on a lower layer 200 such as an interlayer insulating film, and a mask pattern 220 for forming metal wirings is formed on the copper film.

이어서, 상기 마스크 패턴(220)을 이용하여 구리막(110)을 식각한다. 이때, Cu2+(hfac)2, 2VTMS로 구성된 식각 가스와 함께 O2가스를 주입한다. 이 O2가스는 구리 배선의 측벽에 노출된 구리와 반응하여 보호막(230)을 형성함으로써 측면으로 식각되는 것을 방지한다.Subsequently, the copper layer 110 is etched using the mask pattern 220. At this time, O 2 gas is injected together with the etching gas consisting of Cu 2+ (hfac) 2 and 2VTMS. This O 2 gas reacts with the copper exposed on the sidewalls of the copper wiring to form a protective film 230 to prevent side etching.

따라서, 상기 반응 가스량를 적절히 조절하여 구리막의 식각이 수직 방향으로만 되게 함으로써, 도 2B와 같이 균일한 선폭의 구리 배선을 얻을 수 있다.Therefore, by appropriately adjusting the amount of the reaction gas so that the copper film is etched only in the vertical direction, a copper wiring having a uniform line width can be obtained as shown in FIG. 2B.

또한, 구리 외에 알루미늄을 사용하는 경우는 CHF3가스를, 폴리실리콘을 사용하는 경우는 산소(O2) 또는 암모늄(NH3) 가스를 적절히 주입한다.In addition, when aluminum is used other than copper, CHF 3 gas is used, and when polysilicon is used, oxygen (O 2 ) or ammonium (NH 3 ) gas is appropriately injected.

이상에서 설명한 바와 같이, 본 발명은 구리, 알루미늄 등을 사용한 반도체 소자의 금속 배선 형성시 식각 가스와 함께, 금속과 반응하여 박막을 형성하는 반응 가스를 주입함으로써 식각으로 노출된 금속 배선의 측벽에 보호막을 형성하여 금속 배선의 측벽 식각을 방지함으로써 균일한 선폭의 금속 배선을 형성할 수 있다.As described above, the present invention is a protective film on the sidewall of the metal wiring exposed by etching by injecting a reaction gas to form a thin film by reacting with the metal when forming the metal wiring of the semiconductor device using copper, aluminum, etc. By forming the metal wires to prevent sidewall etching of the metal wires, metal wires having a uniform line width can be formed.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

Claims (4)

반도체 소자의 금속배선 형성용 금속막을 형성하는 방법에 있어서,In the method of forming the metal film for metal wiring formation of a semiconductor element, 하부층상에 구리막, 알루미늄막 또는 폴리실리콘막으로 구성된 금속막을 형성하는 단계,Forming a metal film composed of a copper film, an aluminum film or a polysilicon film on the lower layer, 상기 금속막상에 사진 공정을 통하여 금속 배선 형성을 위한 마스크 패턴을 형성하는 단계; 및Forming a mask pattern for forming metal wiring on the metal film through a photo process; And 상기 마스크 패턴을 마스크로 식각 가스를 사용하여 상기 금속막을 식각하면서 상기 식각 가스와 함께 금속막과 반응하는 반응 가스인 산소, 암모늄 또는 CHF3중에서 어느 하나를 선택하여 주입하므로써 식각으로 인해 노출되는 금속배선의 측벽에 보호막을 형성하여 균일한 선폭의 금속 배선을 형성하는 단계;를 포함하여 구성되는 것을 특징으로하는 반도체소자의 금속배선 형성방법.A metal wiring exposed by etching by selecting and injecting one of oxygen, ammonium, or CHF 3 , which is a reaction gas reacting with the metal film together with the etching gas while etching the metal film by using the etching gas as the mask pattern. Forming a protective film on the side wall of the metal wiring of a uniform line width; forming a metal wiring of the semiconductor device comprising a. 제1항에 있어서, 상기 금속막으로 구리막을 적용하는 경우, 반응가스로 산소를 사용하는 것을 특징으로하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein oxygen is used as a reaction gas when a copper film is applied to the metal film. 제1항에 있어서, 상기 금속막으로 알루미늄막을 적용하는 경우, 반응가스로 CHF3를 사용하는 것을 특징으로하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein in the case of applying an aluminum film as the metal film, CHF 3 is used as a reaction gas. 제1항에 있어서, 상기 금속막으로 폴리실리콘막을 적용하는 경우, 반응가스로 산소 또는 암모늄을 사용하는 것을 특징으로하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein when a polysilicon film is used as the metal film, oxygen or ammonium is used as a reaction gas.
KR1019970030416A 1997-06-30 1997-06-30 Method of forming metal line of semiconductor device using protection layer KR100431317B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970030416A KR100431317B1 (en) 1997-06-30 1997-06-30 Method of forming metal line of semiconductor device using protection layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970030416A KR100431317B1 (en) 1997-06-30 1997-06-30 Method of forming metal line of semiconductor device using protection layer

Publications (2)

Publication Number Publication Date
KR19990006194A KR19990006194A (en) 1999-01-25
KR100431317B1 true KR100431317B1 (en) 2004-07-19

Family

ID=37335381

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970030416A KR100431317B1 (en) 1997-06-30 1997-06-30 Method of forming metal line of semiconductor device using protection layer

Country Status (1)

Country Link
KR (1) KR100431317B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950007065A (en) * 1993-08-18 1995-03-21 김주용 Metal wiring formation method of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950007065A (en) * 1993-08-18 1995-03-21 김주용 Metal wiring formation method of semiconductor device

Also Published As

Publication number Publication date
KR19990006194A (en) 1999-01-25

Similar Documents

Publication Publication Date Title
JP2860258B2 (en) Method of forming interconnect wiring
KR100272523B1 (en) Method for forming metallization of semiconductor device
KR20010023696A (en) Borderless vias with cvd barrier layer
KR20020010505A (en) Semiconductor device and manufacturing method thereof
KR900001654B1 (en) Semiconductor device manufacturing method
US6133142A (en) Lower metal feature profile with overhanging ARC layer to improve robustness of borderless vias
KR100338941B1 (en) Contact forming method for semiconductor device
KR20050006472A (en) Method of forming copper wiring in semiconductor device
KR100431317B1 (en) Method of forming metal line of semiconductor device using protection layer
KR100701673B1 (en) METHOD FOR FORMING Cu WIRING OF SENICONDUCTOR DEVICE
EP0256917B1 (en) Method of producing interconnection layers using cvd of metal
JP3308806B2 (en) Semiconductor device and manufacturing method thereof
KR100290786B1 (en) Metal wiring formation method of semiconductor device
KR100247643B1 (en) A reaction chamber for forming metal layer and method for forming metal layer in semiconductor device using the same
KR100324020B1 (en) Metal wiring formation method of semiconductor device
KR100713900B1 (en) Method for manufacturing metal line in semiconductor device
KR100383756B1 (en) Method of forming a metal wiring in a semiconductor device
KR100691935B1 (en) Method of forming a metal wiring in a semiconductor device
KR100250725B1 (en) Process for fabricating metal interconnector of semiconductor device
KR100230032B1 (en) Multilayer connector
KR100547242B1 (en) A method of forming intermetal dielectric layer for preventing void
KR100457408B1 (en) Method for forming tungsten plug of semiconductor device to improve reliability of semiconductor device
KR0168162B1 (en) Method of forming metal wire of semiconductor device
KR0167238B1 (en) Method of wiring line on a semiconductor device
KR100705400B1 (en) Method of performing electric wiring in semiconductor process

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee