KR960008525A - 캐시 열 타이밍 제어장치 - Google Patents
캐시 열 타이밍 제어장치 Download PDFInfo
- Publication number
- KR960008525A KR960008525A KR1019950025902A KR19950025902A KR960008525A KR 960008525 A KR960008525 A KR 960008525A KR 1019950025902 A KR1019950025902 A KR 1019950025902A KR 19950025902 A KR19950025902 A KR 19950025902A KR 960008525 A KR960008525 A KR 960008525A
- Authority
- KR
- South Korea
- Prior art keywords
- timing controls
- cache column
- column timing
- cache
- controls
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US29605894A | 1994-08-24 | 1994-08-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR960008525A true KR960008525A (ko) | 1996-03-22 |
Family
ID=23140431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950025902A KR960008525A (ko) | 1994-08-24 | 1995-08-22 | 캐시 열 타이밍 제어장치 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5680569A (ko) |
EP (1) | EP0698884A1 (ko) |
JP (1) | JPH08212779A (ko) |
KR (1) | KR960008525A (ko) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7089360B1 (en) | 2000-03-22 | 2006-08-08 | Intel Corporation | Shared cache wordline decoder for redundant and regular addresses |
US6507531B1 (en) | 2000-03-29 | 2003-01-14 | Intel Corporation | Cache column multiplexing using redundant form addresses |
KR100401509B1 (ko) * | 2001-05-31 | 2003-10-17 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 센스앰프 회로 |
US6707752B2 (en) | 2001-06-22 | 2004-03-16 | Intel Corporation | Tag design for cache access with redundant-form address |
US9997232B2 (en) | 2016-03-10 | 2018-06-12 | Micron Technology, Inc. | Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3942160A (en) * | 1974-06-03 | 1976-03-02 | Motorola, Inc. | Bit sense line speed-up circuit for MOS RAM |
JPS59203298A (ja) * | 1983-05-04 | 1984-11-17 | Nec Corp | 半導体メモリ |
US4807115A (en) * | 1983-10-07 | 1989-02-21 | Cornell Research Foundation, Inc. | Instruction issuing mechanism for processors with multiple functional units |
US4627032A (en) * | 1983-11-25 | 1986-12-02 | At&T Bell Laboratories | Glitch lockout circuit for memory array |
JPH0658631B2 (ja) * | 1983-12-19 | 1994-08-03 | 株式会社日立製作所 | デ−タ処理装置 |
JPS6142795A (ja) * | 1984-08-03 | 1986-03-01 | Toshiba Corp | 半導体記憶装置の行デコ−ダ系 |
US4899275A (en) * | 1985-02-22 | 1990-02-06 | Intergraph Corporation | Cache-MMU system |
JPS6246489A (ja) * | 1985-08-23 | 1987-02-28 | Nippon Texas Instr Kk | ダイナミツク型差動増幅器 |
US4943948A (en) * | 1986-06-05 | 1990-07-24 | Motorola, Inc. | Program check for a non-volatile memory |
US5226147A (en) * | 1987-11-06 | 1993-07-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device for simple cache system |
US5329489A (en) * | 1988-03-31 | 1994-07-12 | Texas Instruments Incorporated | DRAM having exclusively enabled column buffer blocks |
US5226126A (en) * | 1989-02-24 | 1993-07-06 | Nexgen Microsystems | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags |
JP2761515B2 (ja) * | 1989-03-08 | 1998-06-04 | 株式会社日立製作所 | 半導体記憶装置 |
US5136697A (en) * | 1989-06-06 | 1992-08-04 | Advanced Micro Devices, Inc. | System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache |
JPH0740247B2 (ja) * | 1989-06-20 | 1995-05-01 | 松下電器産業株式会社 | キャッシュメモリ装置 |
GB8923037D0 (en) * | 1989-10-12 | 1989-11-29 | Inmos Ltd | Timing control for a memory |
JPH03130989A (ja) * | 1989-10-17 | 1991-06-04 | Sanyo Electric Co Ltd | Dram |
JP2777247B2 (ja) * | 1990-01-16 | 1998-07-16 | 三菱電機株式会社 | 半導体記憶装置およびキャッシュシステム |
US5031141A (en) * | 1990-04-06 | 1991-07-09 | Intel Corporation | Apparatus for generating self-timing for on-chip cache |
GB2246001B (en) * | 1990-04-11 | 1994-06-15 | Digital Equipment Corp | Array architecture for high speed cache memory |
EP0461904A3 (en) * | 1990-06-14 | 1992-09-09 | Creative Integrated Systems, Inc. | An improved semiconductor read-only vlsi memory |
JPH0485788A (ja) * | 1990-07-27 | 1992-03-18 | Toshiba Corp | 多ポートキャッシュメモリ |
US5132931A (en) * | 1990-08-28 | 1992-07-21 | Analog Devices, Inc. | Sense enable timing circuit for a random access memory |
JP3181311B2 (ja) * | 1991-05-29 | 2001-07-03 | 株式会社東芝 | 半導体記憶装置 |
IT1253678B (it) * | 1991-07-31 | 1995-08-22 | St Microelectronics Srl | Architettura antirumore per memoria |
JPH05325569A (ja) * | 1992-05-27 | 1993-12-10 | Toshiba Corp | 半導体記憶装置 |
JP2823466B2 (ja) * | 1993-01-28 | 1998-11-11 | 株式会社東芝 | 半導体記憶装置 |
JPH06302189A (ja) * | 1993-02-22 | 1994-10-28 | Toshiba Corp | 半導体記憶装置 |
JP2606082B2 (ja) * | 1993-07-02 | 1997-04-30 | 日本電気株式会社 | 半導体集積回路 |
-
1995
- 1995-07-24 EP EP95305154A patent/EP0698884A1/en not_active Withdrawn
- 1995-08-22 KR KR1019950025902A patent/KR960008525A/ko not_active Application Discontinuation
- 1995-08-23 JP JP7214465A patent/JPH08212779A/ja not_active Withdrawn
- 1995-09-21 US US08/531,490 patent/US5680569A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0698884A1 (en) | 1996-02-28 |
JPH08212779A (ja) | 1996-08-20 |
US5680569A (en) | 1997-10-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69524193D1 (de) | Massagegerät | |
FI952093A0 (fi) | Kapsling foer med akustiska ytvaogefunktionerande byggelement | |
DE69514764D1 (de) | Massagegerät | |
KR960008525A (ko) | 캐시 열 타이밍 제어장치 | |
DE69634464D1 (de) | Cachespeicher | |
DE69516958D1 (de) | Zeitschaltungsanordnung | |
DE69634465D1 (de) | Cachespeicher | |
KR960013388U (ko) | 지압기 | |
KR970053540U (ko) | 침시술용 침관 | |
KR950024525U (ko) | 침관 | |
KR950032251U (ko) | 사우나용 찜질방 구조 | |
DE69406402D1 (de) | Zwischenspeicher | |
KR960009986U (ko) | 마사지기 | |
KR950026717U (ko) | 지압구 | |
KR970012149U (ko) | 지압발판 | |
KR950024520U (ko) | 지압기 | |
KR950024518U (ko) | 지압기 | |
KR960004051U (ko) | 침 시술기 | |
KR950024512U (ko) | 맛사지기 | |
KR940026655U (ko) | 텔리스코픽 컬럼의 길이 조절장치 | |
IT238698Y1 (it) | Segnalibro | |
KR960028522U (ko) | 책갈피 | |
KR960004048U (ko) | 지압겸 등긁게 | |
KR950028017U (ko) | 지압용 라이타 | |
KR960013385U (ko) | 경혈 자극구 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |