KR960006706B1 - Via contact manufacturing method - Google Patents

Via contact manufacturing method Download PDF

Info

Publication number
KR960006706B1
KR960006706B1 KR1019930004808A KR930004808A KR960006706B1 KR 960006706 B1 KR960006706 B1 KR 960006706B1 KR 1019930004808 A KR1019930004808 A KR 1019930004808A KR 930004808 A KR930004808 A KR 930004808A KR 960006706 B1 KR960006706 B1 KR 960006706B1
Authority
KR
South Korea
Prior art keywords
forming
titanium nitride
insulating layer
film
via contact
Prior art date
Application number
KR1019930004808A
Other languages
Korean (ko)
Other versions
KR940022706A (en
Inventor
최경근
Original Assignee
현대전자산업주식회사
김주용
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 현대전자산업주식회사, 김주용 filed Critical 현대전자산업주식회사
Priority to KR1019930004808A priority Critical patent/KR960006706B1/en
Publication of KR940022706A publication Critical patent/KR940022706A/en
Application granted granted Critical
Publication of KR960006706B1 publication Critical patent/KR960006706B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844Bottomless liners

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The method of forming a via contact includes the steps of forming an insulating layer(3,4,5) on a first conductive line(2), etching the predetermined portion of the insulating layer to form a via contact hole(6), forming a thin tungsten layer(11) on the insulating layer including the via contact hole through sputtering at a low temperature and forming a thin titanium nitride layer(12) thereon, blanket-etching the titanium nitride layer by a predetermined thickness to remove it placed on the bottom of the via contact hole to expose the tungsten layer, selectively depositing a CVD tungsten layer in the via contact hole to form a via plug(7), and forming a second conductive line(8) on the resulting structure.

Description

비아콘택 제조방법Via contact manufacturing method

제 1A도 내지 제 1C도는 종래기술에 의해 바아콘택 제조단계를 도시한 단면도.1A to 1C are cross-sectional views showing a bar contact manufacturing step according to the prior art.

제2A도 내지 제 2C도는 본 발명에 의해 비아콘택 제조단계를 도시한 단면도.2A to 2C are cross-sectional views showing a via contact manufacturing step according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 하부층 2 : 제 1금속배선1: lower layer 2: first metal wiring

3 : 제 1절연층 4 :지2절연층3: first insulating layer 4: ground 2 insulating layer

5 : 제 3절연층 6 : 비아홀(Via Hole)5: third insulating layer 6: via hole

7 : 비아플러그 8 : 제 2금속층7: Via plug 8: Second metal layer

11 : 스퍼터링 텅스텐막 12 : 티타늄 나이트라이드막.11: sputtering tungsten film 12: titanium nitride film.

본 발명은 고집적 반도체 소자의 제조방법에 관한 것으로, 특히 16메가급 이상의 디램(DRAM), 에스램(SRAM) 및 로직(Logic)공정에서 금속층과 금속층을 연결하는 비아콘택(Via Contact) 제조방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a method of manufacturing a via contact connecting a metal layer and a metal layer in a DRAM, SRAM, and logic process of 16 mega or more. It's about.

반도체 소자가 고집적화됨에 따라 비아홀의 에스팩트비(Aspect Ratio)가 커지고, 비아홀의 깊이가 서로다르게 되어 비아홀에 금속층을 증착할 경우 비아홀 저부에서 층덮힘의 불량으로 콘택불량이 발생된다.As the semiconductor devices are highly integrated, the aspect ratio of the via holes increases, and the depths of the via holes are different from each other. Therefore, when a metal layer is deposited in the via holes, contact failure occurs due to poor layer covering at the bottom of the via holes.

이러한 콘택불량을 개선하기 위하여 비아홀에 비아플러그를 형성한 다음 금속층을 형성하였다.In order to improve such contact defects, via plugs were formed in the via holes, and then metal layers were formed.

종래기술에 의해 비아플러그를 이용한 비아콘택을 제조하는 공정을 제 1A도 내지 제 1C도를 참조하여 설명하기로 한다.A process for manufacturing a via contact using a via plug according to the prior art will be described with reference to FIGS. 1A to 1C.

제 1A도는 하부절연층(1) 상부에 제1금속배선(2) 예를들어 알루미늄 금속배선을 형성하고, 전체면을 따라 얇은 제 1절연층(3)을 형성하고, 그 상부에 평탄화용 제 2절연층(4) 예를를어 SOG막 또는 IMO(Inter Metal Oxide)막을 형성하고, 그 상부에 제 3절연층(5)을 형성한 단면도이다.FIG. 1A shows a first metal wiring 2, for example, an aluminum metal wiring on the lower insulating layer 1, a thin first insulating layer 3 along the entire surface, and a planarizing agent thereon. 2 is a cross-sectional view in which an SOG film or an IMO (Inter Metal Oxide) film is formed, for example, and a third insulating layer 5 is formed thereon.

제 1B도는 제 1A도 공정후에 콘택마스크를 이용하여 제 2절연층(5)을 습식식각하고, 제 2 및 제 1절연층(4,3)을 건식식각하여 제 1급속배선(2)이 노출된 비아홀(6)을 형성한 단면도이다.FIG. 1B illustrates the wet etching of the second insulating layer 5 using the contact mask after the process of FIG. 1A, and the dry etching of the second and first insulating layers 4 and 3 to expose the first rapid wiring 2. It is sectional drawing which formed via hole 6.

제 1C도는 비아홀(6)에 노출된 제 1금속배선(2)에 CVD(Chemical Vapor Deposition) 텅스텐막을 선택적으로 증착시켜, 비아홀(6)에 비아플러그(7)를 형성한 다음, 제 2금속층(8)을 형성한 단면도이다.FIG. 1C illustrates a method of selectively depositing a chemical vapor deposition (CVD) tungsten film on the first metal wire 2 exposed to the via hole 6 to form a via plug 7 in the via hole 6, and then a second metal layer ( It is sectional drawing which formed 8).

그러나 상기의 알루미늄으로된 제 1금속배선 상부에 비아플러그로 CVD텅스텐막을 증착할 경우 CVD텅스텐막의 반응성 기체로 사용되는 WF6와 제 1금속배선이 반응하여 제 1금속배선과 비아플러그의 계면에 AlF₃등의 이물질이 형성되어 비아저항을 증가시키는 요인이 된다. 또한 CVD텅스텐막 증착공정은300∼500℃의 고온 공정이므로 제 2절연층으로 사용된 SOG막 또는 IMO막에서 H2O등의 이물질이 빠져나와 제 1금속배선과 비아플러그 계면에 존재하게 되어 비아저항을 증대시킨다.However, when the CVD tungsten film is deposited by via plug on the first metal wiring made of aluminum, WF6 and the first metal wiring, which are used as reactive gases of the CVD tungsten film, react with each other, such as AlF₃ at the interface between the first metal wiring and the via plug. Foreign matter is formed, which increases the via resistance. In addition, since the CVD tungsten film deposition process is a high temperature process of 300 to 500 ° C., foreign substances such as H 2 O are released from the SOG film or IMO film used as the second insulating layer and exist at the interface between the first metal wiring and the via plug. Increase resistance.

따라서, 본 발명은 상기한 바와같이 비아저항이 증대되는 요인을 제거하기 위하여 비아홀을 형성한 다음, 저온에서 스퍼터링 텅스텐을 비아홀에 노출된 면에 얇게 증착하고, 다시 비아홀 측벽에만 티타늄 나이트라이드막(TiN)을 형성한 후 선택적인 CVD텅스텐막을 증착하여 비아플러그를 제조하는 방법을 제공하는데 그 목적이 있다.Therefore, the present invention forms a via hole in order to eliminate the factor of increasing the via resistance as described above, and then sputtering tungsten is deposited thinly on the surface exposed to the via hole at low temperature, and again, a titanium nitride film (TiN) is formed only on the sidewall of the via hole. It is an object of the present invention to provide a method for manufacturing a via plug by depositing a selective CVD tungsten film after forming a).

이하에서 본 발명을 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

제 2A도 내지 제 2C도는 비아홀을 형성한 다음 본 발명에 의해 비아플러그와 비아콘택을 제조하는 단계를 도시한 단면도이다.2A through 2C are cross-sectional views illustrating a step of forming a via hole and then manufacturing a via plug and a via contact according to the present invention.

제2A도는 하부층(1) 상부에 제 1금속배선(2)을 형성하고, 제 1절연층(3), 제 2절연층(4) 및 제 3절연층(5)을 공지의 기술로 적층한 후(제 1A도 참조), 콘택마스크를 이용하여 예정된 콘택부분의 제 3절연층(5), 제 2절연층(4), 제 1절연층(3)을 순차적으로 습식 및 건식식각으로 식각하여 제 1금속배선(2)이 노출되는비아홀(6)을 공지의 기술로 형성하고(제 1B도 참조) 비아홀(6)과 제3절연층(15) 상부에 저온의 PVD (Physical Vapor Deposition)방법으로 스퍼터링 텅스텐막(11)을 얇은 두께 예를 들어 1000Å 정도 증착하고 그 상부에 PVD 방법으로 티타늄 나이트라이드막(12)을 얇은 두께 예를 들어 700Å 정도 증착한 단면도이다.2A shows a first metal wiring 2 formed on the lower layer 1, and the first insulating layer 3, the second insulating layer 4, and the third insulating layer 5 are laminated by a known technique. Afterwards (see FIG. 1A), the third insulating layer 5, the second insulating layer 4, and the first insulating layer 3 of the predetermined contact portion are sequentially etched by wet and dry etching using a contact mask. A via hole 6 through which the first metal wiring 2 is exposed is formed by a known technique (see FIG. 1B), and a low temperature PVD (Physical Vapor Deposition) method is formed on the via hole 6 and the third insulating layer 15. As a result, the sputtering tungsten film 11 is deposited in a thin thickness, for example, about 1000 mm, and the titanium nitride film 12 is deposited in a thin thickness, for example, about 700 mm by the PVD method.

제 2B도는 제 2A도 공정후, 비아홀(6)의 저부면에 증착된 티타늄 나이트라이드막(12)을 제거한 단면도로서, 티타늄 나이트라이드막(12)이 비아홀(6) 저부에 잘 증착되지 않는 점을 이용하여 RIE(Reactive Ion Etcher) 반응기에서 BC13와 C12 기체를 이용하여 약 400Å 두께의 티타늄 실리사이드막(12)을 전면 식각하여 비아홀(6) 저부의 스퍼터링 텅스텐막(11)이 노출된다.FIG. 2B is a cross-sectional view of the titanium nitride film 12 deposited on the bottom surface of the via hole 6 after the process of FIG. 2A, and the titanium nitride film 12 is hardly deposited on the bottom of the via hole 6. In the RIE (Reactive Ion Etcher) reactor by using the BC13 and C12 gas to etch the titanium silicide film 12 of about 400 Å thick and the sputtering tungsten film 11 of the bottom of the via hole 6 is exposed.

제 2C도는 비아홀(6) 상부에 LPCVD(Low Pressure Chemical Vapor Deposition) 반응기에서 WVF6,SiH₄, H2(또는 Ar)를 사용하여 스퍼터링 텅스텐막(1l) 상부에 CVD텅스텐막을 증착하여 비아플러그(7)를 형성한 다음, 제 2금속층(8)을 예를들어 알루미늄 PVD방법으로 8000Å 정도 증착한후 패턴을 형성한 단면도이다.FIG. 2C shows a via plug (7) by depositing a CVD tungsten film on the sputtered tungsten film (1l) using WVF 6 , SiH₄, H 2 (or Ar) in a low pressure chemical vapor deposition (LPCVD) reactor on the via hole 6. ), And then the second metal layer 8 is deposited by, for example, about 8000 Å by aluminum PVD, and then a pattern is formed.

상기한 본 발명에 의하면 비아플러그를 형성할때의 고온공정으로 인해 절연층에서 H2O와 같은 이물질이 발생되는 문제를 해결할 수 있다.According to the present invention described above it is possible to solve the problem that foreign matters such as H 2 O is generated in the insulating layer due to the high temperature process when forming the via plug.

또한, 비아플러그를 형성할때 사용되는 반응기체 예를들어 WF6와 제 1금속배선이 반응하여 제 1금속계면과 비아플러그 계면에 AlF₃막이 형성되는 것을 방지하여 비아저항이 저하된다.In addition, the reactant used in forming the via plug, for example, WF 6 and the first metal wiring react to prevent the formation of the AlF 3 film at the interface between the first metal interface and the via plug, thereby reducing the via resistance.

또한 비아홀에 스퍼터링 텅스텐막/티타늠 나이트라이드막/CVD텅스텐막의 3층 구조를 형성함으로써 비아콘택에서 EM, SM 특성을 향상시킬 수 있다.In addition, by forming a three-layer structure of a sputtered tungsten film / titanide nitride film / CVD tungsten film in the via hole, it is possible to improve the EM and SM characteristics in the via contact.

Claims (4)

비아콘택 제조방법에 있어서, 제 1도전층 배선 상부에 절연층을 형성하고, 절연층의 소정부분을 식각하여 제 1도전층 배선이 노출된 비아홀을 형성하는 공정과, 비아홀과 절연층 상부에 저온에서 스퍼터링 텅스텐막을 얇은 두께 형성하고, 그 상부에 티타늄 나이트라이드막을 얇은 두께로 형성하는 공정과, 상기의 티타늄 나이트라이드막의 예정두께를 전면식각 공정으로 식각하여 비아홀 저부의 티타늄 나이트라이드막을 제거하여 스퍼터링 텅스텐막이 노출되게 하는 공정과, 비아홀에 CVD텅스텐막을 선택적으로 증착하여 비아플러그를 형성하고, 전체구조 상부에 제 2금속층을 증착하는 공정을 포함하는 비아콘택 제조방법.A method of manufacturing a via contact, comprising: forming an insulating layer on an upper portion of a first conductive layer wiring, etching a predetermined portion of the insulating layer to form a via hole exposing the first conductive layer wiring; Forming a sputtered tungsten film at a thin thickness, forming a titanium nitride film at a thin thickness on top of the same, and etching a predetermined thickness of the titanium nitride film by an entire etching process to remove the titanium nitride film at the bottom of the via hole, thereby sputtering tungsten A method of manufacturing a via contact, comprising: exposing a film, and selectively depositing a CVD tungsten film in a via hole to form a via plug, and depositing a second metal layer over the entire structure. 제 1항에 있어서, 상기 스퍼터링 텅스텐막은 저온의 PVD방법으로 1000Å 정도의 두께로 증착하는 것을 특징으로 하는 비아콘택 제조방법.The method of claim 1, wherein the sputtering tungsten film is deposited to a thickness of about 1000 kW by a low temperature PVD method. 제 1항에 있어서, 상기 티타늄 나이트라이드막은 PVD방법으로 700Å 정도의 두께로 증착하는 것을 특징으로 하는 비아콘택 제조방법.The method of claim 1, wherein the titanium nitride film is deposited to a thickness of about 700 GPa by PVD. 제 1항에 있어서, 상기 티타늄 나이트라이드막의 400Å 정도의 두께를 전면식각하여 비아홀 저부의 스퍼터링 텅스텐막이 노출되게 하는 것을 특징으로 하는 비아콘택 제조방법.The method of claim 1, wherein the titanium nitride film is etched to about 400 Å in thickness to expose the sputtered tungsten film at the bottom of the via hole.
KR1019930004808A 1993-03-26 1993-03-26 Via contact manufacturing method KR960006706B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930004808A KR960006706B1 (en) 1993-03-26 1993-03-26 Via contact manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930004808A KR960006706B1 (en) 1993-03-26 1993-03-26 Via contact manufacturing method

Publications (2)

Publication Number Publication Date
KR940022706A KR940022706A (en) 1994-10-21
KR960006706B1 true KR960006706B1 (en) 1996-05-22

Family

ID=19352840

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930004808A KR960006706B1 (en) 1993-03-26 1993-03-26 Via contact manufacturing method

Country Status (1)

Country Link
KR (1) KR960006706B1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100399904B1 (en) * 1996-06-21 2003-12-24 주식회사 하이닉스반도체 Method for forming barrier metal film of semiconductor device
KR100445552B1 (en) * 2001-06-28 2004-08-21 동부전자 주식회사 Contact plug for a semiconductor device and method for fabricating the same
KR100526870B1 (en) * 2003-06-04 2005-11-09 삼성전자주식회사 Method for forming local interconnection line for use in semiconductor device

Also Published As

Publication number Publication date
KR940022706A (en) 1994-10-21

Similar Documents

Publication Publication Date Title
KR100278657B1 (en) Metal line structure for semiconductor device & manufacturing method thereof
US5281850A (en) Semiconductor device multilayer metal layer structure including conductive migration resistant layers
KR960006706B1 (en) Via contact manufacturing method
JPH05234935A (en) Semiconductor device and its manufacture
US5948705A (en) Method of forming interconnection line
US6787447B2 (en) Semiconductor processing methods of forming integrated circuitry
KR100307827B1 (en) Metal wiring contact formation method of semiconductor device
KR100451493B1 (en) Metal wiring formation method of semiconductor device
KR100640162B1 (en) A method for forming metal wire using difference of gas partial pressure in semiconductor device
KR100340860B1 (en) Method for fabricating contact plug of semiconductor device
KR100402242B1 (en) Method for manufacturing semiconductor device
KR100321141B1 (en) Method for fabricating semiconductor device
KR100470923B1 (en) Metal wiring formation method of semiconductor device
KR100324020B1 (en) Metal wiring formation method of semiconductor device
KR100252905B1 (en) Method for forming plug of semiconductor device
KR100252764B1 (en) Method for fabricating multi-layer metallization in semiconductor device
KR100256825B1 (en) Method of forming metal wiring in semiconductor device
KR100558034B1 (en) Method for forming semiconductor device capable of preventing plug loss during tungsten bit line formation process
KR20030043201A (en) Method for forming contact plug of semiconductor device
KR20020058430A (en) Method for fabricating a wire in semiconductor device
KR20020002602A (en) Method for forming bitline in semiconductor device
KR100457408B1 (en) Method for forming tungsten plug of semiconductor device to improve reliability of semiconductor device
KR0126102B1 (en) Insulating method of inter-metal layer in the semiconductor device
KR100458476B1 (en) Method for forming metal interconnection of semiconductor device to improve filling characteristic of metal thin film and avoid generation of void
KR100369483B1 (en) Method for forming metal wiring in semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110429

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee