KR960005997A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- KR960005997A KR960005997A KR1019940015916A KR19940015916A KR960005997A KR 960005997 A KR960005997 A KR 960005997A KR 1019940015916 A KR1019940015916 A KR 1019940015916A KR 19940015916 A KR19940015916 A KR 19940015916A KR 960005997 A KR960005997 A KR 960005997A
- Authority
- KR
- South Korea
- Prior art keywords
- transistor
- forming
- nitride film
- emitter
- layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000004065 semiconductor Substances 0.000 title claims abstract 10
- 238000000034 method Methods 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims abstract 7
- 239000000758 substrate Substances 0.000 claims abstract 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract 5
- 229920005591 polysilicon Polymers 0.000 claims abstract 5
- 238000005530 etching Methods 0.000 claims abstract 2
- 230000003647 oxidation Effects 0.000 claims abstract 2
- 238000007254 oxidation reaction Methods 0.000 claims abstract 2
- 230000001590 oxidative effect Effects 0.000 claims abstract 2
- 238000009792 diffusion process Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 230000005669 field effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
본 발명은 반도체장치 제조 방법에 관한 것으로, 좁은 에미터폭을 가지는 트랜지스터와 넓은 에미터폭을 가지는 트랜지스터와 넓은 에미터폭을 가지는 트랜지스터의 에미터 접합깊이를 동일하게 형성하기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, in which the emitter junction depths of a transistor having a narrow emitter width, a transistor having a wide emitter width, and a transistor having a wide emitter width are equally formed.
본 발명은 동일기판에 좁은 에미터폭을 가지는 트랜지스터와 넓은 에미터폭을 가지는 트랜지스터를 함께 형성하는 반도체 장치을 제조방법에 있어서, 반도체 기판상에 폴리실리콘층과 질화막을 차례로 형성하는 공정과, 상기 질화막을 선택적으로 식각하여 상기 각각의 트랜지스터의 에미터가 형성될 영역에만 남기는 공정, 국부산화공정에 의해 상기 폴리실리콘층을 선택적으로 산화시키는 공정, 상기 남아있는 질화막을 제거하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체장치의 제조방법을 제공함으로써 동일기판위에 좁은 에미터폭을 가지고 고속 바이폴라 트랜지스터와 넓은 에미터폭을 가지는 고전류 바이폴라 트랜지스터를 형성할 때 에미터 접합깊이를 일정하게 형성할 수 있으므로 스테틱 에미터 전류이득의 편차를 제거한다.The present invention provides a method of manufacturing a semiconductor device in which a transistor having a narrow emitter width and a transistor having a wide emitter width are formed together on a same substrate, the method comprising sequentially forming a polysilicon layer and a nitride film on the semiconductor substrate, and selectively selecting the nitride film. Etching to leave only the region where the emitter of each transistor is to be formed, selectively oxidizing the polysilicon layer by a local oxidation process, and removing the remaining nitride film. By providing a method of manufacturing a semiconductor device, the emitter junction depth can be uniformly formed when forming a high-speed bipolar transistor having a narrow emitter width and a high current bipolar transistor having a wide emitter width on the same substrate. Remove the deviation .
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제3도는 본 발명에 의한 바이폴라 트랜지스터 제조방법을 도시한 공정도이다.3 is a process chart showing a bipolar transistor manufacturing method according to the present invention.
제4도는 본 발명에 의한 접합형 전계효과 트랜지스터 단면 구조도이다.4 is a cross-sectional view of a junction field effect transistor according to the present invention.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940015916A KR0147407B1 (en) | 1994-07-04 | 1994-07-04 | Manufacturing method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940015916A KR0147407B1 (en) | 1994-07-04 | 1994-07-04 | Manufacturing method for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960005997A true KR960005997A (en) | 1996-02-23 |
| KR0147407B1 KR0147407B1 (en) | 1998-08-01 |
Family
ID=19387206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940015916A KR0147407B1 (en) | 1994-07-04 | 1994-07-04 | Manufacturing method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0147407B1 (en) |
-
1994
- 1994-07-04 KR KR1019940015916A patent/KR0147407B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR0147407B1 (en) | 1998-08-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050422 Year of fee payment: 8 |
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| LAPS | Lapse due to unpaid annual fee |