KR970054467A - Power MOS transistor and manufacturing method - Google Patents

Power MOS transistor and manufacturing method Download PDF

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KR970054467A
KR970054467A KR1019950055604A KR19950055604A KR970054467A KR 970054467 A KR970054467 A KR 970054467A KR 1019950055604 A KR1019950055604 A KR 1019950055604A KR 19950055604 A KR19950055604 A KR 19950055604A KR 970054467 A KR970054467 A KR 970054467A
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region
source
silicon substrate
high concentration
contact hole
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KR1019950055604A
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Korean (ko)
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KR100192953B1 (en
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김성한
박용포
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]

Abstract

기생 바이폴라 트랜지스터의 베이스저항을 감소시킬 수 있는 전력 모스트랜지스터 및 그 제조방법에 관하여 기재하고 있다. 이는, 고농도 불순물층 및 저농도 에피층이 적층되고, 액티브 셀 영역 및 게이트 콘택영역으로 구분된 실리콘 기판, 상기 저농도 불순물층 내에 형성된 고농도 및 저농도 베이스 영역, 상기 베이스영역 내의 실리콘 기판 표면에 형성된 소오스영역, 상기 실리콘 기판상에 형성된 게이트 도전층, 및 상기 소오스 영역과 소오스 콘택홀을 통해 접속되는 소오스전극을 구비하는 전력 모스트랜지스터에 있어서, 상기 소오스영역의 일부가 식각되어, 소오스 콘택홀이 실리콘 기판 표면보다 깊게 형성되고, 고농도 베이스영역이 상기 저농도 베이스영역 내에 형성되어 있는 것을 특징으로 한다. 따라서, 종래보다 기생 바이폴리 트랜지스터의 에미터-베이스 간의 저항값이 작기 때문에, 높은 드레인 전압에 의해 발생되는 항복전류에 대해 보다 안정적으로 동작할 수 있다.A power MOS transistor capable of reducing the base resistance of parasitic bipolar transistors and a method of manufacturing the same are described. A silicon substrate is formed by stacking a high concentration impurity layer and a low concentration epi layer, and is divided into an active cell region and a gate contact region, a high concentration and low concentration base region formed in the low concentration impurity layer, a source region formed on a surface of the silicon substrate in the base region, In a power MOS transistor having a gate conductive layer formed on the silicon substrate, and a source electrode connected to the source region through a source contact hole, a portion of the source region is etched so that a source contact hole is formed on the silicon substrate surface. It is formed deeply, characterized in that the high concentration base region is formed in the low concentration base region. Therefore, since the resistance value between the emitter and base of the parasitic bipoly transistor is smaller than before, it is possible to operate more stably against the breakdown current generated by the high drain voltage.

Description

전력 모스트랜지스터 및 그 제조방법Power MOS transistor and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 일 실시예에 따른 전력 모스트랜지스터의 액티브 셀 영역을 도시한 수직단면도.4 is a vertical sectional view showing an active cell region of a power MOS transistor according to an embodiment of the present invention.

Claims (8)

고농도 제1도전형의 불순물층 및 저넝도 제1도전형의 에피층이 적층되고 액티브 셀 영역 및 게이트 콘택영역으로 구분된 실리콘 기판; 상기 저농도 제1도전형의 불순물층 내에 형성되고, 제2도전형의 불순물층으로 이루어진 고농도 및 저농도 베이스영역; 상기 베이스영역 내의 실리콘 기판 표면에 형성되고, 고농도 제1도전형의 불순물층으로 이루어진 소오스 영역; 상기 실리콘 기판 상에 형성된 게이트 도전층; 및 상기 소오스영역과 소오스 콘택홀을 통해 접속되는 소오스전극을 구비하는 전력 모스트랜지스터에 있어서, 상기 소오스영역의 일부가 식각되어, 소오스 콘택홀이 실리콘 기판 표면보다 깊게 형성되고, 고농도 제2도전형의 베이스영역이 상기 저농도 제2도전형의 베이스영역 내에 형성되어 있는 것을 특징으로 하는 전력 모스트랜지스터.A silicon substrate in which a high concentration first impurity layer and a low conductivity first epitaxial layer are stacked and divided into an active cell region and a gate contact region; A high concentration and a low concentration base region formed in the low concentration first conductivity type impurity layer and comprising a second conductivity type impurity layer; A source region formed on the surface of the silicon substrate in the base region, the source region comprising an impurity layer of a high concentration first conductivity type; A gate conductive layer formed on the silicon substrate; And a source electrode connected to the source region through a source contact hole, wherein a portion of the source region is etched so that a source contact hole is formed deeper than a silicon substrate surface, and has a high concentration of the second conductive type. And a base region is formed in the low concentration second conductive base region. 제1항에 있어서, 상기 소오스 콘택홀이 상기 소오스영역이 접합면까지 식각되어 형성된 것을 특징으로 하는 전력 모스트랜지스터.The power MOS transistor of claim 1, wherein the source contact hole is formed by etching the source region to a junction surface. 제1항 또는 제2항에 있어서, 상기 고농도 베이스영역이 상기 저농도 베이스영역과 동일한 깊이로 확산되어 형성된 것을 특징으로 하는 전력 모스트랜지스터.The power MOS transistor according to claim 1 or 2, wherein the high concentration base region is diffused to the same depth as the low concentration base region. 제1항에 있어서, 게이트 도전층과 드레인영역과 단락을 방지하기 위해, 게이트 콘택 영역에 형성된 게이트 도전층과 실리콘 기판 사이에 필드산화막이 형성된 것을 특징으로 하는 전력 모스트랜지스터.2. The power MOS transistor according to claim 1, wherein a field oxide film is formed between the silicon substrate and the gate conductive layer formed in the gate contact region to prevent a short circuit between the gate conductive layer and the drain region. 고농도 제1도전형의 불순물층 및 저농도 제1도전형의 에피층이 형성되고 액티브 셀 영역 및 게이트 콘택영역으로 구분된 실리콘 기판의 게이트 콘택 영역에 선택적으로 필드산화막을 형성하는 제1단계; 필드산화막이 형성된 실리콘 기판 전면에 게이트산화막 및 게이트도전층을 형성하는 제2단계; 상기 제1도전형의 에피층 내에 저농도 제2도전형의 베이스 영역을 형성하는 제3단계; 상기 저농도 제2도전형의 베이스영역 내에 고농도 제1도전형의 소오스영역을 형성하는 제4단계; 소오스영역이 형성된 실리콘 기판 전면에 절연층을 형성한 다음, 상기절연층 및 소오스영역의 일부를 식각하여 액티브 셀 영역의 소오스콘택홀 및 게이트 콘택 영역의 게이트콘택홀을 형성하는 제5단계; 및 상기 소오스콘택홀 아래에 고농도 제2도전형의 베이스영역을 형성하는 제6단계를 구비하는 것을 특징으로 하는 전력 모스트랜지스터 제조방법.A first step of forming a field oxide film on a gate contact region of a silicon substrate formed of an impurity layer of a high concentration first conductivity type and an epitaxial layer of a low concentration first conductivity type and divided into an active cell region and a gate contact region; Forming a gate oxide film and a gate conductive layer on the entire silicon substrate on which the field oxide film is formed; A third step of forming a low concentration second conductive base region in the epitaxial layer of the first conductive type; A fourth step of forming a high concentration first conductivity type source region in the low concentration second conductivity type base region; Forming an insulating layer on the entire surface of the silicon substrate on which the source region is formed, and then etching the insulating layer and a portion of the source region to form a source contact hole in an active cell region and a gate contact hole in a gate contact region; And a sixth step of forming a high concentration second conductive base region under the source contact hole. 제5항에 있어서, 상기 소오스 콘택홀 형성시 상기 소오스영역의 접합면까지 식각하는 것을 특징으로 하는 전력 모스트랜지스터 제조방법.The method of claim 5, wherein the source contact hole is etched to form a junction surface of the source region when forming the source contact hole. 제5항 또는 제6항에 있어서, 상기 고농도 베이스영역 형성시 상기 고농도 베이스영역과 동일한 깊이로 확산시켜 형성하는 것을 특징으로 하는 전력 모스트랜지스터 제조방법.7. The method of claim 5 or 6, wherein forming the high concentration base region is formed by diffusing to the same depth as the high concentration base region. 제5항에 있어서, 상기 게이트 콘택홀 형성시 상기 절연층 및 게이트도전층을 함께 식각하는 것을 특징으로 하는 전력 모스트랜지스터 제조방법.The method of claim 5, wherein the insulating layer and the gate conductive layer are etched together when the gate contact hole is formed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950055604A 1995-12-23 1995-12-23 Power mos transistor and manufacturing method thereof KR100192953B1 (en)

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KR970054467A true KR970054467A (en) 1997-07-31
KR100192953B1 KR100192953B1 (en) 1999-06-15

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