KR960003195A

KR960003195A - Circuit to get digital correlation value

Info

Publication number: KR960003195A
Application number: KR1019940014471A
Authority: KR
Inventors: 이종성; 김용훈
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1994-06-23
Filing date: 1994-06-23
Publication date: 1996-01-26
Also published as: KR970005599B1

Abstract

본 발명은 디지탈 코릴레이션 값을 얻기 위한 회로를 공개한다. 그 회로는 n비트의 데이타를 7비트로 분리하여 입력하여 7비트내의 1의 갯수를 계수하고 그 계수된 값을 가산점으로 최종적인 1의 갯수를 발생하기 위한 디지탈 코릴레이션 값을 엇기 위한 회로에 있어서, 제1출력 비트신호를 발생하기 위한 배타 논리합게이트, 디코더, 기능 수행기, 및 제2, 제3출력신호 발생기로 구성되어 있다. 따라서, 클럭을 필요로 하지 않고 조합논리만으로 이루어져 게이트 지연시간에만 의존하여 코릴레이션 값이 계산되기 때문에 높은 속도의 코릴레이션값을 얻을 수 있다.The present invention discloses a circuit for obtaining a digital correlation value. In the circuit for inputting n bits of data separated into 7 bits, counting the number of 1s in 7 bits, and multiplying the digital correlation value for generating the final number of 1s by adding the counted values. And an exclusive logic sum gate for generating the first output bit signal, a decoder, a function performer, and second and third output signal generators. Therefore, since the correlation value is calculated only by the combinational logic without requiring a clock, and only the gate delay time, the correlation value of high speed can be obtained.

Description

Circuit to get digital correlation value

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 코릴레이션 값을 얻기 위한 회로의 블럭도이다.2 is a block diagram of a circuit for obtaining a correlation value of the present invention.

제3도는 제2도에 나타낸 블럭도의 회로도이다.3 is a circuit diagram of the block diagram shown in FIG.

제4도는 제3도에 나타낸 회로도의 동작 타이밍도이다.4 is an operation timing diagram of the circuit diagram shown in FIG.

Claims

A circuit for obtaining a digital correlation value for generating the final number of 1 by counting the number of 1s in 7 bits by inputting n bits of data separated into 7 bits and adding the counted values, wherein the 7 Exclusive OR means for exclusive ORing the signals of the bits to generate a first output bit signal; If the first, second, third, and fourth bit signals of the seven bits are the third, fifth, sixth, ninth, tenth, and twelfth signals, a first output signal is generated; The eleventh, thirteenth and fourteenth signals generate a second output signal; the zeroth signal generates a third output signal; the first, second, fourth, and eighth signals; Decoding means for generating a fifth output signal if the fifteenth signal; A function performing means and a decoding means for inputting the fifth, sixth, and seventh bit signals of the seven bits to output a signal performing the first, second, third, fourth, fifth, and sixth functions; Outputs a signal performing the first function in response to the third and fifth output signals of the output signal; outputs a signal performing the fourth function in response to the first output signal of the decoding means; Outputting a signal performing a fifth function in response to an output signal, outputting a signal performing a fifth function in response to a second output signal of the decoding means, and outputting a signal in response to a fourth output signal of the decoding means Outputting a signal performing six functions to output a second output bit signal of the first state when at least one of the four output signals is in the first state and in response to the second output signal of the decoding means; Outputting a signal performing the function, and the fourth of the decoding means Outputting a signal performing a second function in response to an output signal, outputting a signal performing the first function of the decoding means in response to a first output signal of the decoding means, and outputting three output signals and the decoding means And means for outputting a third output bit signal of the first state when at least one of the fifth output signals of the first output signal is in the first state.

2. The apparatus of claim 1, wherein the exclusive OR means comprises: a first XOR gate for exclusive ANDing the first and second bit signals; A second XOR gate for exclusive ORing the third and fourth bit signals; A third XOR gate for exclusive ORing the sixth and seventh bit signals; A fourth XOR gate for exclusive logical sum of the output signals of the first and second XOR gates, and a fifth XOR gate for exclusive logical sum of the output signals of the fifth bit signal and the fourth XOR gate; And a sixth XOR gate for exclusively ORing the output signals of the fourth and fifth XOR gates.

2. The apparatus of claim 1, wherein the decoding means comprises: a first AND gate for ANDing the first and second bit signals, and a first XOR gate for exclusively ORing the first and second bit signals; A first NOR gate for illogically combining the first and second bit signals; A second XOR gate for exclusively ORing the first and second bit signals, and a second NOR gate for illogically combining the third and fourth bit signals; A second AND gate for ANDing the fourth and fifth bit signals; A third AND gate for ANDing the output signal of the first NOR gabit and the second AND gate; A fourth AND gate for ANDing the output signal of the first AND gate and the second NOR gate; A fifth AND gate for ANDing the output signal of the first and second XOR gates; A sixth AND gate for ANDing the output signal of the first XOR gate and the second AND gate; A seventh AND gate for ANDing the output signal of the second XOR gate and the first AND gate; An eighth AND gate for generating the third output signal by performing an AND operation on the output signals of the first and second NOR gates; A ninth AND gate for ANDing the output signal of the first NOR gate and the second XOR gate; A tenth AND gate for ANDing the output signal of the first XOR gate and the second NOR gate; An eleventh AND gate for generating the fifth output signal by performing an AND operation on the output signals of the first and second AND gates; A tenth R gate for generating the first output signal by ORing the output signals of the third, fourth and fifth AND gates; A 20th R gate for generating the second output signal by ORing the output signals of the 6th and 7AND gates; And a thirtieth R gate for generating the fourth output signal by ORing the output signals of the eighth and ninth AND gates.

4. The apparatus of claim 3, further comprising: a twelfth AND gate for ANDing the fifth and sixth bit signals; A thirteenth AND gate for ANDing the fifth and seventh bit signals; A fourteenth AND gate for ANDing the sixth and seventh bit signals; A third NOR gate for illogically combining the fifth, sixth, and seventh bit signals; A fifteenth AND gate for generating a signal having a second function by performing an AND operation on the fifth, sixth, and seventh bit signals; A 40R gate for generating a signal performing a third function by ORing the fifth, sixth, and seventh bit signals; A 50R gate for generating a signal performing a first function by ORing the output signals of the first, second, and third AND gates; A sixty-R gate to generate a signal performing a fifth function by ORing the output signals of the NOR gate and the fourth AND gate; A first inverter for inverting an output signal of the 20th R gate to generate a signal having a fourth function; And a second inverter for inverting an output signal of the thirtieth gate to generate a signal having a sixth function, and obtaining a digital correlation value.

5. The apparatus of claim 4, wherein the means comprises: a seventy seventh R gate for performing an OR on the output signals of the eighth and eleventh AND gates; A sixteenth AND gate for ANDing the output signal of the fifth and sixty R gates, and a seventeenth AND gate for ANDing the output signal of the first and tenth R gates; An eighteenth AND gate for ANDing the output signal of the sixth and twenty R gates; A 19AND gate for ANDing the output signal of the second inverter and the 30th R gate; A 20th AND gate for ANDing the output signals of the fourth and 20R gates; A twenty-first AND gate for ANDing the output signal of the fifteenth AND gate and the thirtieth R gate; A 22nd AND gate for ANDing the output signal of the fifth and 10R gates; A gate for outputting a second output signal by ORing the output signals of the sixteenth, seventeenth, eighteenth, and nineteenth AND gates; And a 90 th R gate for outputting a third output signal by ORing the output signals of the 20 th, 21 th, 22 th, and 11 AND gates.

※ Note: The disclosure is based on the initial application.