KR930018853A

KR930018853A - Full adder

Info

Publication number: KR930018853A
Application number: KR1019920002792A
Authority: KR
Inventors: 김상수
Original assignee: 이헌조; 주식회사 금성사
Filing date: 1992-02-24
Publication date: 1993-09-22

Abstract

본 발명은 전 가산기(Full Adder)에 관한 것으로, 종래의 전가산기에 의하면 가산회로를 칩으로 구성할때 지연시간이 길어지게 되는 문제점을 해결하기 위한 것이다.The present invention relates to a full adder, and to solve the problem that the delay time becomes long when the adder circuit is configured as a chip according to the conventional full adder.

본 발명은 4비트의 전가산기로 8비트 이상의 전가산기를 구성하는 경우 상위비트와 하위비트를 여러개의 그룹을 구분하여 각 그룹단위의 데이타 입력과 출력비트에 대한 래치를 수행하고 그 래치결과를 쿨록단위로 연산처리토록 하므로서 고속의 연산이 가능한 것으로 가산기(감산기)에 적용한다.According to the present invention, when a full adder of 8 bits or more is composed of a full adder of 4 bits, the upper and lower bits are divided into groups to perform latches on data input and output bits of each group unit, and the latch result is coollocked. It can be applied to adder (subtracter) because it enables high speed operation by making calculation processing by unit.

Description

Full adder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발영의 16비트 전가산기의 회로도.3 is a circuit diagram of the 16-bit full adder of the present invention.

Claims

Four-bit full adder (1) (2) (3) (4), which adds in units of four bits, and the input data of the upper bit group are temporarily stored so that the full adder (1) (2) of the upper group is performed at the next clock timing. Input latch (21) (22) (23) (24) to be supplied to the < RTI ID = 0.0 > 1) < / RTI > The output latches 26 and 27 outputting the result of the calculation of the data at the next clock timing and the output data of the full adder 1 and 2 and the output latches 26 and 27 are outputted as the final calculation results. Full adder consisting of D flip-flop (5 to 20) output to Y 15.0)

※ Note: The disclosure is based on the initial application.