KR960002594A - Dummy pattern formation method to prevent breakage of the insulating film - Google Patents

Dummy pattern formation method to prevent breakage of the insulating film Download PDF

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Publication number
KR960002594A
KR960002594A KR1019940014826A KR19940014826A KR960002594A KR 960002594 A KR960002594 A KR 960002594A KR 1019940014826 A KR1019940014826 A KR 1019940014826A KR 19940014826 A KR19940014826 A KR 19940014826A KR 960002594 A KR960002594 A KR 960002594A
Authority
KR
South Korea
Prior art keywords
dummy pattern
insulating film
monitor box
cracks
etching
Prior art date
Application number
KR1019940014826A
Other languages
Korean (ko)
Other versions
KR0125307B1 (en
Inventor
손기근
홍상기
오세준
고재완
구영모
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940014826A priority Critical patent/KR0125307B1/en
Priority to CN95109141A priority patent/CN1049762C/en
Priority to JP7160717A priority patent/JP2686916B2/en
Publication of KR960002594A publication Critical patent/KR960002594A/en
Application granted granted Critical
Publication of KR0125307B1 publication Critical patent/KR0125307B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

본 발명은 절연막의 깨짐(crack)현상을 방지하기 위한 더미 패턴(dummy pattern) 형성방법에 관한 것으로, 반도체 소자 제조공정 중 절연 목적으로 형성되는 절연막에 콘택홀등을 형성하기 위해 식각할 때, 식각 정도를 알기 위해 스크라이브 라인(scribe line)상에 모니터 박스(monitor box)를 적용할 경우 후공정의 열공정에 의해 모니터 박스와 모시로부터 깨짐이 발생되어 이로 인한 절연막의 깨짐을 방지하기 위해 모니터 박스의 주변 및/또는 셀영역내의 주변회로부에 일정폭과 높이를 갖는 더미 패턴을 형성하여 모니터 박스의 모서리에 주로 발생되는 깨어짐이 절연막에 전파되지 않도록 한 더미 패턴을 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a dummy pattern for preventing cracking of an insulating film, and when etching to form a contact hole or the like in an insulating film formed for insulation purposes during a semiconductor device manufacturing process, etching is performed. In the case of applying the monitor box on the scribe line to know the degree, the cracks are generated from the monitor box and the ramie due to the thermal process of the post process, and thus the cracks of the insulating film are prevented. The present invention relates to a method of forming a dummy pattern in which a dummy pattern having a predetermined width and height is formed in a peripheral circuit portion in a periphery and / or a cell region so that cracks, which are mainly generated at edges of a monitor box, do not propagate to the insulating film.

Description

절연막의 깨짐현상을 방지하기 위한 더미 패턴 형성방법Dummy pattern formation method to prevent breakage of the insulating film

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 절연막 깨짐 방지를 위한 더미 패턴을 형성한 상태의 도면.3 is a view showing a state in which a dummy pattern for preventing an insulating film is broken according to the present invention.

Claims (3)

절연막의 식각정도를 알기 위한 모니터 박스에서 발생되는 깨짐 전파를 차단하여 절연막의 깨짐현상을 방지하기 위하여, 스크라이브 라인(3)내에 삽입되는 모니터 박스(4) 주변과 셀영역(1)의 주변회로(1A)에 모니터 박스(4)가 형성되기 이전의 도선 및 절연막 마스크, 식각공정시 더미 패턴(10, 20)을 각각 형성하는 것을 특징으로 하는 더미 패턴 형성방법.In order to block the crack propagation generated in the monitor box to know the etching degree of the insulating film to prevent the insulating film from being broken, the peripheral circuit around the monitor box 4 inserted in the scribe line 3 and the cell region 1 ( A dummy pattern forming method, characterized in that the conductive pattern before the monitor box (4) is formed in 1A), and the dummy pattern (10, 20) during the etching process are respectively formed. 제1항에 있어서, 상기 더미 패턴(10, 20) 각각은 그 폭이 2∼3㎛이고, 높이는 0.3∼0.7㎛로 형성되는 것을 특징으로 하는 더미 패턴 형성방법.The dummy pattern forming method according to claim 1, wherein each of the dummy patterns (10, 20) has a width of 2 to 3 mu m and a height of 0.3 to 0.7 mu m. 제1항에 있어서, 상기 더미 패턴(10)은 모니터 박스(4)와의 간격이 4∼7㎛인 위치에 형성되고, 상기 더미 패턴(20)은 가드 링(2)과 이 간격이 8∼12㎛인 위치에 형성되는 것을 특징으로 하는 더미 패턴 형성방법.The dummy pattern 10 is formed at a position where a distance from the monitor box 4 is 4 to 7 µm, and the dummy pattern 20 has a guard ring 2 and an interval of 8 to 12. The dummy pattern forming method characterized in that it is formed at a position that is μm. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940014826A 1994-06-27 1994-06-27 Dummy patterning method of semiconductor device KR0125307B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019940014826A KR0125307B1 (en) 1994-06-27 1994-06-27 Dummy patterning method of semiconductor device
CN95109141A CN1049762C (en) 1994-06-27 1995-06-27 Method of forming a dummy pattern to prevent the cracking of an insulation layer
JP7160717A JP2686916B2 (en) 1994-06-27 1995-06-27 Method of forming pseudo pattern for preventing breakdown of insulating film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940014826A KR0125307B1 (en) 1994-06-27 1994-06-27 Dummy patterning method of semiconductor device

Publications (2)

Publication Number Publication Date
KR960002594A true KR960002594A (en) 1996-01-26
KR0125307B1 KR0125307B1 (en) 1997-12-10

Family

ID=19386390

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940014826A KR0125307B1 (en) 1994-06-27 1994-06-27 Dummy patterning method of semiconductor device

Country Status (3)

Country Link
JP (1) JP2686916B2 (en)
KR (1) KR0125307B1 (en)
CN (1) CN1049762C (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100749252B1 (en) * 2005-11-28 2007-08-13 매그나칩 반도체 유한회사 Cmos image sensor

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650010B2 (en) 2002-02-15 2003-11-18 International Business Machines Corporation Unique feature design enabling structural integrity for advanced low K semiconductor chips
US7183137B2 (en) * 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Company Method for dicing semiconductor wafers
JP4861061B2 (en) * 2006-06-02 2012-01-25 株式会社ディスコ Method and apparatus for confirming annular reinforcing portion formed on outer periphery of wafer
KR20120129682A (en) 2011-05-20 2012-11-28 삼성전자주식회사 Semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613747A (en) * 1979-07-13 1981-02-10 Matsushita Electric Ind Co Ltd Semiconductor device
JPS62193263A (en) * 1986-02-20 1987-08-25 Fujitsu Ltd Resin-sealed semiconductor device
JPH03196521A (en) * 1989-12-25 1991-08-28 Nec Kansai Ltd Manufacture of semiconductor device
JPH0637064A (en) * 1992-07-16 1994-02-10 Fujitsu Ltd Dry etching method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100749252B1 (en) * 2005-11-28 2007-08-13 매그나칩 반도체 유한회사 Cmos image sensor

Also Published As

Publication number Publication date
JP2686916B2 (en) 1997-12-08
JPH08181127A (en) 1996-07-12
CN1049762C (en) 2000-02-23
CN1127934A (en) 1996-07-31
KR0125307B1 (en) 1997-12-10

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