KR19990002944A - Scribe lanes in semiconductor devices - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scribe lane of a semiconductor device, and more particularly, to a scribe lane of a semiconductor device that is suitable for preventing a clock occurring when cutting a wafer on a scribe lane. A first insulating layer and a BPSG layer formed on the first insulating layer, a first metal layer formed in a width of a scribe lane on the BPSG layer, and a second insulating layer formed with a via contact hole to expose a predetermined portion of the surface of the first metal layer; And a second metal layer formed on the second insulating layer including the via contact hole.

Description

Scribe lanes in semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scribe lane of a semiconductor device, and more particularly to a scribe lane of a semiconductor device that is suitable for preventing a clock occurring when cutting a wafer on the scribe lane.

In general, a scribe lane is an area without any units or circuits. It is an area where wafers are subjected to various tests and evaluations as the wafer passes through the process step because accuracy is required in a sawing area or a wafer process for dividing the wafer into individual chips.

Hereinafter, a scribe lane of a conventional semiconductor device will be described with reference to the accompanying drawings.

1 is a plan view of a scribe lane of a conventional semiconductor device, and FIG. 2 is a cross-sectional view of a scribe lane of a conventional semiconductor device.

As shown in FIG. 1, in order to improve the accuracy of the wafer process, the first insulating layer 3 is formed on the semiconductor substrate 1 on which a scribe lane 2 for wafer inspection is defined to improve the accuracy of the wafer process. And after the planarization BPSG layer 4 is formed in turn, the first metal layer mask pattern 5a is formed on the BPSG layer 4 including the scribe lane 2 so that the first metal layer 5 for wafer inspection is formed. do.

The second insulating layer 6 is formed on the entire surface including the first metal layer 5, and the second insulating layer 6 is selectively removed so that the surface of the first metal layer 5 is partially exposed. The via contact hole mask pattern 7a is formed to form the contact hole 7.

Subsequently, a second metal layer mask pattern 8a is formed on the second insulating layer 6 including the via contact hole 7a so that the second metal layer 8 for wafer inspection is formed to be connected to the first metal layer 5. Is formed.

As shown in FIG. 2, in the wafer process, the first insulating layer 3 and the planarization layer are formed on the semiconductor substrate 1 on which the scribe lanes 2 for wafer inspection are defined to improve the accuracy of the wafer process. A BPSG layer 4 is formed in turn, and a first metal layer 5 for wafer inspection is optionally formed on the BPSG layer 4. At this time, an oxide film is used for the first insulating layer 3.

After the second insulating layer 6 having the via contact hole is formed on the BPSG layer 4 including the first metal layer 5 to expose a predetermined portion of the surface of the first metal layer 5, the via contact hole is formed. The second metal layer 8 is formed on the second insulating layer 6 including the first metal layer 4 to be connected to the first metal layer 4. At this time, the second insulating layer 6 uses an oxide film, and the second metal layer 8 is for wafer inspection during the wafer process.

On the other hand, a gap occurs at the interface 9 of the BPSG layer 4 and the first metal layer 5 when cutting the wafer in the stripe lane.

However, the scribe lane of the conventional semiconductor device has the following problems.

In a scribe lane having a structure in which a BPSG layer and a metal layer are connected, a gap occurs between an interface between the metal layer remaining after the wafer cutting and the BPSG layer. As a result, in the chip's reliability test, a gap between the BPSG layer and the metal layer interface is caused, causing a clock inside the chip.

An object of the present invention is to provide a scribe lane of a semiconductor device suitable for improving a clock phenomenon generated during wafer etching by forming a metal layer connected to a BPSG layer in the scribe lane.

1 is a plan view showing a scribe lane of a conventional semiconductor device

2 is a cross-sectional view showing a scribe lane of a conventional semiconductor device.

3 is a plan view showing a scribe lane of the semiconductor device of the present invention.

4 is a cross-sectional view showing a scribe lane of the semiconductor device of the present invention.

Explanation of symbols for main parts of the drawings

30 semiconductor substrate 31 scribe lane

32: first insulating layer 33: BPSG layer

34: First Metal Layer 34a: First Metal Layer Mask Pattern

35: second insulating layer 36: via contact hole

36a: via contact hole mask pattern 37: second metal layer

37a: second metal layer mask pattern

The scribe lane of the semiconductor device of the present invention for achieving the above object is a semiconductor substrate having a scribe lane defined, the first insulating layer and the BPSG layer formed on the semiconductor substrate, and the scribe lane width on the BPSG layer A first metal layer formed therein, a second insulating layer formed with via contact holes to expose a predetermined portion of the surface of the first metal layer, and a second metal layer formed on a second insulating layer including the via contact holes. Characterized in that configured.

Hereinafter, the scribe lane of the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view showing a scribe lane of the semiconductor device of the present invention, Figure 4 is a cross-sectional view showing a scribe lane of the semiconductor device of the present invention.

As shown in FIG. 3, a first insulating layer 32 is formed on a semiconductor substrate 30 on which a scribe lane 31 for wafer inspection is defined in order to improve the accuracy of the wafer process. And after the planarization BPSG layer 33 is formed in turn, a first metal layer mask pattern 34a is formed on the BPSG layer 33 on the scribe lane 31 so that the first metal layer 34 for wafer inspection is formed. . In this case, the width of the scribe lane 31 is 70 ± 5㎛, the width of the first metal layer mask pattern 34a is about 50㎛ maximum considering the margin of the scribe lane 31 and the margin # 10㎛.

The second insulating layer 35 is formed on the entire surface including the first metal layer 34, and the second insulating layer 35 is selectively removed so that the surface of the first metal layer 34 is partially exposed. The via contact hole mask pattern 36a is formed to form the contact hole 36.

Subsequently, a second metal layer mask pattern 37a is formed on the second insulating layer 35 including the via contact hole 36 so that the second metal layer 37 for wafer inspection is formed to be connected to the first metal layer 34. Is formed.

As shown in FIG. 4, in order to improve the accuracy of the wafer process, the first insulating layer 32 and the planarization BPSG layer (on the semiconductor substrate 30 having the scribe lanes for wafer inspection are defined in order to improve the accuracy of the wafer process). 33) are formed in turn, and a first metal layer 34 for wafer inspection is selectively formed on the BPSG layer 33 on the stripe lane 31. In this case, an oxide film is used for the first insulating layer 32.

After the second insulating layer 35 having the via contact hole is formed on the BPSG layer 33 including the first metal layer 34 to expose a predetermined portion of the surface of the first metal layer 34, the via contact hole is formed. The second metal layer 37 is formed on the second insulating layer 35 including the first metal layer 34. In this case, the second insulating layer 35 uses an oxide film, and the second metal layer 37 is for wafer inspection during a wafer process.

As described above, the scribe lane of the semiconductor device of the present invention has the following effects.

Since the metal layer connected to the BPSG layer is formed only on the scribe lane so that the metal layer disappears after cutting the wafer, there is no gap at the interface with the layer connected to the BPSG layer.

Therefore, in a later process, the clock generation phenomenon inside the chip is completely eliminated during the chip reliability test.

Claims (3)

A semiconductor substrate in which a scribe lane is defined, A first insulating layer and a BPSG layer formed on the semiconductor substrate; A first metal layer formed in a width of a scribe lane on the BPSG layer; A second insulating layer having a via contact hole to expose a predetermined portion of the surface of the first metal layer; And a second metal layer formed on the second insulating layer including the via contact hole. The method of claim 1, The scribe lane width of the semiconductor device characterized in that the width of 70 ± 5㎛ The method of claim 1, The width of the first metal layer is a scribe lane of the semiconductor device, characterized in that up to 50㎛.