KR980005965A - Vernier and Patterning Method for Pattern Monitoring in Semiconductor Device Manufacturing - Google Patents

Vernier and Patterning Method for Pattern Monitoring in Semiconductor Device Manufacturing Download PDF

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Publication number
KR980005965A
KR980005965A KR1019960023646A KR19960023646A KR980005965A KR 980005965 A KR980005965 A KR 980005965A KR 1019960023646 A KR1019960023646 A KR 1019960023646A KR 19960023646 A KR19960023646 A KR 19960023646A KR 980005965 A KR980005965 A KR 980005965A
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South Korea
Prior art keywords
vernier
semiconductor device
width
region
length
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KR1019960023646A
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Korean (ko)
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KR100248793B1 (en
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마상훈
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김주용
현대전자산업 주식회사
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Priority to KR1019960023646A priority Critical patent/KR100248793B1/en
Publication of KR980005965A publication Critical patent/KR980005965A/en
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Publication of KR100248793B1 publication Critical patent/KR100248793B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체장치 제조공정중 마스크 형성단계에서 식각전후의 패턴의 상태 및 일정 바이어스상태를 확인하기 위한 버어니어에 관한 것으로, 반도체소자가 형성된 웨이퍼의 필드 중앙부의 스크라이브 라인상에 소정의 박스 구조의 형태로 형성된 반도체장치 제조시 패턴 모니터링을 위한 버어니어를 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vernier for checking a pattern state and a predetermined bias state before and after etching in a mask forming step of a semiconductor device manufacturing process. To provide a vernier for pattern monitoring in manufacturing a semiconductor device formed in a shape.

Description

반도체장치 제조시의 패턴 모니터링을 위한 버어니어 및 이의 형성방법Vernier and Patterning Method for Pattern Monitoring in Semiconductor Device Manufacturing

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 일실시예에 의한 반도체장치제조시의 패턴 모니터링을 위한 버어니어구조를 도시한 평면도이다.1 is a plan view showing a vernier structure for pattern monitoring in manufacturing a semiconductor device according to an embodiment of the present invention.

Claims (5)

반도체소자가 형성된 웨이퍼의 필드 중앙부의 스크라이브 라인상에 소정의 박스구조의 형태로 형성된 것을 특징으로 하는 반도체장치 제조시의 패턴 모니터링을 위한 버어니어.A vernier for pattern monitoring in manufacturing a semiconductor device, characterized in that it is formed in a predetermined box structure on a scribe line in a field center portion of a wafer on which a semiconductor element is formed. 제1항에 있어서, 상기 박스구조는 폭 10㎛, 길이 14㎛의 형태를 갖는 것을 특징으로 하는 반도체장치 제조시의 패턴 모니터링을 위한 버어니어.The vernier of claim 1, wherein the box structure has a shape of 10 μm in width and 14 μm in length. 제1항에 있어서, 상기 버어니어는 각기 폭과 길이가 다른 다수개의 버어니어패턴으로 이루어진 것을 특징으로 하는 반도체장치 제조시의 패턴 모니터링을 위한 버어니어.The vernier of claim 1, wherein the vernier comprises a plurality of vernier patterns having different widths and lengths, respectively. 제3항에 있어서, 상기 버어니어는 폭 0.005㎛, 길이 2㎛의 제1영역과, 상기 제1영역의 상부와 하부에 각각 연결된 폭 1.0㎛, 길이 2㎛의 제2영역, 상기 제2영역의 상부와 하부에 각각 연결된 폭 1.5㎛, 길이 2㎛의 제3영역 및 상기 제1, 제2 및 제3영역으로 이루어진 패턴의 양측에 소정거리만큼 이격되어 형성된 폭 2㎛, 길이 14㎛의 제4영역으로 이루어진 것을 특징으로 하는 반도체장치 제조시의 패턴 모니터링을 위한 버어니어.The vernier of claim 3, wherein the vernier has a first region having a width of 0.005 μm and a length of 2 μm, a second region having a width of 1.0 μm and a length of 2 μm, respectively, connected to an upper portion and a lower portion of the first region. A third region having a width of 1.5 μm and a length of 2 μm connected to the upper and lower portions of the second region and a width of 2 μm and a length of 14 μm spaced apart by a predetermined distance on both sides of the pattern consisting of the first, second and third regions, respectively. Vernier for pattern monitoring in the manufacture of semiconductor devices comprising four areas. 반도체장치 제조공정중 마스크패턴 형성시 반도체소자가 형성된 웨이퍼의 필드 중앙부의 스크라이브 라인상에 소정의 박스구조 형태를 갖는 버어니어를 함께 형성하는 것을 특징으로 하는 반도체장치 제조의 패턴 모니터링을 위한 버어니어 형성방법.When forming a mask pattern during a semiconductor device manufacturing process, forming a vernier for pattern monitoring in semiconductor device manufacturing, wherein a vernier having a predetermined box structure is formed together on a scribe line in a field center of a wafer on which a semiconductor device is formed. Way. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960023646A 1996-06-25 1996-06-25 Vernier for pattern monitoring KR100248793B1 (en)

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Application Number Priority Date Filing Date Title
KR1019960023646A KR100248793B1 (en) 1996-06-25 1996-06-25 Vernier for pattern monitoring

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Application Number Priority Date Filing Date Title
KR1019960023646A KR100248793B1 (en) 1996-06-25 1996-06-25 Vernier for pattern monitoring

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KR980005965A true KR980005965A (en) 1998-03-30
KR100248793B1 KR100248793B1 (en) 2000-03-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100441324B1 (en) * 2000-03-17 2004-07-23 인피니언 테크놀로지스 아게 Method for fabricating and checking structures of electronic circuits in a semiconductor substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950027935A (en) * 1994-03-22 1995-10-18 김주용 Photomask Manufacturing Method to Improve Overlay Margin

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100441324B1 (en) * 2000-03-17 2004-07-23 인피니언 테크놀로지스 아게 Method for fabricating and checking structures of electronic circuits in a semiconductor substrate

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