KR960001466Y1 - Chip magnification rate of exposure device - Google Patents
Chip magnification rate of exposure device Download PDFInfo
- Publication number
- KR960001466Y1 KR960001466Y1 KR92019967U KR920019967U KR960001466Y1 KR 960001466 Y1 KR960001466 Y1 KR 960001466Y1 KR 92019967 U KR92019967 U KR 92019967U KR 920019967 U KR920019967 U KR 920019967U KR 960001466 Y1 KR960001466 Y1 KR 960001466Y1
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- Prior art keywords
- alignment
- wafer
- chip
- pattern
- exposure apparatus
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
내용 없음.No content.
Description
제 1 도는 종래의 웨이퍼 정렬을 설명하기 위한 동작 흐름도1 is an operation flowchart for explaining a conventional wafer alignment.
제 2 도는 제 1 도에 따른 웨이퍼 정렬을 설명하기 위한 정렬 패턴을 나타낸 평면도2 is a plan view showing an alignment pattern for explaining wafer alignment according to FIG.
제 3 도는 본 고안의 웨이퍼 정렬 및 칩 확대를 설명하기 위한 동작 흐름도3 is an operation flowchart for explaining wafer alignment and chip enlargement of the present invention.
제 4 도는 제 3 도에 따른 웨이퍼 정렬 및 칩 확대를 설명하기 위한 정렬 패턴을 나타낸 평면도4 is a plan view showing an alignment pattern for explaining wafer alignment and chip enlargement according to FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : X 방향 웨이퍼 정렬을 하기 위한 정렬 패턴1: Alignment pattern for X direction wafer alignment
2 : Y 방향 웨이퍼 정렬을 하기 위한 정렬 패턴2: alignment pattern for Y-direction wafer alignment
3 : 메모리 셀 4 : 1회에 노광할 수 있는 지역3: memory cell 4: area where light can be exposed at one time
5 : X 방향 칩 확대 측정을 하기 의한 정렬 패턴5: Alignment pattern by measuring chip enlargement in X direction
6 : Y 방향 칩 확대 측정을 하기 위한 정렬 패턴6: Alignment pattern for chip enlargement measurement in Y direction
본 고안은 노광 장치의 칩 확대율(Chip Magnification Rate) 보정에 관한 것으로, 특히 노광 장치에서 웨이퍼(Wafer) 정렬시 칩 확대율을 자동 측정하여 칩 확대율을 자동 보정할 수 있는 노광 장치의 칩 확대율보정 패턴(Pattern)에 관한 것이다.The present invention relates to the correction of the chip magnification rate of the exposure apparatus. In particular, the chip magnification correction pattern of the exposure apparatus capable of automatically correcting the chip magnification ratio by automatically measuring the chip magnification ratio when the wafer is aligned in the exposure apparatus ( Pattern).
종래의 기술은 제 1 도와 같이 노광기에서 웨이퍼 정렬이 끝난 후 예비 정렬도를 보정하여 미세 정렬을 하고, 노광 장치 자체에서 제 2 도와 같이 X, Y 방향 웨이퍼 정렬을 하기 위한 정렬 패턴(1, 2)에 의해 정렬된 메모리셀(Memory Cell)로 이루어진 1회 노광할 수 있는 지역(4)의 정렬 상태를 검사한 후 웨이퍼의 확대(Scale), 회전 정도(Orthogonality)등의 정렬 상태를 자동 보정한후 노광한다.(S1-S4).The conventional technique is to finely align the preliminary degree of alignment after the wafer alignment is completed in the exposure apparatus as in the first diagram, and the alignment patterns (1 and 2) for the wafer alignment in the X and Y directions as the second diagram in the exposure apparatus itself. After checking the alignment state of the once-exposed area (4) made up of memory cells aligned by, automatically correct the alignment state such as the scale of the wafer and the degree of rotation (Orthogonality) It exposes. (S1-S4).
다음, 현상 장비로 현상을 하며 정렬도 측정 장비로 정렬도를 검사하여 웨이퍼 정렬 상태를 보정하고, 이에따른 축소열 보정값을 입력하여 나머지 웨이퍼 전부를 노광한다.(S5-S7).Next, development is carried out with a developing device, and the alignment degree is checked with the alignment degree measuring device to correct the wafer alignment state, and the reduced heat correction value is input accordingly to expose all the remaining wafers (S5-S7).
예를들어, 예비 정렬 패턴을 이용하여 웨이퍼 내의 두 지점 또는 세지점등 임의의 지점을 지정하여 웨이퍼의 예비 정렬을 실시하고, 상기 지정된 지점의 X, Y 좌표를 측정하여 웨이퍼의 회전 정도를 보정한 후 예비 정렬이 끝난 웨이퍼를 제 2 도의 정렬 패턴(1, 2)을 이용하여 웨이퍼 내 8-12지점의 좌표값을 측정함으로써 그 좌표값을 계산하여 웨이퍼의 확대 등을 보정하고, 노광한다.For example, by using a preliminary alignment pattern, the wafer may be pre-aligned by specifying an arbitrary point such as two points or three points in the wafer, and the X and Y coordinates of the designated points may be measured to correct the degree of rotation of the wafer. Thereafter, the pre-aligned wafer is measured using the alignment patterns 1 and 2 of FIG. 2 to measure the coordinate values of 8-12 points in the wafer to calculate the coordinate values, to correct the enlargement of the wafer, and to expose the wafer.
그러나, 이와 같은 종래의 기술에 있어서는 1회에 노광할 수 있는 지역(4)의 좌표값만 알 수 있을뿐, 칩 확대율, 측정을 위한 정렬 페턴이 없기 때문에 칩 확대율 보정은 이루어지지 않는다However, in such a conventional technique, only the coordinate values of the area 4 which can be exposed at a time can be known. Since there is no chip magnification and an alignment pattern for measurement, chip magnification correction is not made.
본 고안은 이와 같은 종래의 결점을 감안하여 안출한 것으로, 1회에 노광할 수 있는 지역에 칩 확대율 및 축소율 보정을 위한 패턴을 형성하여 노광 장치 자체에서 칩 확대율을 보정할 수 있는 노광 장치의 칩 확대율 보정 패턴을 제공하는네 그 목적이 있다.The present invention has been devised in view of the above-described drawbacks, and the chip of the exposure apparatus capable of correcting the chip enlargement ratio in the exposure apparatus itself by forming a pattern for correcting the chip enlargement ratio and reduction ratio in an area that can be exposed at one time. Its purpose is to provide an enlargement correction pattern.
이하에서 이와 같은 목적을 달성하기 위한 본 고안의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, described in detail by the accompanying drawings an embodiment of the present invention for achieving the above object.
제 3 도는 본 고안의 동작 흐름도로, 노광 장치에서 웨이퍼의 예비 정렬이 끝난 후 예비 정렬도를 보정하여 미세 정렬을 하는 것은 종래와 같으며 제 4 도의 메모리 셀(3)의 각 일측에 형성된 X, Y 방향 웨이퍼 정렬을 하기위한 종래와 같은 정렬 패턴(1)(2)에 메모리 셀(3) 모서리릍 사이에 두며 각각 직각으로 형성한 X, Y 방향칩 확대 측정을 하기 위한 정렬 괘턴(5)(6)을 이용하여 노광기 자체에서 정렬 상태를 검사한 후 웨이퍼의 확대, 회전 정도, 칩 확대율 등의 정렬 상태를 자동 보정한다.(S1-S3)3 is an operation flowchart of the present invention, in which the fine alignment is performed by correcting the preliminary alignment after the preliminary alignment of the wafer is completed in the exposure apparatus, and X formed on each side of the memory cell 3 of FIG. Alignment ruler (5) for X and Y direction chip magnification measurements formed at right angles to each other between the edges of the memory cells 3 in the conventional alignment pattern (1) (2) for Y-direction wafer alignment. 6), the alignment state is inspected by the exposure machine itself, and then the alignment state such as the enlargement of the wafer, the degree of rotation, and the chip enlargement ratio is automatically corrected (S1-S3).
다음, 노광을 하며 현상 장비로 현상한 후 정렬도 측정 장비로 정렬도를 검사한다.(S4-S6)Next, the exposure is developed with a developing device, and then the alignment degree is checked with an alignment measuring device. (S4-S6)
단, 상기 도면중 설명되지 않은 4번은 1회에 노광할 수 있는 지역이다.However, 4 which is not described in the said drawing is an area | region which can be exposed at once.
예를들어, 예비 정렬 패턴을 이용하여 웨이퍼 내에서 임의의 두 지점을 웨이퍼 예비 정렬을 실시하고, 그 두지점의 좌표를 측정하여 웨이퍼의 회전 강도를 보정한 후 예비 정렬이 끝난 웨이퍼를 제 4 도의 정렬 패턴(l)(2)(5)(6)을 이용하여 웨이퍼 내 8-12 지점의 좌표값을 측정함으로써 좌표값을 계산하여 웨이퍼의 확대, 칩 확대율 등을 자동 보정한 후 노광한다.For example, using a preliminary alignment pattern, the wafers are pre-aligned at any two points, the coordinates of the two points are measured to correct the rotational strength of the wafer, and the pre-aligned wafer is shown in FIG. Coordinate values are calculated by measuring the coordinate values of 8-12 points in the wafer using the alignment patterns (l) (2) (5) (6), and are automatically corrected for exposure of the wafer enlargement, chip enlargement ratio, and the like.
그리고, 본 고안의 칩 확대율은 다음꽈 같이 계산한다.And, the chip expansion ratio of the present invention is calculated as follows.
X좌표의 칩 확대율 S1은,Chip magnification S1 of X coordinate is
S1 = (두번째 지점 X좌표 - 첫번째 지점 X좌표)/(설계치의 두번째 지점 X좌표 - 설계치의 첫번째 지점 X좌표).S1 = (second point X coordinate-first point X coordinate) / (second point X coordinate of design value-first point X coordinate of design value).
그리고, Y좌표의 칩 확대율 S2는,And chip enlargement ratio S2 of Y coordinate is
S2 = (두번째 지점 Y좌표 - 첫번째 지점 Y좌표)/(설계치의 두번째 지점 Y좌표 - 설계치의 첫번째 지점 Y좌표).S2 = (second point Y coordinate-first point Y coordinate) / (second point Y coordinate of design value-first point Y coordinate of design value).
와 같이 계산된다.Is calculated as
따라서, 칩 확대율 S는,Therefore, the chip magnification S is
S = (S1 + S2)/2 이다.S = (S1 + S2) / 2.
이상에서 설명한 바와 같이 본 고안은 제 4 도와 같은 칩 확대율 및 축소율 보정을 위한 정렬 패턴(5)(6)을 형성함으로써 노광기 자체에서 칩 확대율을 보정할 수 있는 효과가 있다.As described above, the present invention has the effect of correcting the chip enlargement ratio in the exposure apparatus itself by forming the alignment patterns 5 and 6 for correcting the chip enlargement ratio and reduction ratio as shown in FIG.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92019967U KR960001466Y1 (en) | 1992-10-16 | 1992-10-16 | Chip magnification rate of exposure device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92019967U KR960001466Y1 (en) | 1992-10-16 | 1992-10-16 | Chip magnification rate of exposure device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940011107U KR940011107U (en) | 1994-05-27 |
| KR960001466Y1 true KR960001466Y1 (en) | 1996-02-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR92019967U KR960001466Y1 (en) | 1992-10-16 | 1992-10-16 | Chip magnification rate of exposure device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100298193B1 (en) * | 1998-06-16 | 2001-11-15 | 박종섭 | Reticle for leveling alignement of wafer |
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| KR940011107U (en) | 1994-05-27 |
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