JPS6030136A - Forming method of pattern - Google Patents
Forming method of patternInfo
- Publication number
- JPS6030136A JPS6030136A JP58138304A JP13830483A JPS6030136A JP S6030136 A JPS6030136 A JP S6030136A JP 58138304 A JP58138304 A JP 58138304A JP 13830483 A JP13830483 A JP 13830483A JP S6030136 A JPS6030136 A JP S6030136A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- main
- auxiliary
- main pattern
- auxiliary pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 5
- 230000007261 regionalization Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 9
- 230000000873 masking effect Effects 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 4
- 238000005259 measurement Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、縮小投影総光装置によるパターンの形成方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming a pattern using a reduction projection total light device.
従来、縮小投影ｉＩＩ元装置を用いてウェハにパターン
を露光する際、主パターン内に相対位置精度マーカーを
配置し、主パターンの霧光後、ウェハ全面に形成された
数ケ所の相対位置精度マーカーを検出して精度評価を行
っている。なお、この評価に除しては、ウェハの各チッ
プのリピートｓ度を得るために、全チップの相対位置精
度のマーカを全て測定しなければならない。Conventionally, when exposing a pattern on a wafer using a reduction projection III source device, relative position accuracy markers are placed within the main pattern, and after the main pattern is mist-lighted, relative position accuracy markers are placed at several locations on the entire surface of the wafer. is detected and evaluated for accuracy. Note that for this evaluation, in order to obtain the repeat degree of each chip on the wafer, all markers of relative position accuracy of all chips must be measured.
しかしながら、従来技術によれば、ウェハに第１層目の
主パターンを露光した時、縮小投影露光でリピートされ
たパターンのリピート精度を確認できない。However, according to the prior art, when the main pattern of the first layer is exposed on the wafer, it is not possible to confirm the repeat accuracy of the pattern repeated by reduction projection exposure.
また、リピート精度が確認されない才ま第２層目の主パ
ターンを重ねで露光した場合、第１゜第２層目の主パタ
ーンのいずれのリピート精度が患いか判断できず、重ね
合せ不良として扱われている。In addition, if the main patterns of the second layer are exposed in an overlapping manner without confirming the repeat accuracy, it is not possible to determine which of the main patterns of the first and second layers has poor repeat accuracy, and it is treated as an overlay defect. It is being said.
更に、ウェーハステップアンドリピータと１：１プロジ
ェクションアライナ−を混用して、重ね合せ精度が悲く
なった場合、その原因がどちらであるかの判断をするこ
とが困難である。Furthermore, when a wafer step-and-repeater and a 1:1 projection aligner are used together and the overlay accuracy deteriorates, it is difficult to determine which is the cause.
本発明は、上記事情に鑑みてなされたもので、主パター
ンの露光の前後に互いに対をなす補助パターンを露光す
ることによって、これら一対の補助パターン相互の位置
関係を検出し、もって主パターンのリピート精度を測定
可能にする管種々の効果を得られるパターンの形成方法
を提供することを目的とするものである。The present invention has been made in view of the above circumstances, and by exposing paired auxiliary patterns before and after the exposure of the main pattern, the mutual positional relationship between these pairs of auxiliary patterns is detected, and thereby the main pattern is exposed. It is an object of the present invention to provide a method for forming a pattern that enables measurement of repeat accuracy and obtains various effects.
本発明は、ウェハの主パターン形成予定領域外に少なく
とも１つの第１の補助パターンを露光により形成した後
、同ウェハに主パターンを露光により形成し、しかる後
同ウェハの主パターン形成仙域外に前記第１０） ｑ’
＋’Ａ助パターンと対をなす第２の補助パターンを露光
により形成することにより、主パターンのリピート精＋
１（７）測定を可能にする管種々の効果を得ることを骨
子とする。In the present invention, after at least one first auxiliary pattern is formed by exposure outside the main pattern formation area of the wafer, a main pattern is formed on the same wafer by exposure, and then the main pattern is formed outside the main pattern formation area of the wafer. Said No. 10) q'
By forming a second auxiliary pattern that pairs with the +'A auxiliary pattern by exposure, the repeat precision of the main pattern can be increased.
1(7) Tube that enables measurement The main point is to obtain various effects.
以下、本発明を第１図〜第５図を参押して説明する。 The present invention will be explained below with reference to FIGS. 1 to 5.
まず、第１図に示すウェハとしての８１基板１の主パタ
ーン形成予定領域外に、縮小投影露光装置用レティクル
の主パターン外に予め配置された第２図図示の第１の補
助パターン２を例えば３個露光した。つついで、呈パタ
ーンを、前記基板Ｉの各チップ３・・・にａ元し主パタ
ーン領域４を形成した。なお、この主パターン領域、４
は、第３図に示す如く第１の補助パターン２をマスク５
により被覆した状態で行なった。次いで、第１の補助パ
ターン２及び主パターンをマスキングしながら、旧基板
１の主パターン領域４の外にｍｌの補助パターン２と対
をなす第４図図示の第２の補助パターン５を３個露光し
た。First, the first auxiliary pattern 2 shown in FIG. 2, which has been placed in advance outside the main pattern formation area of the 81 substrate 1 as a wafer shown in FIG. Three pieces were exposed. Next, the pattern was applied to each chip 3 of the substrate I to form a main pattern region 4. Note that this main pattern area, 4
As shown in FIG. 3, the first auxiliary pattern 2 is covered with a mask 5.
The test was carried out in a state covered with Next, while masking the first auxiliary pattern 2 and the main pattern, three second auxiliary patterns 5 as shown in FIG. exposed.
しかして、本発明によれば、主パターンの露光の前後に
互いに対をなす補助パターン２，５を露光するため、こ
れら一対の補助パターン２゜５の相互の位置関係を検出
することによって、露光のスループットを現状のま才で
各層個々の主パターン及び縮小投影露光装置のリピート
精匪を測定することができる。According to the present invention, in order to expose the auxiliary patterns 2 and 5 that form a pair before and after the exposure of the main pattern, the exposure With the current throughput, it is possible to measure the individual main patterns of each layer and the repeat precision of the reduction projection exposure apparatus.
才た、上記と同様な理由により、各層間の精ンのｗｒ党
をする手間を省くことができる。For the same reason as mentioned above, it is possible to save the trouble of having to deal with the troubles between the various layers.
更に、ウェーハステップアンドリピータと１＝１プロジ
ェクションアライナ−を混用して、重ね合せ精度が悪く
なった場合、その原因がどちらであるか容易化判断する
ことができる。Furthermore, when a wafer step-and-repeater and a 1=1 projection aligner are used together and the overlay accuracy deteriorates, it is possible to easily determine which is the cause.
なお、本発明に係る補助パターンは、第２図及び第４図
図示の形状のものに限らず、第１゜第２の補助パターン
が互いに対をなす形状のものであれば伺でもよい。Note that the auxiliary pattern according to the present invention is not limited to the shape shown in FIGS. 2 and 4, but may be any shape as long as the first and second auxiliary patterns form a pair with each other.
以上詳述した如く本発明によれば、主パターン及び縮小
投影露光装置のリピート精度を測定可能にする等ｆｉな
の効果を有するパターンの形成方法を提供できるもので
ある。As described in detail above, according to the present invention, it is possible to provide a method for forming a pattern which has such effects as making it possible to measure the repeat accuracy of the main pattern and the reduction projection exposure apparatus.
第１図は主パターン領域及び補助パターンを形成した８
１基板の平面図、第２図は第１図図示の８１基版に露
光された第１の補助パターンの平面図、第３図は第１図
図示のＳｉ基板のチップの平面図、第４図は第１図図示
のＳｉ基板に露光された第２の補助パターンの平１面図
、第５図は第１、第２の補助パターンが一対となって露
光された状シーを示す平面図である。
１・・・Ｓｉ基板（ウェハ）、２．５・・・補助パター
ン、３・・・チップ、４・・・主パターン領域。
出願人代理人 弁理士 鈴 江 武 彦第 １ｖｌＪ
第４図
／
第５ｖｌＪFigure 1 shows 8 areas where the main pattern area and auxiliary patterns are formed.
1. FIG. 2 is a plan view of the first auxiliary pattern exposed on the 81 substrate shown in FIG. 1. FIG. 3 is a plan view of the chip of the Si substrate shown in FIG. 1. The figure is a plan view of the second auxiliary pattern exposed to the Si substrate shown in FIG. 1, and FIG. 5 is a plan view showing the state in which the first and second auxiliary patterns are exposed as a pair. It is. DESCRIPTION OF SYMBOLS 1... Si substrate (wafer), 2.5... Auxiliary pattern, 3... Chip, 4... Main pattern area. Applicant's agent Patent attorney Takehiko Suzue 1vlJ Figure 4/Figure 5vlJ
Claims (1)
第１の補助パターンを露光により形成する工程と、同ウ
ェハに主パターンを露光により形成する工程と、同ウェ
ハの主パターン形成領域外に前記第１の補助パターンと
対をなす第２の補助パターンを６元により形成すること
を特徴とするパターンの形成方法。forming at least one first auxiliary pattern by exposure outside the main pattern formation area of the wafer; forming a main pattern on the wafer by exposure; A method for forming a pattern, characterized in that a second auxiliary pattern paired with the auxiliary pattern is formed using six elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58138304A JPS6030136A (en) | 1983-07-28 | 1983-07-28 | Forming method of pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58138304A JPS6030136A (en) | 1983-07-28 | 1983-07-28 | Forming method of pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6030136A true JPS6030136A (en) | 1985-02-15 |
Family
ID=15218742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58138304A Pending JPS6030136A (en) | 1983-07-28 | 1983-07-28 | Forming method of pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6030136A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008133100A (en) * | 2006-11-28 | 2008-06-12 | Kyocera Mita Corp | Paper feeding device and image forming device mounted therewith |
-
1983
- 1983-07-28 JP JP58138304A patent/JPS6030136A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008133100A (en) * | 2006-11-28 | 2008-06-12 | Kyocera Mita Corp | Paper feeding device and image forming device mounted therewith |
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