KR950034720A - Ic다이와 기판간의 본딩을 위한 다이 부착물 큐어 방법 및 이 방법에 의한 프로덕트 - Google Patents

Ic다이와 기판간의 본딩을 위한 다이 부착물 큐어 방법 및 이 방법에 의한 프로덕트 Download PDF

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KR950034720A
KR950034720A KR1019950013802A KR19950013802A KR950034720A KR 950034720 A KR950034720 A KR 950034720A KR 1019950013802 A KR1019950013802 A KR 1019950013802A KR 19950013802 A KR19950013802 A KR 19950013802A KR 950034720 A KR950034720 A KR 950034720A
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South Korea
Prior art keywords
die attach
attach film
solvent
substrate
product
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KR1019950013802A
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English (en)
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KR100338018B1 (ko
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티. 홀스테드 린덴
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윌리엄 이. 힐러
텍사스 인스트루먼츠 인코포레이티드
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Publication of KR950034720A publication Critical patent/KR950034720A/ko
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Publication of KR100338018B1 publication Critical patent/KR100338018B1/ko

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

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Abstract

IC 다이들(16)을 기판들에 본딩하기 위한 다이 부착물(attach)을 큐어(cure) 함에 있어 설비(fixture)를 전혀 사용하지 않는 방법에 있어서는, 리드 프레임 다이 지지 패드나 인쇄 회로 보드(PCB;12)상에 다이(16)소자를 배치하기에 앞서, 열가소성 다이 부착 막의 상측 표면과 하측 표면에 솔벤트를 적용한다. 솔벤트 건조시, 다이 부착 막(14)이 IC 다이(16) 및 리드 프레임, 또는 IC 다이(16) 및 인쇄 회로 보드(PCB;12)에 본딩된다.

Description

IC 다이와 기판간의 본딩을 위한 다이 부착물 큐어 방법 및 이 방법에 의한 프로덕트
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제8도는 본 발명의 실시예에 따라, 패키징하기 전에 리드 프레임에 백 본딩 및 와이어 본딩된 반도체 장치를 위에서 본 도면.

Claims (20)

  1. 기판을 제공하는 단계; 다이 부착(die attach) 막을 제공하는 단계; 상기 다이 부차 막을 연화(soften)시키기 위해서 솔벤트를 상기 다이 부착 막의 양면에 코팅하는 단계; 상기 솔벤트 코팅된 다이 부착 막을 상기 기판 상에 배치하는 단계; 반도체 장치를 상기 솔벤트 코팅된 다이 부착 막 상에 배치되는 단계; 및 상기 솔벤트를 건조시키도록 하는 단계의 공정으로 형성된 것을 특징으로 하는 프로덕트(product).
  2. 제1항에 있어서, 상기 기판은 인쇄 배선 보드(PWB;Printed Wiring Board)인 것을 특징으로 하는 프로덕트.
  3. 제1항에 있어서, 상기 기판은 리드 프레임 다이 패드 지지체인 것을 특징으로 하는 프로덕트.
  4. 제1항에 있어서, 상기 다이 부착 막은 열가소성 막인 것을 특징으로 하는 프로덕트.
  5. 제1항에 있어서, 상기 솔벤트를 건조시키도록 하는 상기 단계는 건조를 촉진시키기 위해서 상기 인쇄배선 보드(PWB)의 글래스 전이 온도(Tg) 이하의 온도에서 짧은 시간 구간 동안 상기 인쇄 배선 보드(PWB), 상기 다이 부착 막 및 상기 반도체 장치를 베이킹하는 단계를 더 포함하는 것을 특징으로 하는 프로덕트.
  6. 제1항에 있어서, 상기 솔벤트 코팅된 다이 부착 막은 상기 기판 상의 열(thermal) 패드들 상에 배치되는 것을 특징으로 하는 프로덕트.
  7. 기판을 제공하는 단계; 다이 부착 막을 제공하는 단계; 상기 다이 부착 막을 연화시킬 수 있는 솔벤트를 상기 기판의 일부에 코팅하는 단계; 상기 다이 부착 막을 연화시킬 수 있는 솔벤트를 반도체 장치의 뒷면에 코팅하는 단계; 상기 다이 부착 막을 상기 기판의 솔벤트 부분 상에 배치하는 단계; 상기 반도체 장치를 상기 다이 부착 막 상에 배치하는 단계; 및 상이 솔벤트 코팅된 다이 부착 막을 건조시키도록 하는 단계의 공정에 의해 형성된 것을 특징으로 하는 프로덕트.
  8. 제7항에 있어서, 상기 기판은 인쇄 배선 보드(PWB)인 것을 특징으로 하는 프로덕트.
  9. 제7항에 있어서, 상기 기판은 리드 프레임 다이 패드 지지체인 것을 특징으로 하는 프로덕트.
  10. 제7항에 있어서, 상기 다이 부착 막은 열가소성 막인 것을 특징으로 하는 프로덕트.
  11. 제7항에 있어서, 상기 솔벤트 코팅된 다이 부착 막을 건조시키도록 하는 사익 단계는 건조를 촉진시키기 위해서 사익 인쇄 배선 보드(PWB)의 글래스 전이 온도(Tg) 이하의 온도에서 짧은 시간 구간 동안 상기 인쇄 배선 보드(PWB), 상기 다이 부착 막 및 상기 반도체 장치를 베이킹하는 단계를 더 포함하는 것을 특징으로 하는 프로덕트.
  12. 기판을 제공하는 단계; 다이 부착 막을 제공하는 단계; 상기 다이 부착 막을 연화시킬 수 있는 솔벤트를 상기 기판의 일부에 코팅하는 단계; 상기 다이 부착 막을 상기 기판의 상기 코팅된 부분 상에 배치하는 단계; 상기 다이 부착 막을 연화시킬 수 있는 솔벤트를 상기 다이 부착 막의 노출된 부분에 코팅하는 단계; 상기 반도체 장치를 상기 다이 부착 막 상에 배치하는 단계; 및 상기 솔벤트를 건조시키도록 하는 단계의 프로세스에 의해 형성된 것을 특징으로 하는 프로덕트.
  13. 제12항에 있어서, 상기 기판은 인쇄 배선 보드(PWB)인 것을 특징으로 하는 프로덕트.
  14. 제12항에 있어서, 상기 기판은 리드 프레임 다이 패드 지지체인 것을 특징으로 하는 프로덕트.
  15. 제12항에 있어서, 상기 다이 부착 막은 열가소성 막인 것을 특징으로 하는 프로덕트.
  16. 제12항에 있어서, 상기 솔벤트를 건조시키도록 하는 상기 단계는 건조를 촉진시키기 위해 상기 인쇄 배선 모드(PWB)의 글래스 전이 온도(Tg) 이하의 온도에서 짧은 시간 구간 동안 상기 인쇄 배선 모드(PWB), 상기 다이 부착 막 및 상기 반도체 장치를 베이킹하는 단계를 더 포함하는 것을 특징으로 하는 프로덕트.
  17. 제1항에 있어서, 어떠한 설비들도 상기 솔벤트가 건조되는 동안 상기 반도체 장치에 압력을 가하는데 사용되지 않는 것을 특징으로 하는 프로덕트.
  18. 제7항에 있어서, 어떠한 설비들도 상기 솔벤트가 건조되는 동안 상기 반도체 장치에 압력을 가하는데 사용되지 않는 것을 특징으로 하는 프로덕트.
  19. 제12항에 있어서, 어떠한 설비들도 상기 솔벤트가 건조되는 동안 상기 반도체 장치에 압력을 가하는데 사용되지 않는 것을 특징으로 하는 프로덕트.
  20. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950013802A 1994-05-31 1995-05-30 Ic다이와기판간의본딩을위한다이부착물을설비없이큐어하는방법 KR100338018B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/250977 1994-05-31
US08/250,977 US5471017A (en) 1994-05-31 1994-05-31 No fixture method to cure die attach for bonding IC dies to substrates
US8/250,977 1994-05-31

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KR950034720A true KR950034720A (ko) 1995-12-28
KR100338018B1 KR100338018B1 (ko) 2002-11-30

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US6232150B1 (en) 1998-12-03 2001-05-15 The Regents Of The University Of Michigan Process for making microstructures and microstructures made thereby
US6541872B1 (en) * 1999-01-11 2003-04-01 Micron Technology, Inc. Multi-layered adhesive for attaching a semiconductor die to a substrate
US8188375B2 (en) * 2005-11-29 2012-05-29 Tok Corporation Multilayer circuit board and method for manufacturing the same
US20080203566A1 (en) * 2007-02-27 2008-08-28 Chao-Yuan Su Stress buffer layer for packaging process

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US4029628A (en) * 1974-05-22 1977-06-14 The United States Of America As Represented By The Secretary Of The Navy Bonding material for planar electronic device
CA1290676C (en) * 1987-03-30 1991-10-15 William Frank Graham Method for bonding integrated circuit chips
US5057900A (en) * 1988-10-17 1991-10-15 Semiconductor Energy Laboratory Co., Ltd. Electronic device and a manufacturing method for the same
US5205036A (en) * 1988-10-17 1993-04-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device with selective coating on lead frame
EP0384704A3 (en) * 1989-02-21 1991-05-08 General Electric Company Die attach material and die attach process
US5225023A (en) * 1989-02-21 1993-07-06 General Electric Company High density interconnect thermoplastic die attach material and solvent die attach processing
US5204399A (en) * 1989-03-09 1993-04-20 National Starch And Chemical Investment Holding Corporation Thermoplastic film die attach adhesives
US5006575A (en) * 1989-10-20 1991-04-09 E. I. Du Pont De Nemours And Company Die attach adhesive composition
US5371328A (en) * 1993-08-20 1994-12-06 International Business Machines Corporation Component rework

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