KR950022599A - PCM Data Conversion and Demultiplexing Circuit for Electronic Switching System - Google Patents

PCM Data Conversion and Demultiplexing Circuit for Electronic Switching System Download PDF

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Publication number
KR950022599A
KR950022599A KR1019930026455A KR930026455A KR950022599A KR 950022599 A KR950022599 A KR 950022599A KR 1019930026455 A KR1019930026455 A KR 1019930026455A KR 930026455 A KR930026455 A KR 930026455A KR 950022599 A KR950022599 A KR 950022599A
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KR
South Korea
Prior art keywords
pair
conversion
demultiplexing
parallel
data
Prior art date
Application number
KR1019930026455A
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Korean (ko)
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KR0143207B1 (en
Inventor
차현열
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정장호
엘지정보통신 주식회사
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Priority to KR1019930026455A priority Critical patent/KR0143207B1/en
Publication of KR950022599A publication Critical patent/KR950022599A/en
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Publication of KR0143207B1 publication Critical patent/KR0143207B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q1/00—Details of selecting apparatus or arrangements
    • H04Q1/18—Electrical details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M2201/00—Electronic components, circuits, software, systems or apparatus used in telephone systems
    • H04M2201/30—PCM

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

본 발명은 전전자 교환기용 PCM데이타 변환 및 역다중화 회로에 관한 것으로, 특히 하나의 보드에 실장이 가능한 간단한 구조를 갖는 전전자 교환기용 PCM 데이타 변환 및 역다중화회로에 관한 것이다. 본 발명의 전전자 교환기용 PCM데이타 변환 및 역다중 회로는 디지탈 음성 데이타 및 콘트롤 데이타를 수시하기 위한 한쌍의 입력랫치와 수신된 상기 디지탈 음성 및 콘트롤 데이타에 응답하여 8단계의 음성데이타 감쇄 및 A-로오/U-로우 변환을 수행하기 위한 한쌍의 룩업테이블 수단과, 상기 각 룩업 테이블 수단의 출력을 랫치하기 위한 한쌍의 랫치와 상기 각 랫치를 통해 입력된 병렬 데이타로 부터 병렬/직렬 변환과 역다중화를 수행하여 각각 32개의 직렬 서브하이웨이 구동출력을 발생하기 위한 한쌍의 병렬/직렬 변환 및 역다중화 수단과, 상기 각각 병렬/직렬 변환 및 역다중화 수단으로부터 발생된 32 서브하이웨이 구동출력을 수신하여 출력하기 위한 한쌍의 출력버퍼로 구성된다.The present invention relates to PCM data conversion and demultiplexing circuit for all-electronic exchange, and more particularly, to PCM data conversion and demultiplexing circuit for all-electronic exchange having a simple structure that can be mounted on one board. The PCM data conversion and demultiplex circuit for an electronic switching system of the present invention has a pair of input latches for receiving digital voice data and control data, and 8 steps of voice data attenuation and A- in response to the received digital voice and control data. Parallel / serial conversion and demultiplexing from a pair of lookup table means for performing row / U-row conversion, a pair of latches for latching the output of each lookup table means, and parallel data inputted through each latch Receiving and outputting a pair of parallel / serial conversion and demultiplexing means for generating 32 serial subhighway driving outputs respectively, and 32 subhighway driving outputs generated from the parallel / serial conversion and demultiplexing means, respectively. It consists of a pair of output buffers.

Description

전전자 교환기용 PCM데이타 변환 및 역다중화 회로.PCM data conversion and demultiplexing circuit for electronic exchanger.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 종래의 역다중화회로의 블록도,2 is a block diagram of a conventional demultiplexing circuit,

제3도는 본 발명의 바람직한 일실시예에 따른 PCM 데이타 변환 및 역다중화회로의 블록도이다.3 is a block diagram of a PCM data conversion and demultiplexing circuit in accordance with a preferred embodiment of the present invention.

Claims (2)

디지탈 음성 데이타 및 콘트롤데이타를 수신하기 위한 한쌍의 입력랫치와 수신된 상기 디지탈 음성 및 콘트롤 데이타에 응답하여 8단계의 음성데이타 감쇄 및 A-로오/U-로우 변환을 수행하기 위한 한쌍의 룩업테이블 수단과, 상기 각 룩업 테이블 수단의 출력을 랫치하기 위한 한쌍의 랫치와, 상기 각 랫치를 통해 입력된 병렬 데이타로 부터 병렬/직렬 변환과 역다중화를 수행하여 각각 32개의 직렬 서브하이웨이 구동출력을 발생하기 위한 한쌍의 병렬/직렬 변환 및 역다중화 수단과, 상기 각각 병렬/직렬 변환 및 역다중화 수단으로부터 발생된 32 서브하이웨이 구동출력을 수신하여 출력하기 위한 한쌍의 출력버퍼로 구성되는 것을 특징으로 하는 전전자 교환기용 PCM데이타 변환 및 역다중화 회로.A pair of input latches for receiving digital voice data and control data, and a pair of lookup table means for performing 8-step voice data attenuation and A-Roo / U-low conversion in response to the received digital voice and control data. And a pair of latches for latching the output of each lookup table means, and performing parallel / serial conversion and demultiplexing from the parallel data input through the respective latches to generate 32 serial subhighway driving outputs, respectively. And a pair of output buffers for receiving and outputting 32 subhighway driving outputs generated from the parallel / serial conversion and demultiplexing means, respectively, and a pair of parallel / serial conversion and demultiplexing means. PCM data conversion and demultiplexing circuit for the exchange. 제1항에 있어서 8.192MHz와 8KHz주파수 신호를 수신하여 상기 한쌍의 랫치와 병렬/직렬 변환 및 역다중화 수단에 대한 클록을 제공하기 위한 클록 발생회로를 더 포함하는 것을 특징으로 하는 전전자 교환기용 PCM데이타 변환 및 역다중화 회로.2. The PCM of claim 1, further comprising a clock generation circuit for receiving the 8.192 MHz and 8 KHz frequency signals and providing a clock for the pair of latches and the parallel / serial conversion and demultiplexing means. Data Conversion and Demultiplexing Circuits. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930026455A 1993-12-04 1993-12-04 Full electronic telephone exchange pcm data change & inverted multiplex KR0143207B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930026455A KR0143207B1 (en) 1993-12-04 1993-12-04 Full electronic telephone exchange pcm data change & inverted multiplex

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930026455A KR0143207B1 (en) 1993-12-04 1993-12-04 Full electronic telephone exchange pcm data change & inverted multiplex

Publications (2)

Publication Number Publication Date
KR950022599A true KR950022599A (en) 1995-07-28
KR0143207B1 KR0143207B1 (en) 1998-08-17

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KR1019930026455A KR0143207B1 (en) 1993-12-04 1993-12-04 Full electronic telephone exchange pcm data change & inverted multiplex

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100315187B1 (en) * 1999-10-18 2001-11-26 윤종용 Method to communicate between μ-law communication system and A-law communication system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020063690A (en) * 2001-01-30 2002-08-05 삼성전자 주식회사 Pcm data conversion apparatus and method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100315187B1 (en) * 1999-10-18 2001-11-26 윤종용 Method to communicate between μ-law communication system and A-law communication system

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KR0143207B1 (en) 1998-08-17

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