KR950021238A - Method for manufacturing field effect semiconductor device - Google Patents

Method for manufacturing field effect semiconductor device Download PDF

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Publication number
KR950021238A
KR950021238A KR1019930028890A KR930028890A KR950021238A KR 950021238 A KR950021238 A KR 950021238A KR 1019930028890 A KR1019930028890 A KR 1019930028890A KR 930028890 A KR930028890 A KR 930028890A KR 950021238 A KR950021238 A KR 950021238A
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KR
South Korea
Prior art keywords
film
forming
oxide film
semiconductor device
transition metal
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KR1019930028890A
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Korean (ko)
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KR0137734B1 (en
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박상훈
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김주용
현대전자산업 주식회사
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Priority to KR1019930028890A priority Critical patent/KR0137734B1/en
Publication of KR950021238A publication Critical patent/KR950021238A/en
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Publication of KR0137734B1 publication Critical patent/KR0137734B1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히, 소자를 소형화하면서 실리콘 기판과 금속배선의 접합부에서 발생하는 스파이킹 현상을 방지하도록 실리콘 기판과 금속배선의 연결부위를 단결정 실리콘막으로 형성하고 그 상부에 전이 금속막을 증착한 후 금속배선을 형성시킴으로 금속원자들이 집적 실리콘 기판과 접합되지 않고 소오스/드레인의 상부 전이 금속막과 접합을 하도록 하여 얕은 접합을 형성할 수 있도록 한 전계 효과형 반도체 소자의 제조방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a connection between the silicon substrate and the metal wiring is formed of a single crystal silicon film in order to reduce the size of the device and to prevent spiking occurring at the junction between the silicon substrate and the metal wiring. After the deposition of the transition metal film on the upper portion of the field effect type semiconductor device to form a metal junction by forming a metal wiring to be bonded to the upper transition metal film of the source / drain rather than being bonded to the integrated silicon substrate to form a shallow junction It is a manufacturing method.

Description

전계 효과형 반도체 소자의 제조방법Method for manufacturing field effect semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2G도는 본 발명의 전계 효과형 반도체 소자의 형성방법에 따른 공정 단계를 도시한 단면도.2A to 2G are sectional views showing the process steps according to the method for forming the field effect semiconductor device of the present invention.

Claims (3)

반도체 소자제조 공정에 있어서 실리콘 기판상에 패드용 산화막과 제1질화막 패턴을 형성한 후 필드 산화막을 형성하는 단계와, 상기 제1질화막 패턴을 제거하고 제2질화막을 전체구조의 상부에 형성한 후, 식각공정으로 제2질화막이 필드 산화막 상부에만 남도록 하는 단계와, 상기 제2질화막을 식각 정지층으로 하여 실리콘 기판내의 일정한 깊이로 트렌치를 형성하는 단계와, 실리콘 기판에 남아있는 패드용 산화막을 제거하고, 에피택셜 단결정 실리콘을 노출된 실리콘 기판과 제2질화막 상부에 형성하는 단계와, 상기 에피택셜 단결정 실리콘의 일정부분을 식각하여 에피택셜 단결정 실리콘 패턴을 형성하고 전체 구종의 상부에 게이트 산화막 및 폴리실리콘막을 형성하는 단계와, 상기 게이트 산화막과 폴리 실리콘막을 식각하여 게이트 전극을 형성한 후 N+이온 주입을 실시하는 단계와, 전체 구조에 산화막을 증착한 후 이방성 블랭키트 식각으로 식각하여 에피택셜 단결정 실리콘 패턴과 게이트 전극 측벽에 측면 산화막을 형성한 후 N+이온을 주입하여 소오스/드레인을 형성하는 단계와, 상기 소오스/드레인과 게이트 전극 상부에 전이 금속막을 선택 증착하는 단계와, 상기 미반응 전이 금속막을 제거하기 위하여 화학용액의 혼합용액에서 일정시간 세정하는 단계와, 절연 산화막을 전체구조의 상부에 형성한 후, 상기 소오스/드레인 상부의 절연 산화막을 식각하여 전이 금속막이 노출된 콘택홀을 형성하고, 상기 콘택홀을 통하여 상기 전이금속막에 콘택되는 금속배선을 형성하는 단계를 포함하는 것을 특징으로 하는 전계 효과형 반도체 소자의 제조방법.Forming a pad oxide film and a first nitride film pattern on a silicon substrate in a semiconductor device manufacturing process, forming a field oxide film, removing the first nitride film pattern, and forming a second nitride film on the entire structure Forming a trench at a predetermined depth in the silicon substrate by removing the second nitride film from the silicon oxide substrate by using the second nitride film as an etch stop layer, and removing the pad oxide film remaining on the silicon substrate. And forming epitaxial single crystal silicon on the exposed silicon substrate and the second nitride film, etching a portion of the epitaxial single crystal silicon to form an epitaxial single crystal silicon pattern, and forming a gate oxide film and a poly on top of the entire sphere. Forming a silicon film and etching the gate oxide film and the polysilicon film to form a gate electrode; Comprising the steps of: after performing N + ion implantation, and then after depositing an oxide film on the entire structure is etched anisotropically block raengki bit etching to form a side of the oxide film on the epitaxial single crystal silicon pattern and the gate electrode side wall by implanting N + ions Forming a source / drain, selectively depositing a transition metal film on the source / drain and the gate electrode, washing for a predetermined time in a mixed solution of a chemical solution to remove the unreacted transition metal film, and After the oxide film is formed on the entire structure, the insulating oxide film on the source / drain is etched to form a contact hole in which the transition metal film is exposed, and a metal wiring contacted to the transition metal film through the contact hole. Method of manufacturing a field effect semiconductor device comprising the step. 제1항에 있어서, 상기 미반응 전이 금속막을 제거하기 위해 황산과 과산화 수소의 혼합용액에서 일정시간 세정하는 것을 특징으로 하는 전계 효과형 반도체 소자의 제조방법.The method of manufacturing a field effect type semiconductor device according to claim 1, wherein the unreacted transition metal film is washed for a predetermined time in a mixed solution of sulfuric acid and hydrogen peroxide. 제1항에 있어서, 상기 제2질화막의 증착 두께는 500 옹그스트롱(Å)인 것을 특징으로 하는 전계 효과형 반도체 소자의 제조방법.The method of manufacturing a field effect type semiconductor device according to claim 1, wherein the deposition thickness of the second nitride film is 500 angstroms. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930028890A 1993-12-21 1993-12-21 Mosfet fabrication method KR0137734B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930028890A KR0137734B1 (en) 1993-12-21 1993-12-21 Mosfet fabrication method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930028890A KR0137734B1 (en) 1993-12-21 1993-12-21 Mosfet fabrication method

Publications (2)

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KR950021238A true KR950021238A (en) 1995-07-26
KR0137734B1 KR0137734B1 (en) 1998-06-01

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KR0137734B1 (en) 1998-06-01

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